The ASUS ROG Phone 9 has recently been spotted on Geekbench where it appears to be powered by the new Qualcomm chipset.

The post ASUS ROG Phone 9 spotted on Geekbench with Qualcomm’s latest chipset appeared first on Phandroid.

Shared by Gator Boys star Paul Bedard, the viral video shows the alligator emerging from his den to the tune of the iconic song.

Zomato witnesses approximately 400,000 cancelled orders monthly which prompted it to launch the initiative.

A guidance has been issued to the wealthier students with a list of actions they need to follow to create an inclusive environment.

Positioned near the side of her head, the eye provides an expansive field of vision, while a thick layer of protective blubber shields it from harm and maintains warmth.

Children's Day, also known as 'Bal Diwas', is celebrated annually on November 14 in India. The day is celebrated to appreciate and acknowledge children as they are the future of the county.

A Bengaluru-based entrepreneur recently took to social media to jokingly explain how his daily commute on bike taxes in the city doubles as an unexpected fitness routine.

US-based comedian Austin Nasso is going viral online for his hilarious impersonation of US-President-elect Donald Trump during a fictional visit to India.

By celebrating Children's Day as Bal Diwas, India reinforced the cultural and emotional significance of the day, making it a uniquely Indian celebration rooted in national pride and values.

[SAPS] - Five suspects are appearing in the Kariega Magistrate's Court today, after they were arrested and found in possession of cycads with an estimated value of R1 Million on Friday 08 November 2024.

[GroundUp] Former Lavender Hill gangster died on 29 October

[The Conversation Africa] South Africa's finance minister, Enoch Godongwana, announced in his October mid-term budget policy statement that cabinet had approved funding for an early retirement programme to reduce the public sector wage bill. R11 billion (about US$627 million) will be allocated over the next two years to pay for the exit costs of 30,000 civil servants while retaining critical skills and promoting the entry of younger talent.

[SAnews.gov.za] With the United Nations Framework Convention on Climate Change (COP29) taking place this week, South Africa expects the COP29 Presidency to enhance efforts to finalise the New Collective Quantified Goal on Finance (NCQG), which is a matter of great importance for developing economies.

[Premium Times] In September, Tyla made headlines at the MTV Video Music Awards (VMAs) for winning the "Best Afrobeats," but she stirred debate by clarifying that she identified with the Amapiano genre rather than Afrobeats

[State Department] U.S. Ambassador-at-Large to Monitor and Combat Trafficking in Persons Cindy Dyer will travel to Madagascar November 13-16 and South Africa November 17-21.

[Daily Maverick] Office of the Chief Justice reveals Constitutional Court has been unable to sit because of unreliable water supply. This article is free to read.Sign up for free or sign in to continue reading.Unlike our competitors, we don't force you to pay to read the news but we do need your email address to make your experience better.Create your free account or sign in FAQ | Contact Us Nearly there! Create a password to finish signing up with us: You want to receive First Thing, our flagship daily newsletter. Opt

[COSATU] The Congress of South African Trade Unions (COSATU) is deeply concerned by the Minister for Communications and Digital Technologies, Mr. S. Malatsi's sudden withdrawal of the South African Broadcasting Corporation (SABC) SOC Ltd Bill from Parliament where it was being engaged upon by the National Assembly's Portfolio Committee: Communications and Digital Technologies.

[The Conversation Africa] Despite the flaws in the latest novel by South African writer Nthikeng Mohlele, there is something alluring about Revolutionaries' House. It is Mohlele's most political novel, and the parallels drawn between love and politics - and their pitfalls - are intriguing.

PCI-SIG DevCon 2024 was a great success for Cadence. We posted the blog, Cadence Demonstrates Complete PCIe 7.0 Solution at PCI-SIG DevCon ‘24 a day before the event to advertise our IP solutions for PCIe 7.0, which resulted in a lot of extra traffic at our booth. All of the attendees were excited to see Cadence demonstrate the robustness of 128GT/s PCIe 7.0 IP's TX and RX capabilities over a real-world, low-latency, non-retimed, linear optics connector. We achieved and maintained a consistent, impressive pre-FEC BER of ~3E-8 (PCIe spec requires 1E-6) for the entire duration of the event, spanning over two full days with no breaks. This provides an ample margin for RS FEC. As seen in the picture below, the receiver Eye PAM4 histograms have good linearity and margin. This is the world’s first stable demonstration of 128 GT/s TX and RX over off-the-shelf optical connectors—by far the main attraction of DevCon this year.

Cadence 128 GT/s TX and RX capability over optics

Block diagram of Cadence PHY for PCIe 7.0 128 GT/s demo setup with linear pluggable optics

As a leader in PCIe, our PCIe controller architect Anish Mathew shared his valuable insights on an important topic: “Impact of UIO ECN on PCIe Controller Design and Performance,” highlighting the strides made by the Cadence design team in achieving this implementation.

Anish Mathew presenting “Impact of UIO ECN on PCIe Controller Design and Performance”

In summary, Cadence had a dominating presence on the demo floor with a record number of PCIe demos:

• PCIe 7.0 over optics
• PCIe 7.0 electrical
• PCIe 6.0 RP/EP interop back-to back
• PCIe 6.0 protocol in FLIT mode with Lecroy Exerciser (at Cadence booth)
• PCIe 6.0 protocol in FLIT mode (at the Lecroy booth)
• PCIe 6.0 JTOL with Anritsu and Tektronix equipment (at Tektronix booth)
• PCIe 6.0 protocol with Viavi Protocol Analyzer (at Viavi booth)
• PCIe 6.0 System Level Interop Demo with Gen5 platform (at SerialTek booth)

The Cadence team and its partners did a great job in coordinating and setting up the demos that worked flawlessly. This was the culmination of many weeks of hard work and dedication. Four different vendors featured our IP for PCIe 6.0. They attracted a lot of attention and drove traffic back to us.

Highlights of Cadence demos for PCIe 7.0 and 6.0

Cadence team at the PCI-SIG Developers Conference 2024

Thanks to everyone who attended the 32nd PCI-SIG DevCon. We really appreciate your interest in Cadence IP, and a big thanks to our partners and customers for all the positive feedback and for creating so much buzz for the Cadence brand.

Staying ahead of the curve is essential to meeting customer needs. Cadence has consistently demonstrated its commitment to innovation, and its latest IP portfolio available on TSMC's 3nm (N3) process is no exception. Today, rapid advancements in AI/ML, hyperscale computing (HPC), and the automotive industry are driving significant changes in technology. Let's explore the impressive array of IP that Cadence offers on this advanced node.

Memory Solutions: High-Speed and Power-Efficient

Cadence's DDR5 12.8G MRDIMM IP supports the highest speed grade Gen2 MRDIMMs and features a fully hardened PHY optimized to the customer's floorplan. The LPDDR5X IP is silicon-proven at 9.6Gbps and is ideal for power-sensitive applications, offering a fully integrated memory subsystem.

GDDR7: Leading the Way in Graphics Memory

Cadence has achieved a significant milestone with the world's first silicon-proven GDDR7 IP, supporting data rates up to 32Gbps. This IP offers the best price/performance ratio for AI interfaces, making it a game-changer in the graphics memory domain.

PCIe and CXL Solutions: Robust and Reliable

Cadence's PCIe 3.0 IP is a mature and production-proven solution available across a wide range of process nodes from 28nm to 3nm. It offers a versatile multi-link architecture for optimum SoC configurability and flexible use cases. The PCIe 6.0 and CXL 3.x solutions are silicon-proven, power-optimized, and highly robust, with jitter-tolerant capabilities. These IP are the only subsystem proven with eight lanes of controller and PHY in silicon, ensuring interoperability with leading test vendors and OEMs.

UCIe PHY: Setting New Standards

The UCIe PHY IP from Cadence are set to be generally available after successful silicon characterization in both standard and advanced package options on the TSMC N3 (3nm) process. These IP demonstrate significantly better power, performance, and area (PPA) metrics than the specifications, with a bit error rate (BER) better than 1E-27 compared to the spec of 1E-15. The power consumption is also notably lower than the spec limit, ensuring a simpler integration with a best-in-class power profile.

112G PHY IP: Pushing the Boundaries of Performance

Cadence's 112G PHY IP are designed to meet the demands of high-speed data transmission. The 112G-ULR PHY IP, characterized in the 3nm process, showcases exceptional performance with support for insertion loss over 45dB at data rates ranging from 1.25Gbps to 112.5Gbps. This IP is optimized for both power and area, making it a versatile choice for various applications. The 112G-VSR/MR PHY IP also stands out with its excellent power and performance metrics, making it ideal for short-reach applications and optical interconnects. Additionally, the 112G PAM4 PHY solutions cater to hyperscale, AI, HPC, and optics applications, featuring a mature DSP-based SerDes architecture with advanced techniques such as reflection cancellation.

Cadence's IP portfolio on TSMC N3 shows innovation and expertise to solve today's design challenges. From high-speed PHY IP to robust PCIe and CXL solutions and advanced memory IP, Cadence continues to lead the way in semiconductor IP development. These solutions not only meet but exceed industry standards, ensuring that customers can confidently achieve their design goals. Stay tuned for more updates on Cadence's groundbreaking advancements in semiconductor technology.

Learn more about Cadence IP and other silicon solutions.

Hi everyone,

I'm new to using Innovus and I'm encountering an issue while trying to perform the "init_design" command. My goal is to perform the place and route. Here are the commands I'm using:

``
set init_verilog ./test.v
set init_top_cell TEST
set init_pwr_net {VDD VDD_2 VDD_3}
set init_gnd_net {VSS VSSA}
set init_lef_file { /home/laumecha/uw_openroad_free45/pdk/Drexel-ECEC575/Encounter/NangateOpenCellLibrary/Back_End/lef/NangateOpenCellLibrary.lef}
set init_mmmc_file {./viewDefinition.tcl}
init_design
```

However, I receive the following error:

```
#% Begin Load netlist data ... (date=06/04 12:07:50, mem=1478.7M)
*** Begin netlist parsing (mem=1439.0M) ***
Created 0 new cells from 0 timing libraries.
Reading netlist ...
Backslashed names will retain backslash and a trailing blank character.
**ERROR: (IMPVL-209):   In Verilog file './test.v', check line 16 near the text # for the issue: 'syntax error'.  Update the text accordingly.
Type 'man IMPVL-209' for more detail.
Verilog file './test.v' has errors!  See above.

*** Memory Usage v#1 (Current mem = 1439.027M, initial mem = 634.098M) ***
#% End Load netlist data ... (date=06/04 12:07:50, total cpu=0:00:00.0, real=0:00:00.0, peak res=1478.7M, current mem=1478.7M)
**ERROR: (IMPVL-902):   Failed to read netlist ./test.v. See previous error messages for details.  Resolve the issues and reload the design.
```

However, the file works perfectly in Genus.

It seems there is a syntax error in my Verilog file at line 16, but I'm not sure how to resolve it. Any guidance or suggestions would be greatly appreciated.

Thanks in advance!

I am trying to install IC231 on RHEL 8 using installscape, however configuring keeps failing.

I tried to run the configuration file manually as suggested in one of the previous posts and it gives me following errors:

sh batch_configure.sh
/home/rs/cadence/installs/IC231/install/tmp/slconfig.sh: line 165: xterm: command not found
cat: ncvhdl23.03-d103lnx86_101124125631.stat: No such file or directory
rm: cannot remove 'ncvhdl23.03-d103lnx86_101124125631.stat': No such file or directory
/home/rs/cadence/installs/IC231/install/tmp/slconfig.sh: line 165: xterm: command not found
cat: ncvhdl64b23.03-d103lnx86_101124125631.stat: No such file or directory
rm: cannot remove 'ncvhdl64b23.03-d103lnx86_101124125631.stat': No such file or directory
/home/rs/cadence/installs/IC231/install/tmp/slconfig.sh: line 165: xterm: command not found
cat: oaRedist22.61-p003lnx86_101124125631.stat: No such file or directory
rm: cannot remove 'oaRedist22.61-p003lnx86_101124125631.stat': No such file or directory
/home/rs/cadence/installs/IC231/install/tmp/slconfig.sh: line 165: xterm: command not found
cat: amsEnv64b23.10-p043lnx86_101124125631.stat: No such file or directory
rm: cannot remove 'amsEnv64b23.10-p043lnx86_101124125631.stat': No such file or directory
/home/rs/cadence/installs/IC231/install/tmp/slconfig.sh: line 165: xterm: command not found
cat: ihdl64b23.10-p043lnx86_101124125631.stat: No such file or directory
rm: cannot remove 'ihdl64b23.10-p043lnx86_101124125631.stat': No such file or directory

I am not very well versed with Linux at the moment but trying. Could any one suggest something or point to what is missing?

Hi guys,

I see that inside VNC I can’t resize window boxes by mouse. While pressing the arrow at the box edge and dragging it nothing happens:

is it a bug, or setup change require?

Noted, it only happens when trying to resize window box from left and right side..

Thx

Hi,

I want to define a procedure that with @key, and I also want to restrict the variable's datatype, I tried with folloing but I received error in CIW

procedure(tt(handler @key str1 str2 "ssS")
  printf("handler: %L " handler)
)

tt('test)

The error is like: *Error* tt: argument for keyword ?str1 should be a symbol (type template = "ssS") at line 11 of file

Thanks,

James

Hello,

I was looking to destructively and efficiently modify a list that was passed in as an argument to a procedure, by prepending an item to the list.

I noticed that cons lets you do this efficiently, but the operation is non-destructive. Hence this wouldn't work if you are trying to modify a function's list parameter in place.

Here is an example of trying to add "0" to the front of a list:

Dear all, 

I'm trying to perform an LVS check using Calibre between a layout that was generated by Innovus and the initial netlist generated by Genus. However, once I hit Run LVS on Calibre, it reports the following warnings and recommends to stop the process:

Source netlist references but does not define more than 10 subckts:
DFD1BWP7T
DFKCND1BWP7T
DFKCNQD1BWP7T
DFKSND1BWP7T
DFQD1BWP7T
IND2D0BWP7T
INR2D0BWP7T
INVD0BWP7T
INVD2P5BWP7T
IOA21D0BWP7T
... (and more)

If I proceed the LVS process it shows lots of errors as shown in the following image:

Why Genus doesn't include the definition of those sub circuits in the generated netlist? Is this related to Flat/Hierarchy netlisting? 

I have included my Genus scripts as well as the generated netlist in the attachments (and here - if attachment don't work).

Many thanks,

Anas

Hi Cadence & forumers, 

I am running a conformal LEC with a flattened netlist against RTL. 

The run hang for 5 days at the "analyze abort" step which is automatically launched by the compare. 

The netlist is flattened at some levels so hierarchical flow which I tried didn't help much. The flattened/highly optimized netlist is from customer and the ultimate goal. How shall I proceed now? 

On the a side note, a test run with a hierarchical netlist from a simple DC "compile -map_effort medium" command finished after 1 day or so. 

Thank you! 

// Command: vpx compare -verbose -ABORT_Print -NONEQ_Print -TIMEstamp
// Starting multithreaded comparison ...
Comparing 241112 points in parallel.

// Multithreading Overhead: 38% Gates: 8501606/6168138
// Multithreaded processing completed.
================================================================================
Compared points PO DFF DLAT BBOX CUT Total
--------------------------------------------------------------------------------
Equivalent 1025 241638 30 75 21 242789
--------------------------------------------------------------------------------
Abort 0 124 0 0 0 124
================================================================================
Compare results of instance/output/pin equivalences and/or sequential merge
================================================================================
Compared points DFF Total
--------------------------------------------------------------------------------
Equivalent 204 204
================================================================================
// Warning: 512 DFFs/DLATs have 1 disabled clock port: skipped data cone comparison
// Resolving aborts by analyze abort...

We have a big circuit having 12K gates totally and trying to show it in one page slide visually. But it is so hard for us to shrink it down from gate-level to module-level. Do you have any function like these:

• Toggle wires on and off
• “Right click” elements and group them into black boxes
• Quickly left or right align elements to clean up pictures

Hi,

I'm looking to download Tensilica SDK for evaluation, but I can't get past the registration form:

Virtuoso Studio IC23.1 ISR9 production release is now available for download.(read more)

Hello Fellow PCB Designers,

We have a 10 layer PCB design that originated in Pads and was converted over to Allegro 17.4, this is an old design but is manufacturable and works perfectly fine.  When I try to generate a Gerber for the Top or Bottom layers

the Gerber comes out fine.  But Most of the middle layers are Etch's and via's for power and grounds, but the Gerber's come mostly blank, there might be some details, but in the Gerber view everything is displayed correctly.

The design does have many close spacings, I have not changed anything in the constrains manager yet, turned off a lot of the DRC's, but thinking there might be something wrong with the constrains.

  I find that the CSet is set to 2_18, not sure yet what this means, also there are many of these definitions, PCS 3,4,5,ect, are the same as CSet 2_18 any suggestions would be great, we are currently looking into this, have seen

that even small change in constraint manager can cause long processing and even Allegro crashing, this is a large project.

Thanks Much, Thanks, Mike Pollock.

I'm trying to use Jasper for checking parameter propagation in a large design. I have a list of top-level parameters, each with a HDL path of a module parameter somewhere lower in the hierarchy that's supposed to receive its value from the top-level module. The FPV app seems like an excellent tool for this, but elaborating the entire design in it is extremely time-consuming and memory-intensive. So, I'm trying to black-box everything but the interesting HDL paths. I thought using `elaborate -top dut_module_name -bbox_i * -no_bbox_i inst_foo -no_bbox_i inst_bar (...)` would work, but it doesn't. Jasper just starts flooding the log with warnings from modules that are definitely not on the whitebox list, and eventually dies due to insufficient memory. When I use -bbox_m * it correctly elaborates the top-level module with all of its sub-modules black-boxed. But then the -no_bbox_i switches have no effect. Could anyone suggest a working solution for this use case?

Hello All,

Following is the einstein's puzzle solved by cadence Incisive92  (solved in less than 3 seconds -> FAST!!!!!!)

Thanks,

Vinay Honnavara

Verification engineer at Keyu Tech

vinayh@keyutech.com

 // Author: Vinay Honnavara

// Einstein formulated this problem : he said that only 2% in the world can solve this problem
// There are 5 different parameters each with 5 different attributes
// The following is the problem

// -> In a street there are five houses, painted five different colors (RED, GREEN, BLUE, YELLOW, WHITE)

// -> In each house lives a person of different nationality (GERMAN, NORWEGIAN, SWEDEN, DANISH, BRITAIN)

// -> These five homeowners each drink a different kind of beverage (TEA, WATER, MILK, COFFEE, BEER),

// -> smoke different brand of cigar (DUNHILL, PRINCE, BLUE MASTER, BLENDS, PALL MALL)

// -> and keep a different pet (BIRD, CATS, DOGS, FISH, HORSES)


///////////////////////////////////////////////////////////////////////////////////////
// *************** Einstein's riddle is: Who owns the fish? ***************************
///////////////////////////////////////////////////////////////////////////////////////

/*
Necessary clues:

1. The British man lives in a red house.
2. The Swedish man keeps dogs as pets.
3. The Danish man drinks tea.
4. The Green house is next to, and on the left of the White house.
5. The owner of the Green house drinks coffee.
6. The person who smokes Pall Mall rears birds.
7. The owner of the Yellow house smokes Dunhill.
8. The man living in the center house drinks milk.
9. The Norwegian lives in the first house.
10. The man who smokes Blends lives next to the one who keeps cats.
11. The man who keeps horses lives next to the man who smokes Dunhill.
12. The man who smokes Blue Master drinks beer.
13. The German smokes Prince.
14. The Norwegian lives next to the blue house.
15. The Blends smoker lives next to the one who drinks water.
*/




typedef enum bit [2:0]  {red, green, blue, yellow, white} house_color_type;
typedef enum bit [2:0]  {german, norwegian, brit, dane, swede} nationality_type;
typedef enum bit [2:0]  {coffee, milk, water, beer, tea} beverage_type;
typedef enum bit [2:0]  {dunhill, prince, blue_master, blends, pall_mall} cigar_type;
typedef enum bit [2:0]  {birds, cats, fish, dogs, horses} pet_type;




class Einstein_problem;

    rand house_color_type house_color[5];
    rand nationality_type nationality[5];
    rand beverage_type beverage[5];
    rand cigar_type cigar[5];
    rand pet_type pet[5];
        rand int arr[5];
    
    constraint einstein_riddle_solver {
    
        
    
        foreach (house_color[i])
            foreach (house_color[j])
               if (i != j)
                house_color[i] != house_color[j];
        foreach (nationality[i])
            foreach (nationality[j])
               if (i != j)
                nationality[i] != nationality[j];
        foreach (beverage[i])
            foreach (beverage[j])
               if (i != j)
                beverage[i] != beverage[j];
        foreach (cigar[i])
            foreach (cigar[j])
               if (i != j)
                cigar[i] != cigar[j];
        foreach (pet[i])
            foreach (pet[j])
               if (i != j)
                pet[i] != pet[j];
    
    
        //1) The British man lives in a red house.
        foreach(nationality[i])
                (nationality[i] == brit) -> (house_color[i] == red);
                
        
        //2) The Swedish man keeps dogs as pets.
        foreach(nationality[i])
                (nationality[i] == swede) -> (pet[i] == dogs);
                
                
        //3) The Danish man drinks tea.        
        foreach(nationality[i])
                (nationality[i] == dane) -> (beverage[i] == tea);
        
        
        //4) The Green house is next to, and on the left of the White house.
        foreach(house_color[i])        
                 if (i<4)
                    (house_color[i] == green) -> (house_color[i+1] == white);
        
        
        //5) The owner of the Green house drinks coffee.
        foreach(house_color[i])
                (house_color[i] == green) -> (beverage[i] == coffee);
                
        
        //6) The person who smokes Pall Mall rears birds.
        foreach(cigar[i])
                (cigar[i] == pall_mall) -> (pet[i] == birds);
        
        
        //7) The owner of the Yellow house smokes Dunhill.
        foreach(house_color[i])
                (house_color[i] == yellow) -> (cigar[i] == dunhill);
        
        
        //8) The man living in the center house drinks milk.
        foreach(house_color[i])
                if (i==2) // i==2 implies the center house (0,1,2,3,4) 2 is the center
                    beverage[i] == milk;
        
        
        
        //9) The Norwegian lives in the first house.
        foreach(nationality[i])        
                if (i==0) // i==0 is the first house
                    nationality[i] == norwegian;
        
        
        
        //10) The man who smokes Blends lives next to the one who keeps cats.
        foreach(cigar[i])        
                if (i==0) // if the man who smokes blends lives in the first house then the person with cats will be in the second
                    (cigar[i] == blends) -> (pet[i+1] == cats);
        
        foreach(cigar[i])        
                if (i>0 && i<4) // if the man is not at the ends he can be on either side
                    (cigar[i] == blends) -> (pet[i-1] == cats) || (pet[i+1] == cats);
        
        foreach(cigar[i])        
                if (i==4) // if the man is at the last
                    (cigar[i] == blends) -> (pet[i-1] == cats);
        
        foreach(cigar[i])        
                if (i==4)
                    (pet[i] == cats) -> (cigar[i-1] == blends);
        
        
        //11) The man who keeps horses lives next to the man who smokes Dunhill.
        foreach(pet[i])
                if (i==0) // similar to the last case
                    (pet[i] == horses) -> (cigar[i+1] == dunhill);
        
        foreach(pet[i])        
                if (i>0 & i<4)
                    (pet[i] == horses) -> (cigar[i-1] == dunhill) || (cigar[i+1] == dunhill);
                    
        foreach(pet[i])        
                if (i==4)
                    (pet[i] == horses) -> (cigar[i-1] == dunhill);
                    


        //12) The man who smokes Blue Master drinks beer.
        foreach(cigar[i])
                (cigar[i] == blue_master) -> (beverage[i] == beer);
        
        
        //13) The German smokes Prince.
        foreach(nationality[i])        
                (nationality[i] == german) -> (cigar[i] == prince);
        

        //14) The Norwegian lives next to the blue house.
        foreach(nationality[i])
                if (i==0)
                    (nationality[i] == norwegian) -> (house_color[i+1] == blue);
        
        foreach(nationality[i])        
                if (i>0 & i<4)
                    (nationality[i] == norwegian) -> (house_color[i-1] == blue) || (house_color[i+1] == blue);
        
        foreach(nationality[i])        
                if (i==4)
                    (nationality[i] == norwegian) -> (house_color[i-1] == blue);
        

        //15) The Blends smoker lives next to the one who drinks water.            
        foreach(cigar[i])            
                if (i==0)
                    (cigar[i] == blends) -> (beverage[i+1] == water);
        
        foreach(cigar[i])        
                if (i>0 & i<4)
                    (cigar[i] == blends) -> (beverage[i-1] == water) || (beverage[i+1] == water);
                    
        foreach(cigar[i])        
                if (i==4)
                    (cigar[i] == blends) -> (beverage[i-1] == water);
        
    } // end of the constraint block
    


    // display all the attributes
    task display ;
        foreach (house_color[i])
            begin
                $display("HOUSE : %s",house_color[i].name());
            end
        foreach (nationality[i])
            begin
                $display("NATIONALITY : %s",nationality[i].name());
            end
        foreach (beverage[i])
            begin
                $display("BEVERAGE : %s",beverage[i].name());
            end
        foreach (cigar[i])
            begin
                $display("CIGAR: %s",cigar[i].name());
            end
        foreach (pet[i])
            begin
                $display("PET : %s",pet[i].name());
            end
        foreach (pet[i])
            if (pet[i] == fish)
                $display("THE ANSWER TO THE RIDDLE : The %s has %s ", nationality[i].name(), pet[i].name());
    
    endtask // end display
    
    
endclass




program main ;

    initial
        begin
            Einstein_problem ep;
            ep = new();
            if(!ep.randomize())
                $display("ERROR");
            ep.display();
        end
endprogram // end of main

        

Using the EMX solver, X-FAB design engineers can efficiently develop next-generation RF technology for the latest communication standards (including sub-6GHz 5G, mmWave, UWB, etc.), which are enabling technologies for communications and electric vehicle (EV) wireless applications. (read more)

Sample clues

18 across: Makoto Hagiwara and David Jung both claim to have invented it (7,6)

1 down: French impressionist who rejected that term (5)

3 down: Artificial surface used for playing hockey (9)

7 down: The sequel to Iliad (7)

12 down: Adipose tissue (4,3)

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Sample clues

6 across: Franchise revived by Frank Miller (6)

13 across: What Keanu Reeves and Zayed Khan have in common (5)

18 across: What Frank Sinatra and George Clooney have in common (6,6)

19 across: Dosa mix, for example (6)

2 down: Green, in a non-environmental way (7)

Extrowords © 2007 IndiaUncut.com. All rights reserved.
India Uncut * The IU Blog * Rave Out * Extrowords * Workoutable * Linkastic

Sample clues

5 down: Torso covering (6)

7 down: Government by rogues (12)

15 across: eBay speciality (7)

18 across: Demonic (8)

20 across: Common language (6,6)

Extrowords © 2007 IndiaUncut.com. All rights reserved.
India Uncut * The IU Blog * Rave Out * Extrowords * Workoutable * Linkastic

I have a small shape for connecting three SMD pads, but it won't connect to one of the pads (0.2x0.6 mm). Thermal relief connects are set to Full contact for SMD pin in Shape parameters, but that doesn't help.

However, if I decrease the Minimum aperture for gap width in Void controls in Shape parameters to something below 0.2 mm the shape connects to the pad. But it is a little contracted at the pad entrance. Just 0.002 mm. What is going on here? 

Tried to attach some pictures, but I get: "An error occurred. Please try again or contact your administrator.". Will try later again.

/F

Cyprus is ranked first in fDi’s Island Economies of the Future rankings, followed by the Dominican Republic and Sri Lanka. Cathy Mullan and Naomi Davies detail the results.

New York continues to reign as leader of fDi’s American Cities of the Future 2019/20 ranking. San Francisco retains second place with Toronto rising to third. Naomi Davies reports.

A more detailed look at fDi's judges’ top five American Cities of the Future 2019/20 for FDI strategy. Naomi Davies reports.

Research by fDi Intelligence reveals which countries receive more than their ‘expected share’ of FDI. 

London has been named fDi’s inaugural Fintech Location of the Future for 2019/20, followed by Singapore and Belfast. 

Singapore has retained its place at the top of fDi's Asia-Pacific Cities of the Future ranking, with Shanghai and Tokyo completing the top three list. 

The UAE's DMCC takes home the top prize in fDi’s Global Free Zones of the Year for a fifth consecutive year. 

Research by fDi Intelligence reveals which cities received the most tech start-up FDI relative to their population between 2016 and 2018, with European cities coming out on top.

Australia tops the FDI Strategy category of fDi's Tourism Locations of the Future 2019/20 rankings, followed by Costa Rica and Azerbaijan.

Lithuania's Go Vilnius has been named fDi’s IPA of the Year for 2019, and organisations from across the globe are commended for their investment promotion and economic development activities. 

A look at the results of fDi’s rankings throughout 2019 finds that Singapore and New York dominated the year’s league tables, followed by Shanghai, Tokyo and London