1 Croatian Kuna = 0.9739 Trinidad and Tobago Dollar

1 Peruvian Nuevo Sol = 1.9881 Trinidad and Tobago Dollar

The wind was a constant factor at the Ottawa University Invitational the last two days but the men's golf team battled to a fourth place finish.  In their first fall tournament of the season, Haskell Indian Nations University had to overcome a team high score of 333 on Monday at Eagle Bend Golf Course in Lawrence.  Head Coach Gary Tanner's squad would improve play by eight strokes Tuesday but it wasn't enough to make a big move on the final day of competition.  Kansas Wesleyan University won the tournament with a two-day total of 626 (304, 322) while KWU's Tyler Clark took the top individual honor with a 154 (76, 78).  However, HINU would not be far behind in this category as Josiah Kurley finished runner-up in the event with a 156 (79, 77).

The two-day golf event at the Kansas Wesleyan Fall Invitational saw similar results for the HINU squad.  The team of five - Josiah Kurley, Johnny Wright, Trevor Pueblo, Steven Harshberger, Brandon Thompson - each produced a score of 80 or above on a round during the tournament.  That inconsistency in competition play puzzles Head Coach Gary Tanner.

The final competition of the fall men's golf season was held at the Swope Memorial Golf Course in Kansas City.  Hosted by Avila University, the Indians were hoping to close out the event with a solid performance both Monday and Tuesday.  However, HINU could not break the habit which plagued them early in the season.

The most important part of the men's golf season is traditionally held in the spring when post-season competition can lead to a national championship.  Before the team entered the spring, Head Golf Coach Gary Tanner recognized four players for their past performance at a recent home volleyball match.

Haskell Indian Nations University is in the midst of the spring golf season and Head Coach Gary Tanner is hoping they save their best for last.  Already, the Indians have played in three events and have just completed their fourth at the Bethel Spring Invitational.  "We can't make any progress if we shoot in the 80's," said Tanner.  "We've got the golfers to compete but we've got to be consistent throughout the course to make a run at the top."

Lawrence, Kansas – The Haskell men's golf team finished eighth at the Ottawa Invitational held at Eagle Bend Golf Course on Tuesday evening. The Indians finished with a two round score of 678. 

Lawrence, Kansas – The Haskell men's golf team finished 8th out of 9 teams at the Ottawa Spring Invitational held at Eagle Bend Golf Course on Monday. The Indians finished with a round score of 344 and the second round was cancelled due to snow on the course. 

Maryville, MO – The Haskell Men's golf team competed in the Graceland Invitational which was cut short due to inclement weather conditions on the second day. 

Lawrence, Kansas – The Haskell men's golf team finished 14th out of 16 teams in the Bethel Tournament held at Hesston Municipal Golf Park in Hesston, Kansas on Saturday. The Indians finished with a round score of 345 and the second round score of 334 with a total team score 679. 

Lawrence, Kansas – The Haskell men's golf team finished 9th out of 11 teams in the Baker Tournament held at Eagle Bend Golf Course in Lawrence, Kansas on Monday and Tuesday. The Indians finished with a round scores of 330, 332, and 325 with a total team score 987.

LAWRENCEVILLE, Ga. – The Association of Independent Institutions (A.I.I.) announced on Monday that Grant Shorty (SO/Albuquerque, NM) of Haskell Indian Nations University (Kan.) has been named the A.I.I.'s Men's Golfer of the Week for the duration of April 10-16.

Haskell Golf team would have finished out their season at the PGA Minority National Championship Tournament in Port St. Lucie, Florida this weekend. The team was informed that they had two players fall below hour's just days before leaving towards Florida.

Lawrence, Kansas – The Haskell men's golf team finished 8th out of 11 teams in the Ottawa Invitational held at Eagle Bend Golf Course in Lawrence, Kansas on Monday and Tuesday. The Indians finished with a round score of 321, 331, with a total team score 652.

Haskell Golf team, Layne Brasswell and Russell Parker are on the search for more teammates!

1 Dominican Peso = 0.1228 Trinidad and Tobago Dollar

Liberty, MO - The Haskell Indian Nations University Men's track and field teams competed at the Darrel Gourley Open on Saturday.

1 Papua New Guinean Kina = 1.9699 Trinidad and Tobago Dollar

1 Brunei Dollar = 4.7815 Trinidad and Tobago Dollar

Formal verification is a complex technology that has traditionally required experts or specialized teams who stood apart from the IC design and verification flow. Taking a different approach, a new release of the Cadence JasperGold formal verification platform (June 8, 2015) provides formal techniques that complement simulation, emulation, and debugging in the form of “Apps” or under-the-hood solutions that any design or verification engineer can use.

JasperGold was the initial (in fact only) product of Jasper Design Automation, acquired by Cadence in 2014. Jasper pioneered the formal Apps concept several years ago. While the company had previously sold JasperGold as a one-size-fits-all solution, Jasper began selling semi-automated JasperGold Apps that solved specific problems using formal analysis technology.

The new release is the next generation of JasperGold and will be available later this month. It includes three major improvements over previous Cadence and Jasper formal analysis offerings:

• A unified Cadence Incisive and JasperGold formal verification platform delivers up to 15X performance gain over previous solutions.
• JasperGold is integrated into the Cadence System Development Suite, where it provides formal-assisted simulation, emulation, and coverage. As a result, System Development Suite users can find bugs three months earlier than existing verification methods.
• JasperGold’s formal analysis engines are integrated with the recently announced Indago debug platform, automating root cause analysis and on-the-fly, what-if exploration.

Best of Both Formal Verification Worlds

Taking advantage of technologies from both Cadence and Jasper, the new JasperGold represents a “best of both worlds” solution, according to Pete Hardee, product management director at Cadence. This solution combines technologies from the Cadence Incisive Enterprise Verifier and Incisive Formal Verifier with JasperGold formal analysis engines.

For example, to ease migration from Incisive formal tools, Cadence has integrated an Incisive common front end into the JasperGold apps platform. Jasper formal engines can run within the Incisive run-time environment. Cadence has also brought some selected Incisive formal engines into JasperGold.

As shown to the right, the JasperGold platform supports both the existing JasperGold front-end parser and the Incisive front-end parser. Hardee observed that this dual parser arrangement simplifies migration from Incisive formal tools to JasperGold, and provides a common compilation environment for people who want to use JasperGold with Incisive simulation. Further, the common run-time environment enables formal-assisted simulation.

The combination of JasperGold engines and Incisive engines supports two use models for formal analysis: formal proofs and bug hunting. In the first case, formal engines try all combinations of inputs without a testbench. The test is driven by formal properties written in languages such as SVA (SystemVerilog assertions) or PSL (Property Specification Language). Completion of a property is exhaustive proof that something can or cannot happen. This provides a “much stronger result” than simulation, Hardee said.

He also noted that formal analysis doesn’t necessarily require that all properties are completed. “You can get a lot of value even if proofs don’t complete,” he said. “Proofs that run deep enough to find bugs are just fine.”

Bug hunting involves random searches, and JasperGold bug hunting engines are very fast. However, these engines don’t necessarily use the most optimal path to get to a bug. So, Cadence engineers brought a constraint solver from Incisive and integrated it into JasperGold. “It looks at the constraints in the environment and gives you a better starting point,” Hardee said. “It takes more up-front time, but once you’ve done that the bug hunting engines can actually take a shorter path and find a bug a lot quicker.”

Another new JasperGold capability from the Incisive Formal Verifier is called “search pointing.” This uses simulation to penetrate deeply into the state space, and then kicks off a random formal search from a given point that you’ve reached in simulation. This technique makes it possible to find bugs that are very deep in the design.

It is probably clear by now that a number of different formal “engines” may be required to solve a given verification problem. Traditionally, a formal tool (or user) will farm a problem out to many engines and see which one works best. To put more intelligence into that process, Cadence launched the Trident “multi-cooperating engine” a couple of years ago. That has now been brought into JasperGold, where it helps “orchestrate” the engines according to what will work best for the design. This is a big part of the reason for the 15X speedup noted earlier in this post.

Integration with System Development Suite

The Cadence System Development Suite is an integrated set of hardware/software development and verification engines, including virtual prototyping, Incisive simulation, emulation, and FPGA-based prototyping. As shown below, JasperGold technology is integrated into the System Development Suite in several places, including formal-assisted debug, formal-assisted verification closure, formal-assisted simulation, formal-assisted emulation, and the Incisive vManager verification planning tool.

Formal-assisted emulation sounds like it should be easy, especially since Cadence has both accelerated verification IP (VIP) and assertion-based VIP. However, there’s a complication. Accelerated VIP represents less verification content than simulation VIP, because you have to remove many checkers to get VIP to compile on a Palladium emulator. That’s because the Palladium requires synthesizable code.

What you can do, however, is use assertion-based VIP in “snoop mode” as shown below. Assertion-based VIP coded in synthesizable SystemVerilog can replace the missing checkers in accelerated VIP. In this diagram, everything in the green box is running in the emulator and is thus completely accelerated.

Another example of formal-assisted emulation has to do with deep traces. As Hardee noted, emulation will produce very long traces, and it can be very difficult to find a point of interest in the trace and determine what caused an error. With formal-assisted emulation, users can find interesting events within the traces and create properties that mark them, so a debugger can find these events and trace back to the root cause.

Formal-assisted verification closure is available with the new JasperGold release. This is possible because you can use the vManager product to determine which tasks were completed by formal engines. It’s important information for verification managers who are not used to formal tools, Hardee noted.

Another aspect of formal-assisted verification closure is the JasperGold Unreachability Analysis (UNR) App, which can save simulation users weeks of time and effort. This App takes in the simulation coverage database and RTL, and automatically generates properties to explore coverage holes and determine if holes are reachable or unreachable. The App then generates an unreachable coverage point database. If the unreachable code does something useful, there’s a bug in the design or the testbench; if not, you don’t have to worry about it. The diagram below shows how it works.

Formal-Assisted Debugging

The third major component of the JasperGold announcement is the integration of formal analysis into the Indago debugging platform. As shown below, this platform has several apps, including the Indago Debug Analyzer. Two formal debug capabilities from the Jasper Visualize environment have been added to the the Indago Debug Analyzer:

• Highlight Relevant Logic: This highlights the “cone of influence,” or the logic that is involved in reaching a given point
• Why: This button highlights the immediate causes for a given event, and allows users to trace backwards in time

More formal capabilities will come with the Indago Advanced Debug Analyzer app, scheduled for release towards the end of 2015. This includes Quiet Trace, a Jasper capability that reduces trace activity to transactions relevant to an event. Also, a what-if analysis allows on-the-fly trace editing and recalculation to explore effects and sensitivities, without having to re-compile and re-execute the simulation.

Finally, Cadence has a Superlint flow that is now fully integrated with the JasperGold Visualize debugger. This two-tiered flow includes a basic lint capability as well as automated formal analysis based on the JasperGold Structural Property Synthesis app. “This could be a very good entry point for designers to start using formal,” Hardee said.

“Formal is taking off,” Hardee concluded. “People are no longer talking about return on investment for formal—they have established that. Now they’re supporting a proliferation of formal in their companies such that a wider set of people experience the benefit from that proven return on investment.”

Further information is available at the JasperGold Formal Verification Platform (Apps) page.

Richard Goering

Related Blog Posts

- JUG Keynote—How Jasper Formal Verification Technology Fits into the Cadence Flow

- Why Cadence Bought Jasper—A New Era in Formal Analysis

- Q&A: An R&D Perspective on Formal Verification—Past, Present and Future

There has been so much hype about the “Internet of Things” (IoT) that it is refreshing to hear about a cutting-edge development project that can bring concrete benefits to millions of people. That project is the ongoing development of the Google Smart Contact Lens, and it was detailed in a keynote speech June 8 at the Design Automation Conference (DAC 2015).

The keynote speech was given by Brian Otis (right), a director at Google and a research associate professor at the University of Washington. The “smart lens” that the project envisions is essentially a disposable contact lens that fits on an eye and continuously monitors blood glucose levels. This is valuable information for anyone who has, or may someday have, diabetes.

Since he was speaking to an engineering audience, Otis focused on the challenges behind building such a device, and described some of the strategies taken by Google and its partner, Novartis. The project required new approaches to miniaturization, low-power design, and connectivity, as well as a comfortable and reliable silicon-to-human interface. Otis discussed the “why” as well and showed how the device could potentially save or improve millions of lives.

Millions of Users

First, a bit of background. Google announced the smart lens project in a blog post in January 2014. Since then it has been featured in news outlets including Forbes, Time, and the Wall Street Journal. In March 2015, Time reported that Google has been granted a patent for a smart contact lens.

The smart lens monitors the level of blood glucose by looking at its concentration in tears. The lens includes a wireless system on chip (SoC) and a miniaturized glucose sensor. A tiny pinhole in the lens allows tear fluid to seep into the sensor, and a wireless antenna handles communications to the wireless devices.

“We figure that if we can solve a huge problem, it is probably worth doing,” Otis said. “Diabetes is one example.” He noted 382 million people worldwide have diabetes today, and that 35% of the U.S. population may be pre-diabetic. Today, diabetics must *** their fingers to test blood glucose levels, a procedure that is invasive, painful, and subject to infrequent monitoring.

According to Otis, the smart contact lens represents a “new category of wearable devices that are comfortable, inexpensive, and empowering.” The lens does sensor data logging and uses a portable instrument to measure glucose levels. It is thin, cheap, and disposable, he said.

Moreover, the lens is not just for people already diagnosed with diabetes—it’s for anyone who is pre-diabetic, or may be at risk due to genetic predisposition. “If we are pro-active rather than re-active,” Otis said, “Instead of waiting until a person has full-fledged diabetes, we could make a huge difference in peoples’ lives and lower the costs of treating them.”

Technical Challenges

No one has built anything quite like the smart lens, so researchers at Google and Novartis are treading new ground. Otis identified three key challenges:

• Miniaturization: Everything must be really small—the SoC, the passive components, the power supply. Components must be flexible and cheap, and support thin-film integration.
• Platform: Google has developed a reusable platform that includes tiny, always-on wireless sensors, ultra low-power components, and standards-based interfaces.
• Data: Researchers are looking for the best ways to get the resulting data into a mobile device and onto the cloud.

Comfort is another concern. “This is not intended to be for the most severe cases,” Otis said. “This is intended to be for all of us as a pro-active way of improving our lifestyles.”

The platform provides a bidirectional encrypted wireless link, integrated power management, on-chip memory, standards-based RFID link, flexible sensor interface, high-resolution potentiostat sensor, and decoupling capacitors. Most of these capabilities are provided by the standard CMOS SoC, which is a couple hundred microns on a side and only “tens of microns” thick.

Otis noted that unpackaged ICs are typically 250 microns thick when they come back from the foundry. Thus, post-processing is needed so the IC will fit into a contact lens.

Furthermore, the design requires precision analog circuitry and additional environmental sensors. “Some of this stuff sounds mundane but it is really hard, especially when you find out you can’t throw large decoupling capacitors and bypass capacitors onto a board, and all that has to be re-integrated into the chip,” Otis said.

Sensor Challenges

Getting information from the human body is challenging. The smart lens sensor does a direct chemical measurement on the surface of the eye. The sensor is designed to work with very low glucose concentrations. This is because the concentration of glucose in tears is an order of magnitude lower than it is in blood.

In brief, the sensor has two parallel plates that are coated with an enzyme that converts glucose into hydrogen peroxide, which flows around the electrodes of the sensor. This is actually a fairly standard way of doing glucose monitoring. However, the smart lens sensor has two electrodes compared to the typical three.

In manufacturing, it is essential to keep costs low. Otis outlined a three-step manufacturing process:

• Start with the bottom layer, and mold a contact lens in the way you typically would.
• Add the electronics package on top of that layer.
• Build a second layer that encapsulates the electronics and provides the curvature needed for comfort and vision correction.

Beyond the technical challenges are the “clinical” challenges of working with human beings. The human body “is messy and very variable,” Otis said. This variability affects sensor performance and calibration, RF/electro-magnetic performance, system reliability, and comfort.

The final step is making use of the data. “We need to get the data from the device into a phone, and then display it so users can visualize the data,” Otis said. This provides “actionable feedback” to the person who needs it. Eventually, the data will need to be stored in the cloud.

As he concluded his talk, Otis noted that the platform his group developed may have many applications beyond glucose monitoring. “There is a lot you can do with a bunch of logic and sensing capability,” he said, “and there are hundreds of biomarkers beyond glucose.” Clearly this will be an interesting technology to watch.

Richard Goering

Related Blog Post

- Gary Smith at DAC 2015: How EDA Can Expand Into New Directions

According to the book Electronic Design Automation For Integrated Circuits Handbook there are mutiple algorithms available. Quote from book: "One of the first complete ATPG algorithms is the D-algorithm [9]. Subsequently, other algorithms were proposed, including PODEM [14], FAN [15], and SOCRATES [10]."

I was wondering which algorithms are used in Cadence Modus.

In last week's post, 1G Mobile: AMPS, TOPS, C-450, Radiocom 2000, and All Those Japanese Ones . I covered 1G mobile, the first analog standards. Then we went digital. 2G The Nordic countries...

[[ Click on the title to access the full blog on the Cadence Community site. ]]

Key Findings:  There are a host of issues that arise in mixed-signal verification.  As discussed in earlier blogs, the industry trends indicate that teams need to prepare themselves for a more mixed world.  The good news is that these top five pitfalls are all avoidable.

It’s always interesting to study the human condition.  Watching the world through the lens of mixed-signal verification brings an interesting microcosm into focus.  The top 5 items that I regularly see vexing teams are:

1. When there’s a bug, whose problem is it?
2. Verification team is the lightning rod
3. Three (conflicting) points of view
4. Wait, there’s more… software
5. There’s a whole new language

Reason 1: When there’s a bug, whose problem is it?

It actually turns out to be a good thing when a bug is found during the design process.  Much, much better than when the silicon arrives back from the foundry of course. Whether by sheer luck, or a structured approach to verification, sometimes a bug gets discovered. The trouble in mixed-signal design occurs when that bug is near the boundary of an analog and a digital domain.

Figure 1.   Whose bug is it?

Typically designers are a diligent sort and make sure that their block works as desired. However, when things go wrong during integration, it is usually also project crunch time. So, it has to be the other guy’s bug, right?

A step in the right direction is to have a third party, a mixed-signal verification expert, apply rigorous methods to the mixed-signal verification task.  But, that leads to number 2 on my list.

Reason 2: Verification team is the lightning rod

Having a dedicated verification team with mixed-signal expertise is a great start, but what can typically happen is that team is hampered by the lack of availability of a fast executing model of the analog behavior (best practice today being a SystemVerilog real number model – SV_RNM). That model is critical because it enables orders of magnitude more tests to be run against the design in the same timeframe. 

Without that model, there will be a testing deficit. So, when the bugs come in, it is easy for everyone to point their finger at the verification team.

Figure 2.  It’s the verification team’s fault

Yes, the model creates a new validation task – it’s validation – but the speed-up enabled by the model more than compensates in terms of functional coverage and schedule.

The postscript on this finger-pointing is the institutionalization of SV-RNM. And, of course, the verification team gets its turn.

Figure 3.  Verification team’s revenge

Reason 3: Three (conflicting) points of view

The third common issue arises when the finger-pointing settles down. There is still a delineation of responsibility that is often not easy to achieve when designs of a truly mixed-signal nature are being undertaken.  

Figure 4.  Points of view and roles

Figure 4 outlines some of the delegated responsibility, but notice that everyone is still potentially on the hook to create a model. It is questions of purpose, expertise, bandwidth, and convention that go into the decision about who will “own” each model. It is not uncommon for the modeling task to be a collaborative effort where the expertise on analog behavior comes from the analog team, while the verification team ensures that the model is constructed in such a manner that it will fit seamlessly into the overall chip verification. Less commonly, the digital design team does the modeling simply to enable the verification of their own work.

Reason 4: Wait, there’s more… software

As if verifying the function of a chip was not hard enough, there is a clear trend towards product offerings that include software along with the chip. In the mixed-signal design realm, many times this software has among its functions things like calibration and compensation that provide a flexible way of delivering guards against parameter drift. When the combination of the chip and the software are the product, they need to be verified together. This puts an enormous premium on fast executing SV-RNM.

Figure 5.   There’s software analog and digital

While the added dimension of software to the verification task creates new heights of complexity, it also serves as a very strong driver to get everyone aligned and motivated to adopt best known practices for mixed-signal verification.  This is an opportunity to show superior ability!

Figure 6.  Change in perspective, with the right methodology

Reason 5: There’s a whole new language

Communication is of vital importance in a multi-faceted, multi-team program.  Time zones, cultures, and personalities aside, mixed-signal verification needs to be a collaborative effort.  Terminology can be a big stumbling block in getting to a common understanding. If we take a look at the key areas where significant improvement can usually be made, we can start to see the breadth of knowledge that is required to “get” the entirety of the picture:

• Structure – Verification planning and management
• Methodology – UVM (Unified Verification Methodology – Accellera Standard)
• Measure – MDV (Metrics-driven verification)
• Multi-engine – Software, emulation, FPGA proto, formal, static, VIP
• Modeling – SystemVerilog (discrete time) down to SPICE (continuous time)
• Languages – SystemVerilog, Verilog, Verilog-AMS, VHDL, SPICE, PSL, CPF, UPF

Each of these areas has its own jumble of terminology and acronyms. It never hurts to create a team glossary to start with. Heck, I often get my LDO, IFV, and UDT all mixed up myself.

Summary

Yes, there are a lot of things that make it hard for the humans involved in the process of mixed-signal design and verification, but there is a lot that can be improved once the pain is felt (no pain, no gain is akin to no bugs, no verification methodology change). If we take a look at the key areas from the previous section, we can put a different lens on them and describe the value that they bring:

• Structure – Uniformly organized, auditable, predictable, transparency
• Methodology – Reusable, productive, portable, industry standard
• Measure – Quantified progress, risk/quality management, precise goals
• Multi-engine – Faster execution, improved schedule, enables new quality level
• Modeling – Enabler, flexible, adaptable for diverse applications/design styles
• Languages – Flexible, complete, robust, standard, scalability to best practices

With all of this value firmly in hand, we can turn our thoughts to happier words:

…  stay tuned for more!

 Steve Carlson

Typically, analog designers verify their AMS IP in schematic driven, interactive environment, while SoC designers use a UVM SystemVerilog testbench ran from a command line. In our last MS blog, we talked about automation for reusing SystemVerilog testbench by analog designers in order to verify AMS IP in exactly same context as in its SoC integration, hence reducing surprises and unnecessary iterations.

But, what about other direction: selecting proper AMS IP views for SoC Verification? Manually export netlist from Virtuoso and then manually assemble together all of the files for use with in command line driven flow? Often, there are multiple views for the same instance (RNM, analog behavioral model, transistor netlist). Which one to pick? Who is supposed to update configuration files? We often work concurrently and update the AMS IP views frequently. Obviously, manually selecting correct and most up-to-date AMS IP views for SoC Verification is tedious and error prone. Thanks to Cadence Innovation, there is a better way!

Cadence has developed a Command-Line IP Selector (CLIPS) product as part of the Virtuoso^® environment, which:

• Bridges the gap between MS SoC command-line setup and the Virtuoso-based analog mixed-signal configuration
• Allows seamless importing of AMS IP from the Virtuoso environment into an existing digital verification setup
• Provides a GUI-based and command-line use model, flexible to fit into an existing design flow methodologyCLIPS reads MS SoC command (irun) files, identifies required AMS IP modules, uses Virtuoso ADE setup files to properly netlist required modules, and pulls the AMS IP out of the Virtuoso environment. All necessary files are properly extracted/prepared and package as required for the MS SoC command line verification run. CLIPS setup can be saved and rerun as a batch process to ensure the latest IP from the hierarchy is being simulated.

For more details, please see CLIPS Rapid Adoption Kit at Cadence Online Support page

The way you need blocks of different sizes and styles to build great Lego masterpieces, a complex WSP-based design requires stitching together routing regions with multiple patterns that follow different WSSPDef periods. Let's see how you can achieve this. (read more)

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દુનિયામાં ખાલી 43 લોકો જ છે જેમની શરીરની નસોમાં વહે છે ગોલ્ડન બ્લડગ્રુપ

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કોરોના વાયરસના પ્રકોપના પગલે એવિએશન સેક્ટરની રેવેન્યૂમાં ખૂબ જ મોટો ફટકો પડ્યો છે. આના પગલે કોસ્ટ એરલાઇન્સ GoAirએ બુધવારે માર્ચમાં પોતાના બધા કર્મચારીઓનો પગાર કાપવાની જાહેરાત કરી છે.

ગત વર્ષે આ દરમિયાન ગોલ્ડનો 10 ગ્રામનો ભાવ લગભગ 31,500 હતો, જે હવે વધીને 46,500 રૂપિયા પ્રતિ 10 ગ્રામના સ્તર પર પહોંચી ગયો છે

જે કર્મચારીઓની ગ્રોસ સેલરી 30,000 રૂપિયા છે તે કર્મચારીઓને ESI કવરેજનો ફાયદો મળશે. ESIC સ્કીમમાં બીમાર પડવા પર સેલરી પ્રોટેક્શન પણ આપવામાં આવશે.

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