Initial draft of the technology framework. Informal document by the Chair

Informal document containing the draft elements of the draft decision on the work programme under the framework for non-market approaches referred to in Article 6, paragraph 8, of the Paris Agreement. Informal document by the Chair.

Informal document containing the draft elements of the rules, modalities and procedures for the mechanism established by Article 6, paragraph 4, of the Paris Agreement. Informal document by the Chair.

Informal document containing the draft elements of guidance on cooperative approaches referred to in Article 6, paragraph 2, of the Paris Agreement. Informal document by the Chair.

Draft elements of the modalities, work programme and functions of the forum on the impact of the implementation of response measures under the Paris Agreement . Informal document by the Chairs.

Governor teams up with popular social network to keep Delawareans informed of the latest on the neighborhood level   WILMINGTON, Del. – Governor John Carney on Friday formally extended the State of Emergency declaration in place to limit the spread of COVID-19, and announced a partnership with the social network Nextdoor to keep Delawareans informed on […]

Biocidal active substance could be used in public health areas

Formal verification is a complex technology that has traditionally required experts or specialized teams who stood apart from the IC design and verification flow. Taking a different approach, a new release of the Cadence JasperGold formal verification platform (June 8, 2015) provides formal techniques that complement simulation, emulation, and debugging in the form of “Apps” or under-the-hood solutions that any design or verification engineer can use.

JasperGold was the initial (in fact only) product of Jasper Design Automation, acquired by Cadence in 2014. Jasper pioneered the formal Apps concept several years ago. While the company had previously sold JasperGold as a one-size-fits-all solution, Jasper began selling semi-automated JasperGold Apps that solved specific problems using formal analysis technology.

The new release is the next generation of JasperGold and will be available later this month. It includes three major improvements over previous Cadence and Jasper formal analysis offerings:

• A unified Cadence Incisive and JasperGold formal verification platform delivers up to 15X performance gain over previous solutions.
• JasperGold is integrated into the Cadence System Development Suite, where it provides formal-assisted simulation, emulation, and coverage. As a result, System Development Suite users can find bugs three months earlier than existing verification methods.
• JasperGold’s formal analysis engines are integrated with the recently announced Indago debug platform, automating root cause analysis and on-the-fly, what-if exploration.

Best of Both Formal Verification Worlds

Taking advantage of technologies from both Cadence and Jasper, the new JasperGold represents a “best of both worlds” solution, according to Pete Hardee, product management director at Cadence. This solution combines technologies from the Cadence Incisive Enterprise Verifier and Incisive Formal Verifier with JasperGold formal analysis engines.

For example, to ease migration from Incisive formal tools, Cadence has integrated an Incisive common front end into the JasperGold apps platform. Jasper formal engines can run within the Incisive run-time environment. Cadence has also brought some selected Incisive formal engines into JasperGold.

As shown to the right, the JasperGold platform supports both the existing JasperGold front-end parser and the Incisive front-end parser. Hardee observed that this dual parser arrangement simplifies migration from Incisive formal tools to JasperGold, and provides a common compilation environment for people who want to use JasperGold with Incisive simulation. Further, the common run-time environment enables formal-assisted simulation.

The combination of JasperGold engines and Incisive engines supports two use models for formal analysis: formal proofs and bug hunting. In the first case, formal engines try all combinations of inputs without a testbench. The test is driven by formal properties written in languages such as SVA (SystemVerilog assertions) or PSL (Property Specification Language). Completion of a property is exhaustive proof that something can or cannot happen. This provides a “much stronger result” than simulation, Hardee said.

He also noted that formal analysis doesn’t necessarily require that all properties are completed. “You can get a lot of value even if proofs don’t complete,” he said. “Proofs that run deep enough to find bugs are just fine.”

Bug hunting involves random searches, and JasperGold bug hunting engines are very fast. However, these engines don’t necessarily use the most optimal path to get to a bug. So, Cadence engineers brought a constraint solver from Incisive and integrated it into JasperGold. “It looks at the constraints in the environment and gives you a better starting point,” Hardee said. “It takes more up-front time, but once you’ve done that the bug hunting engines can actually take a shorter path and find a bug a lot quicker.”

Another new JasperGold capability from the Incisive Formal Verifier is called “search pointing.” This uses simulation to penetrate deeply into the state space, and then kicks off a random formal search from a given point that you’ve reached in simulation. This technique makes it possible to find bugs that are very deep in the design.

It is probably clear by now that a number of different formal “engines” may be required to solve a given verification problem. Traditionally, a formal tool (or user) will farm a problem out to many engines and see which one works best. To put more intelligence into that process, Cadence launched the Trident “multi-cooperating engine” a couple of years ago. That has now been brought into JasperGold, where it helps “orchestrate” the engines according to what will work best for the design. This is a big part of the reason for the 15X speedup noted earlier in this post.

Integration with System Development Suite

The Cadence System Development Suite is an integrated set of hardware/software development and verification engines, including virtual prototyping, Incisive simulation, emulation, and FPGA-based prototyping. As shown below, JasperGold technology is integrated into the System Development Suite in several places, including formal-assisted debug, formal-assisted verification closure, formal-assisted simulation, formal-assisted emulation, and the Incisive vManager verification planning tool.

Formal-assisted emulation sounds like it should be easy, especially since Cadence has both accelerated verification IP (VIP) and assertion-based VIP. However, there’s a complication. Accelerated VIP represents less verification content than simulation VIP, because you have to remove many checkers to get VIP to compile on a Palladium emulator. That’s because the Palladium requires synthesizable code.

What you can do, however, is use assertion-based VIP in “snoop mode” as shown below. Assertion-based VIP coded in synthesizable SystemVerilog can replace the missing checkers in accelerated VIP. In this diagram, everything in the green box is running in the emulator and is thus completely accelerated.

Another example of formal-assisted emulation has to do with deep traces. As Hardee noted, emulation will produce very long traces, and it can be very difficult to find a point of interest in the trace and determine what caused an error. With formal-assisted emulation, users can find interesting events within the traces and create properties that mark them, so a debugger can find these events and trace back to the root cause.

Formal-assisted verification closure is available with the new JasperGold release. This is possible because you can use the vManager product to determine which tasks were completed by formal engines. It’s important information for verification managers who are not used to formal tools, Hardee noted.

Another aspect of formal-assisted verification closure is the JasperGold Unreachability Analysis (UNR) App, which can save simulation users weeks of time and effort. This App takes in the simulation coverage database and RTL, and automatically generates properties to explore coverage holes and determine if holes are reachable or unreachable. The App then generates an unreachable coverage point database. If the unreachable code does something useful, there’s a bug in the design or the testbench; if not, you don’t have to worry about it. The diagram below shows how it works.

Formal-Assisted Debugging

The third major component of the JasperGold announcement is the integration of formal analysis into the Indago debugging platform. As shown below, this platform has several apps, including the Indago Debug Analyzer. Two formal debug capabilities from the Jasper Visualize environment have been added to the the Indago Debug Analyzer:

• Highlight Relevant Logic: This highlights the “cone of influence,” or the logic that is involved in reaching a given point
• Why: This button highlights the immediate causes for a given event, and allows users to trace backwards in time

More formal capabilities will come with the Indago Advanced Debug Analyzer app, scheduled for release towards the end of 2015. This includes Quiet Trace, a Jasper capability that reduces trace activity to transactions relevant to an event. Also, a what-if analysis allows on-the-fly trace editing and recalculation to explore effects and sensitivities, without having to re-compile and re-execute the simulation.

Finally, Cadence has a Superlint flow that is now fully integrated with the JasperGold Visualize debugger. This two-tiered flow includes a basic lint capability as well as automated formal analysis based on the JasperGold Structural Property Synthesis app. “This could be a very good entry point for designers to start using formal,” Hardee said.

“Formal is taking off,” Hardee concluded. “People are no longer talking about return on investment for formal—they have established that. Now they’re supporting a proliferation of formal in their companies such that a wider set of people experience the benefit from that proven return on investment.”

Further information is available at the JasperGold Formal Verification Platform (Apps) page.

Richard Goering

Related Blog Posts

- JUG Keynote—How Jasper Formal Verification Technology Fits into the Cadence Flow

- Why Cadence Bought Jasper—A New Era in Formal Analysis

- Q&A: An R&D Perspective on Formal Verification—Past, Present and Future

Dear all,

I am using Conformal Constraint Designer (Version 17.1) to analyse a SystemVerilog based design.

While performing default HDL checks it finds  some violations (issues) in RTL and complains (warnings, etc) about RTL checks and others.

My questions:

Is there any directive which I can add to RTL (system Verilog) so that particular line of code or signal is ignored or not checked for HDL or RTL checks.

I can set ignore rules in rule manager (gui) but it does not seems effective if code line number changes or new signals are introduced.

What is the best way to customize default_hdl_rules ?

I will be grateful for your guidance.

Thanks for your time.

For a netlist vs. netlist LEC flow we have to solve the following problem:

- in the RTL code we replicate a large array of N x M all-identical hard-macros, let call them MACRO_A

- MACRO_A is pre-assembled in Innovus and contains digital parts and analog parts (bottom-up hierarchical flow)

- at top-level (full-chip) we instantiate this array of all-identical macros

- in the top-level place-and-route flow we perform ecoChangeCell to remaster the top row of this array with MACRO_B

- MACRO_B is just a copy of the original MACRO_A cell containing same pins position, same internal digital functionality and also same digital layout, only slight differences in one analog block inside the macro

- MACRO_A and MACRO_B have the same .lib file generated with the do_extract_model command at the end of the Innovus flow, they only differ in the name of the macro

- when performing post-synthesis netlist vs post-place-and-route we load .lib files of both macros in Conformal LEC

- the LEC flow fails because Conformal LEC sees only MACRO_A instantiated in the post-synthesis netlist and both MACRO_A and MACRO_B in the post-palce-and-route netlist

Since both digital functionality and STD cells layout are the same between MACRO_A and MACRO_B we don't want to keep track of this difference already at RTL stage, we just want to perform this ECO change in place-and-route and force Conformal to assume equivalence between MACRO_A and MACRO_B .

Basically what I'm searching for is something similar to the add_instance_equivalences Conformal command but that works between Golden and Revised designs on cell primitives/black-boxes .

Is this flow supported ?

Thanks in advance

Luca

Analog and Mixed-signal (AMS) designs are increasingly using active power management to minimize power consumption. Typical mixed-signal design uses several power domains and operate in a dozen or more power modes including multiple functional, standby and test modes. To save power, parts of design not active in a mode are shut down or may operate at reduced supply voltage when high performance is not required. These and other low power techniques are applied on both analog and digital parts of the design. Digital designers capture power intent in standard formats like Common Power Format (CPF), IEEE1801 (aka Unified Power Format or UPF) or Liberty and apply it top-down throughout design, verification and implementation flows. Analog parts are often designed bottom-up in schematic without upfront defined power intent. Verifying that low power intent is implemented correctly in mixed-signal design is very challenging. If not discovered early, errors like wrongly connected power nets, missing level shifters or isolations cells can cause costly rework or even silicon re-spin. 

Mixed-signal designers rely on simulation for functional verification. Although still necessary for electrical and performance verification, running simulation on so many power modes is not an effective verification method to discover low power errors. It would be nice to augment simulation with formal low power verification but a specification of power intent for analog/mixed-signal blocs is missing. So how do we obtain it? Can we “extract” it from already built analog circuit? Fortunately, yes we can, and we will describe an automated way to do so!

Virtuoso Power Manager is new tool released in the Virtuoso IC6.1.8 platform which is capable of managing power intent in an Analog/MS design which is captured in Virtuoso Schematic Editor. In setup phase, the user identifies power and ground nets and registers special devices like level shifters and isolation cells. The user has the option to import power intent into IEEE1801 format, applicable for top level or any of the blocks in design. Virtuoso Power Manager uses this information to traverse the schematic and extract complete power intent for the entire design. In the final stage, Virtuoso Power Manager exports the power intent in IEEE1801 format as an input to the formal verification tool (Cadence Conformal-LP) for static verification of power intent.

Cadence and Infineon have been collaborating on the requirements and validation of the Virtuoso Power Manager tool and Low Power verification solution on real designs. A summary of collaboration results were presented at the DVCon conference in Munich, in October of 2018.  Please look for the paper in the conference proceedings for more details. Alternately, can view our Cadence webinar on Verifying Low-Power Intent in Mixed-Signal Design Using Formal Method for more information.

On Sept. 3, U.S. President Barack Obama and China's President, Xi Jinping, formally agreed to participation in the negotiated 2015 United Nations Climate Change Conference (COP 21) Paris Agreement, a global agreement on the reduction of climate change.
 

Millions of Asia’s informal workers – such as vendors, day laborers, and others – are left out of national pension systems. Here’s what we can do to help them in their later years.

ISLAMABAD: As many as 1.6 billion of the world’s 2bn informal economy workers are affected by Covid-19 lockdown and containment measures, a new briefing paper issued by the International Labour Organi­sation (ILO) said.

Most are working in the hardest-hit sectors or in small units more vulnerable to shocks including workers in accommodation and food services, manufacturing, wholesale and retail, and the more than 500 million farmers producing for the urban market, the report says. Women are particularly affected in high-risk sectors, it adds.

The Covid-19 lockdown and containment measures threaten to increase relative poverty levels among the world’s informal economy workers by as much as 56 percentage points in low-income countries.

In high-income countries, relative poverty levels among informal workers is estimated to increase by 52 percentage points, while in upper middle-income countries the increase is estimated to be 21 percentage points.

In addition, with these workers needing to work to feed their families, Covid-19 containment measures in many countries cannot be implemented successfully. This is endangering governments’ efforts to protect the population and fight the pandemic. It may become a source of social tension in countries with large informal economies, the report says.

More than 75 per cent of total informal employment takes place in businesses of fewer than ten workers, including 45pc of independent workers without employees.

With most informal workers having no other means of support, they face an almost unsolvable dilemma: to die from hunger or from the virus, the briefing says. This has been exacerbated by disruptions in food supplies, which has particularly affected those in the informal economy.

For the world’s 67 million domestic workers, 75pc of whom are informal workers, unemployment has become as threatening as the virus itself. Many have not been able to work, whether at the request of their employers or in compliance with lockdowns. Those who do continue to go to work face a high risk of contagion, caring for families in private households. For the 11 million migrant domestic workers the situation is even worse.

The countries with the largest informal economies, where full lockdowns have been adopted, are suffering the most from the consequences of the pandemic. Informal economy workers significantly impacted by lockdown vary from 89pc in Latin America and the Arab states to 83pc in Africa, 73pc in Asia and the Pacific, and 64pc in Europe and Central Asia.

Countries need to follow a multi-track strategy that combines several lines of actions relating to both the health and economic impacts of the pandemic, the ILO said.

Among its recommendations, the report highlights the need for policies that reduce the exposure of informal workers to the virus; ensure that those infected have access to health care; provide income and food support to individuals and their families; and prevent damage to the economic fabric of countries.

Published in Dawn, May 9th, 2020

Embedded connectivity is one of the latest technological trends that has been enthusiastically embraced by the automotive industry. As the modern car becomes increasingly connected, the number of vehicle radio services for aviation, infotainment, ADAS...

Dr. Sethi raises an excellent point about the term functional neurologic disorder (FND) in his comment on the editorial.¹ It seems clear that reticence to use the term functional creates the ambiguity he mentions. Medically unexplained symptoms, categorized in the international classification of diseases as undifferentiated somatoform disorders, are a diagnosis that many providers are loathed to give. Whether that is because of concern about missing a diagnosis is not clear. Having evaluated and treated more than 400 of these individuals in the FND clinic at the University of Colorado, I can attest to the fact that patients arrive confused about their diagnosis. Multiple incorrect diagnoses, as Dr. Sethi points out, pack the medical histories of patients with FND, leading doctors and patients astray. I believe that the commentary by Perez et al.² gives us the best chance for a way forward, by teaching a new generation of residents and fellows how to approach patients in a nonjudgmental and open-minded fashion. It took 30 years to add Functional Neurologic Disorder to the Diagnostic and Statistical Manual, and it is still parenthetical to the term Conversion.³ Stripping the diagnosis of FND of its stigma and empowering care providers to rule in functional disorders is an actionable step which should be taken.

I read with interest the editorial by Strom¹ about functional neurologic disorders (FNDs). As a treating physician, I have struggled with the multiple diagnostic labels attached to these patients by physicians of different medical specialties during the course of their clinical disease presentation. A neurologist may assign a patient who presents with chronic fatigue the diagnostic labels of narcolepsy, idiopathic hypersomnia, or chronic Lyme disease. A rheumatologist may assign the label of collagen vascular disease, and a psychiatrist may diagnose depression. This diagnostic ambiguity is troublesome for patients and clinicians alike. I contend that even the term FND needs to be revisited. A patient should be broadly labeled as having a functional disorder and only after characterization sublabeled and referred to an appropriate specialty physician.

Former Home Office Permanent Secretary Sir Philip Rutnam has formally begun legal action against Home Secretary Priti Patel, claiming "constructive dismissal".

“It will not be a priority to use federal resources to prosecute patients with serious illnesses or their caregivers who are complying with state laws on medical marijuana, but we will not tolerate drug traffickers who hide behind claims of compliance with state law to mask activities that are clearly illegal,” Holder said.

The investigation into the 2001 anthrax attacks, which killed five individuals and sickened 17 others, has formally concluded.

A Joint statement on behalf of the United States and the European Union:

Formal businesses in developing countries often complain about unfair competition from their peers in the informal sector. Their complaints are often well-founded: Growing formal companies must go through the hurdles of paying taxes and fees, waiting in line for permits, and even facing greater scrutiny from government agencies. Informal businesses, on the other hand, use minimal,…

At first this smart lock seemed like gimmicky over-engineering. Then I got thinking about the possibilities.

But hey, what’s wrong with formaldehyde? It’s in our breath, our apples and our trees.