A fiber coupled semiconductor device and a method of manufacturing of such a device are disclosed. The method provides an improved stability of optical coupling during assembly of the device, whereby a higher optical power levels and higher overall efficiency of the fiber coupled device can be achieved. The improvement is achieved by attaching the optical fiber to a vertical mounting surface of a fiber mount. The platform holding the semiconductor chip and the optical fiber can be mounted onto a spacer mounted on a base. The spacer has an area smaller than the area of the platform, for mechanical decoupling of thermally induced deformation of the base from a deformation of the platform of the semiconductor device. Optionally, attaching the fiber mount to a submount of the semiconductor chip further improves thermal stability of the packaged device.

A method to tune an emission wavelength of a laser diode (LD) finely is disclosed. The method first controls a temperature of the etalon filter in T1 or T2, where the transmittance of the etalon filter becomes 40 to 50%, assuming a height between the peak and the bottom of the periodic transmittance to be 100%, at the grid wavelength λ1 or λ2, respectively. Then, the temperature of the LD is adjusted such that the intensity of light emitted from the LD and transmitted through the etalon filter becomes 40 to 50%.

A device including one or more layers with lateral regions configured to facilitate the transmission of radiation through the layer and lateral regions configured to facilitate current flow through the layer is provided. The layer can comprise a short period superlattice, which includes barriers alternating with wells. In this case, the barriers can include both transparent regions, which are configured to reduce an amount of radiation that is absorbed in the layer, and higher conductive regions, which are configured to keep the voltage drop across the layer within a desired range.

A drill bit assembly has a bit head and a pin body. The bit head comprises a cutting end, an opposite connecting end with an engagement section, and a feature facing the connecting end. The pin body comprises a tubular body with an axial bore therethrough, a connecting end with an engagement section and a feature facing the connecting end. The drill bit assembly is manufactured by positioning the pin body connecting end with the bit head connecting end such that the pin body and bit head engagement sections overlap with a gap therebetween, and the pin body and bit head features are aligned; injecting a thermoplastic or other connecting material in liquid form between the bit head and pin body engagement sections and into the gap; and solidifying the thermoplastic or other connecting material such that the bit head and pin body are mechanically coupled together at their connecting ends and their features are securely aligned.

An assembly comprising at least two non-metal components which are fixed to each other using at least one fixing system. The fixing system includes a fixing device with a fixing element which is provided with a head and a rod, and a crimping ring which is in contact with one of the components. A protection device is a part of the fixing system which delimits a cavity for confining gas around a portion of the device comprising the crimping ring. In order to improve the repeatability of the operation for positioning the protection device, a guiding device is provided which includes an assembly element on the portion of the fixing device, and an element for guiding the protection device.

Bushing assemblies include a first tubular end portion, a second tubular end portion, and a middle tubular portion. The middle tubular portion has a longitudinal compressive strength that is less than that of the end portions. In some embodiments, the middle tubular portion is constructed of braided sleeving. Also disclosed are bushing assembly kits, apparatuses that include bushing assemblies, such as aircraft, and associated methods of utilizing bushing assemblies.

A method for applying compression to a joint includes providing an intramedullary fixation assembly having a proximal screw member positioned at a proximal end of the intramedullary fixation assembly and a lag screw member positioned at a distal end of the intramedullary fixation assembly. Medullary canals are drilled in a first and second bone and the medullary canals are reamed. The proximal screw member is inserted into the first bone and a drill is used create a dorsal hole in the first bone. The lag screw member is slideably coupled to the dorsal hole and to the proximal screw member and into the second medullary canal. A torque is applied to the lag screw member to apply compression to the joint.

A showerhead electrode is provided where backside inserts are positioned in backside recesses formed along the backside of the electrode. The backside inserts comprise a tool engaging portion. The tool engaging portion is formed such that the backside insert further comprises one or more lateral shielding portions between the tool engaging portion and the threaded outside diameter to prevent a tool engaged with the tool engaging portion of the backside insert from extending beyond the threaded outside diameter of the insert. Further, the tool engaging portion of the backside insert comprises a plurality of torque-receiving slots arranged about the axis of rotation of the backside insert. The torque-receiving slots are arranged to avoid on-axis rotation of the backside insert via opposing pairs of torque-receiving slots.

A protrusion anchor assembly is provided that utilizes a plurality of extendable pins to secure the anchor body within a bore in any hard material, such as concrete. The anchor body is rotated within the bore while the pins are simultaneously and gradually extended, carving out a groove or grooves within which the pins can sit. After installation, the device is secured within the bore by tightening a jamb nut against the surface of the concrete wall and in some embodiments placing a security plug within the anchor body to ensure that the pins are held in place. The pins prevent the anchor from being withdrawn because they act as protuberances that catch against the edges of the groove and cannot be drawn past that point.

A nut assembly and a holddown assembly using the nut assembly are described, including methods of manufacture and assembly. The nut assembly may include a body portion having first and second openings with an internal wall extending between them. A rotation-inhibiting wall may be included between the first and second openings. A nut portion configured to move axially within the internal wall of the body portion includes structures for co-acting with a rotation-inhibiting wall to limit or prevent rotation of the body portion and the nut portion relative to each other. A nut portion and a body portion extending around the nut portion have limited axial movement relative to each other due to axial engagement between adjacent surfaces on the nut portion and the body portion.

Panel fasteners, panel assemblies, methods of assembly and installation of panel assemblies and panel fasteners, anchor systems, anchor systems with captive fasteners and assemblies are disclosed.

A semiconductor device that includes transistors having the same polarity consumes less power and can prevent a decrease in amplitude of a potential output. The semiconductor device includes a first wiring having a first potential, a second wiring having a second potential, a third wiring having a third potential, a first transistor and a second transistor having the same polarity, and a plurality of third transistors for selecting supply of the first potential to gates of the first transistor and the second transistor or supply of the third potential to the gates of the first transistor and the second transistor and for selecting whether to supply one potential to drain terminals of the first transistor and the second transistor. A source terminal of the first transistor is connected to the second wiring, and a source terminal of the second transistor is connected to the third wiring.

A semiconductor device which shifts a low-level signal is provided. In an example, a first transistor including a first terminal electrically connected to a first wiring and a second terminal electrically connected to a second wiring, a second transistor including a first terminal electrically connected to a third wiring and a second terminal electrically connected to the second wiring, a third transistor including a first terminal electrically connected to a fourth wiring and a second terminal electrically connected to a gate of the second transistor, a fourth transistor including a first terminal electrically connected to a fifth wiring, a second terminal electrically connected to a gate of the third transistor, and a gate electrically connected to a sixth wiring, and a first switch including a first terminal electrically connected to the third wiring and a second terminal electrically connected to a gate of the first transistor are included.

A low profile hold down assembly is mounted to the exterior surface of a sidewall of a trailer. The hold down assembly includes a cover member formed from the same material from which the sidewall of the trailer is formed and therefore is aesthetically desirable.

An anti-disassembling device for an electronic product includes a case, a linear movement device, a circular movement device and an optical encoder. At least one retractable transmission member is connected to the case. The circular movement device is located in the case and has an encoding disk, which has multiple slots defined therethrough and teeth are defined in the periphery thereof. The at least one retractable transmission member is engaged with the teeth to rotate the encoding disk. The optical encoder has a lighting module which emits light beams through the slots of the encoding disk and a photosensitive module receives the light beams and sends a signal to the storage unit of the electronic product. The retractable device rotates when the electronic product is disassembled.

A semiconductor integrated circuit includes: a main-interconnect to which supply voltage or reference voltage is applied; a plurality of sub-interconnects; a plurality of circuit cells configured to be connected to the plurality of sub-interconnects; a power supply switch cell configured to control, in accordance with an input control signal, connection and disconnection between the main-interconnect and the sub-interconnect to which a predetermined one of the circuit cells is connected, of the plurality of sub-interconnects; and an auxiliary interconnect configured to connect the plurality of sub-interconnects to each other.

An isolator circuit capable of two-way electrical disconnection and a semiconductor device including the isolator circuit are provided. A data holding portion is provided in an isolator circuit without the need for additional provision of a data holding portion outside the isolator circuit, and data which is to be input to a logic circuit that is in an off state at this moment is stored in the data holding portion. The data holding portion may be formed using a transistor with small off-state current and a buffer. The buffer can include an inverter circuit and a clocked inverter circuit.

Disclosed herein is a device that includes first and second buffer circuits connected to a data terminal and a first control circuit controlling the first and second buffer circuits. The first control circuit receives n pairs of first and second internal data signals complementary to each other from 2n input signal lines and outputs a pair of third and fourth internal data signals complementary to each other to first and second output signal lines, where n is a natural number more than one. The first and second buffer circuits are controlled based on the third and fourth internal data signals such that one of the first and second buffer circuits turns on and the other of the first and second buffer circuits turns off.

A semiconductor device includes an internal circuit, a power supply control circuit which controls supply of a power supply to the internal circuit upon receipt of a first control signal, and a control signal generation circuit which outputs the first control signal upon receipt of a second control signal. The control signal generation circuit does not deactivate the first control signal when an inactive period of the second control signal is equal to or less than a first period and deactivates the first control signal when the inactive period of the second control signal is more than the first period.

An embodiment of this invention uses a massive parallel interconnect fabric (MPIF) at the flipped interface of a core die substrate (having the core logic blocks) and a context die (used for in circuit programming/context/customization of the core die substrate), to produce ASIC-like density and FPGA-like flexibility/programmability, while reducing the time and cost for development and going from prototyping to production, reducing cost per die, reducing or eliminating NRE, and increasing performance. Other embodiments of this invention enable debugging complex SoC through large contact points provided through the MPIF, provide for multi-platform functionality, and enable incorporating FGPA core in ASIC platform through the MPIF. Various examples are also given for different implementations.

A semiconductor integrated circuit including: a circuit block having an internal voltage line; an annular rail line forming a closed annular line around the circuit block and supplied with one of a power supply voltage and a reference voltage; and a plurality of switch blocks arranged around the circuit block along the annular rail line, the plurality of switch blocks each including a voltage line segment forming a part of the annular rail line and a switch for controlling connection and disconnection between the voltage line segment and the internal voltage line.

An integrated structure of compound semiconductor devices is disclosed. The integrated structure comprises from bottom to top a substrate, a first epitaxial layer, an etching-stop layer, a second epitaxial layer, a sub-collector layer, a collector layer, a base layer, and an emitter layer, in which the first epitaxial layer is a p-type doped layer, the second epitaxial layer is an n-type graded doping layer with a gradually increased or decreased doping concentration, and the sub-collector layer is an n-type doped layer. The integrated structure can be used to form an HBT, a varactor, or an MESFET.

A current output control device is provided that includes: a current cell array section including plural current cell circuits that are each connected in parallel between a first terminal (power source) and a second terminal (ground) that connect between the first terminal and the second terminal in by operation ON so as to increase control current flowing between the first terminal and the second terminal; and a code conversion section (decoder) that generates signals (row codes, column codes) to ON/OFF control current cells so as to change the number of current cells that connect the first terminal and the second terminal according to change in an externally input code and that inputs the generated signals to the current cell array section.

An assembly structure of an electronic control unit and a coil assembly of a solenoid valve for an electronic brake system connected to the electronic control unit having a printed circuit board and applying power to the solenoid valve. The coil assembly is penetrated to allow an upper portion of the solenoid valve to be fitted thereinto, and includes a cylindrical bobbin provided with a coil and a coil case. The electronic control unit is provided with a housing having an insertion groove and joined to the hydraulic control unit, the printed circuit board being disposed spaced apart from the coil assembly, and the housing is provided with an elastic member having one end contacting the printed circuit board and the other end contacting the coil case. The elastic member is configured with a coil spring to produce different elastic forces.

A flush adaptor for use with a valve fitment assembly for dispensing liquids from a container; wherein the flush adaptor comprises an outer ring-collar; a flange with an edge molded to the bottom of the outer ring-collar; an interior ring-collar adjacent to the outer ring-collar; a ridge molded in the interior ring-collar; a seat molded onto the interior ring-collar and a pin molded into the interior ring-collar which keeps the valve in an open position; and a hollow tube molded into the adaptor to allow the flow of liquid through the adaptor and into the fitment assembly; whereby the flush adaptor allows for cleaning of the assembly and any tubes connected thereto.

A fuel system valve assembly may include a housing, a spring, and a body. The housing may have a fuel passage defined in part or more by a fuel passage wall. The fuel passage wall may have a seat and a cylindrical section. The cylindrical section may have a constant diameter and may be located downstream of the seat. In use, the body may reciprocate linearly in the housing between an open position and a closed position. The body may be biased to the closed position by the spring. The body may abut the seat when the body is in the closed position.

Power-efficient actuator apparatus and methods. In one exemplary embodiment, the actuator assembly utilizes a shape memory alloy (SMA) filament driven by an electronic power source to induce movement in the underlying assembly to actuate a load (e.g., water valve). In addition, a circuit board is included which allows the actuator assembly to be readily incorporated or retrofit into a wide range of systems such that the signal characteristics of the supply line can, among other applications, be conditioned in order to protect the SMA filament. Furthermore, the circuit board can also readily be adapted for use with “green” power sources such as photovoltaic systems and the like. Methods for manufacturing and utilizing the aforementioned actuator assembly are also disclosed.

A filler assembly is mounted in an axial hole of a cap of a valve. The filler assembly includes at least one first filler and at least one second filler stacked in a longitudinal direction. A valve rod received in the axial hole extends through the at least one first filler and the at least one second filler. At least one of two mutually abutting faces respectively of the at least one first filler and the at least one second filler is at a non-parallel angle to a radial direction perpendicular to the longitudinal direction. If one of the at least one first filler and the at least one second filler is subjected to a pressing force in the longitudinal direction, at least one of the at least one first filler and the at least one second filler is moved in the radial direction to press against the valve rod.

For a flap assembly, in particular an exhaust gas flap assembly, with the flap mounted on both sides via bearing devices in the housing, the disclosure describes a design in which a bearing body is supported radially against an annular collar of the bearing device and, by way of the annular collar, is held braced in a radially spring-loaded manner in a predefined radial position.

The present invention relates generally to a semiconductor device and, more specifically, to optimizing the creep-age distance of the power semiconductor device and a preparation method thereof. The power semiconductor device includes a chip mounting unit with a die paddle and a plurality of leads arranged side by side located close to one side edge of the die paddle in a non-equidistant manner, a semiconductor chip attached on the die paddle, and a plastic packaging body covering the die paddle, the semiconductor chip, where the plastic packing body includes a plastic extension portion covering at least a part of a lead shoulder of a lead to obtain better electrical safety distance between the terminals of the semiconductor device, thus voltage creep-age distance of the device is increased.

Some implementations provide a structure that includes a first package substrate, a first component, a second package substrate, a second component, and a third component. The first package substrate has a first area. The first component has a first height and is positioned on the first area. The second package substrate is coupled to the first package substrate. The second package substrate has second and third areas. The second area of the second package substrate vertically overlaps with the first area of the first package substrate The third area of the second package substrate is non-overlapping with the first area of the first package substrate. The second component has a second height and is positioned on the second area. The third component is positioned on the third area. The third component has a third height that is greater than each of the first and second heights.

The stack package includes a first semiconductor package and a second semiconductor package. The first semiconductor package includes a first substrate having a first modulus and at least one semiconductor chip mounted on the first substrate. The second semiconductor package stacked on the first semiconductor package and includes a second substrate having a second modulus and at least one semiconductor chip mounted on the second substrate. The second modulus is less than the first modulus. Even in the event that the first semiconductor package is under severe warpage due to a temperature change, the flexible second substrate, which includes e.g., polyimide or poly ethylene terephthalate, of the second semiconductor package may be less sensitive to the temperature change, thereby improving reliability of the stack package.

Systems, manufactures, methods and/or techniques for a merged fiducial for chip packages are described. According to some embodiments, an integrated circuit package may include a package substrate having a first side and a second side, a plurality of conductive traces coupled to the first side and a plurality of balls disposed on the second side. The balls may be adapted to electrically connect the laminate package to a circuit board. The integrated circuit package may include a plurality of ball pads disposed on the second side, the ball pads being adapted to electrically connect the plurality of balls to the plurality of conductive traces. One or more of the ball pads may be uniquely shaped when compared to the rest of the plurality of ball pads, optionally, to serve as a fiducial to designate an A1 pin or ball of the laminate package.

A base at least one principal plane of which is a nitride is prepared for use in epitaxial growth. The base is placed on a susceptor in an epitaxial growth reactor and heated to a predetermined temperature (step A). The heating is started with inactive, nitrogen gas being supplied into the reactor. Then, active, NH3 gas is supplied. Then, a growth step (step B) of a first nitride semiconductor layer is started without an intervening step of thermally cleaning the principal nitride plane of the base. In step B, the first nitride semiconductor layer is epitaxially grown on a principal nitride plane of a base without supply of an Si source material. Then, a relatively thick, second nitride semiconductor layer is epitaxially grown on the first nitride semiconductor layer by supplying an n-type dopant source material (step C).

In manufacturing an LSI, or semiconductor integrated circuit device, the step of assembling device (such as resin sealing step) is normally followed by a voltage-application test in an environment of high temperature (e.g., from 85 to 130° C.) and high humidity (e.g., about 80% RH). It has been found that separation of a titanium nitride anti-reflection film from an upper film and generation of cracks in the titanium nitride film at an upper surface edge part of the aluminum-based bonding pad applied with a positive voltage in the test is caused by an electrochemical reaction due to moisture incoming through the sealing resin and the like to generate oxidation and bulging of the titanium nitride film. These problems are addressed by removing the titanium nitride film over the pad in a ring or slit shape at peripheral area of the aluminum-based bonding pad.

A larger substrate can be used, and a transistor having a desirably high field-effect mobility can be manufactured through formation of an oxide semiconductor layer having a high degree of crystallinity, whereby a large-sized display device, a high-performance semiconductor device, or the like can be put into practical use. A first multi-component oxide semiconductor layer is formed over a substrate and a single-component oxide semiconductor layer is formed thereover; then, crystal growth is carried out from a surface to an inside by performing heat treatment at 500° C. to 1000° C. inclusive, preferably 550° C. to 750° C. inclusive so that a first multi-component oxide semiconductor layer including single crystal regions and a single-component oxide semiconductor layer including single crystal regions are formed; and a second multi-component oxide semiconductor layer including single crystal regions is stacked over the single-component oxide semiconductor layer including single crystal regions.

A first impurity region is formed by ion implantation through a first opening formed in a mask layer. By depositing a spacer layer on an etching stop layer on which the mask layer has been provided, a mask portion having the mask layer and the spacer layer is formed. By anisotropically etching the spacer layer, a second opening surrounded by a second sidewall is formed in the mask portion. A second impurity region is formed by ion implantation through the second opening. An angle of the second sidewall with respect to a surface is 90°±10° across a height as great as a second depth. Thus, accuracy in extension of an impurity region can be enhanced.

A semiconductor device has a semiconductor wafer with a plurality of contact pads. A first insulating layer is formed over the semiconductor wafer and contact pads. A portion of the first insulating layer is removed, exposing a first portion of the contact pads, while leaving a second portion of the contact pads covered. An under bump metallization layer and a plurality of bumps is formed over the contact pads and the first insulating layer. A second insulating layer is formed over the first insulating layer, a sidewall of the under bump metallization layer, sidewall of the bumps, and upper surface of the bumps. A portion of the second insulating layer covering the upper surface of the bumps is removed, but the second insulating layer is maintained over the sidewall of the bumps and the sidewall of the under bump metallization layer.

A method of making a microelectronic package includes forming a dielectric encapsulation layer on an in-process unit having a substrate having a first surface and a second surface remote therefrom. A microelectronic element is mounted to the first surface of the substrate, and a plurality of conductive elements exposed at the first surface, at least some of which are electrically connected to the microelectronic element. Wire bonds have bases joined to the conductive elements and end surfaces remote from the bases and define an edge surface extending away between the base and the end surface. The encapsulation layer is formed to at least partially cover the first surface and portions of the wire bonds with unencapsulated portions of the wire bonds being defined by at least one of the end surface or a portion of the edge surface that is uncovered thereby.

It is an object to provide a semiconductor device including a thin film transistor with favorable electric properties and high reliability, and a method for manufacturing the semiconductor device with high productivity. In an inverted staggered (bottom gate) thin film transistor, an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer, and a buffer layer formed using a metal oxide layer is provided between the semiconductor layer and a source and drain electrode layers. The metal oxide layer is intentionally provided as the buffer layer between the semiconductor layer and the source and drain electrode layers, whereby ohmic contact is obtained.

A process for preparing a semiconductor structure for mounting to a carrier is disclosed. The process involves causing a support material to substantially fill a void defined by surfaces formed in the semiconductor structure and causing the support material to solidify sufficiently to support the semiconductor structure when mounted to the carrier.

A III-N device is described with a III-N material layer, an insulator layer on a surface of the III-N material layer, an etch stop layer on an opposite side of the insulator layer from the III-N material layer, and an electrode defining layer on an opposite side of the etch stop layer from the insulator layer. A recess is formed in the electrode defining layer. An electrode is formed in the recess. The insulator can have a precisely controlled thickness, particularly between the electrode and III-N material layer.

The object of the invention is to provide a method for fabricating a semiconductor device having a peeled layer bonded to a base material with curvature. Particularly, the object is to provide a method for fabricating a display with curvature, more specifically, a light emitting device having an OLED bonded to a base material with curvature. An external force is applied to a support originally having curvature and elasticity, and the support is bonded to a peeled layer formed over a substrate. Then, when the substrate is peeled, the support returns into the original shape by the restoring force, and the peeled layer as well is curved along the shape of the support. Finally, a transfer object originally having curvature is bonded to the peeled layer, and then a device with a desired curvature is completed.

Disclosed is a semiconductor device including an oxide semiconductor film. A first oxide semiconductor film with a thickness of greater than or equal to 2 nm and less than or equal to 15 nm is formed over a gate insulating layer. First heat treatment is performed so that crystal growth from a surface of the first oxide semiconductor film to the inside thereof is caused, whereby a first crystal layer is formed. A second oxide semiconductor film with a thickness greater than that of the first oxide semiconductor film is formed over the first crystal layer. Second heat treatment is performed so that crystal growth from the first crystal layer to a surface of the second oxide semiconductor film is caused, whereby a second crystal layer is formed. Further, oxygen doping treatment is performed on the second crystal layer.

To provide a method by which a semiconductor device including a thin film transistor with excellent electric characteristics and high reliability is manufactured with a small number of steps. After a channel protective layer is formed over an oxide semiconductor film containing In, Ga, and Zn, a film having n-type conductivity and a conductive film are formed, and a resist mask is formed over the conductive film. The conductive film, the film having n-type conductivity, and the oxide semiconductor film containing In, Ga, and Zn are etched using the channel protective layer and gate insulating films as etching stoppers with the resist mask, so that source and drain electrode layers, a buffer layer, and a semiconductor layer are formed.

An object is to provide a thin film transistor and a method for manufacturing the thin film transistor including an oxide semiconductor with a controlled threshold voltage, high operation speed, a relatively easy manufacturing process, and sufficient reliability. An impurity having influence on carrier concentration in the oxide semiconductor layer, such as a hydrogen atom or a compound containing a hydrogen atom such as H2O, may be eliminated. An oxide insulating layer containing a large number of defects such as dangling bonds may be formed in contact with the oxide semiconductor layer, such that the impurity diffuses into the oxide insulating layer and the impurity concentration in the oxide semiconductor layer is reduced. The oxide semiconductor layer or the oxide insulating layer in contact with the oxide semiconductor layer may be formed in a deposition chamber which is evacuated with use of a cryopump whereby the impurity concentration is reduced.

A method for producing a Ga-containing group III nitride semiconductor having reduced threading dislocation is disclosed. A buffer layer in a polycrystal, amorphous or polycrystal/amorphous mixed state, comprising AlGaN is formed on a substrate. The substrate having the buffer layer formed thereon is heat-treated at a temperature higher than a temperature at which a single crystal of a Ga-containing group III nitride semiconductor grows on the buffer layer and at a temperature that the Ga-containing group III nitride semiconductor does not grow, to reduce crystal nucleus density of the buffer layer as compared with the density before the heat treatment. After the heat treatment, the temperature of the substrate is decreased to a temperature that the Ga-containing group III nitride semiconductor grows, the temperature is maintained, and the Ga-containing group III nitride semiconductor is grown on the buffer layer.

A microelectronic assembly and method of making, which includes a first microelectronic element (including a substrate with first and second opposing surfaces, a semiconductor device, and conductive pads at the first surface which are electrically coupled to the semiconductor device) and a second microelectronic element (including a handler with first and second opposing surfaces, a second semiconductor device, and conductive pads at the handler first surface which are electrically coupled to the second semiconductor device). The first and second microelectronic elements are integrated such that the second surfaces face each other. The first microelectronic element includes conductive elements each extending from one of its conductive pads, through the substrate to the second surface. The second microelectronic element includes conductive elements each extending between the handler first and second surfaces. The conductive elements of the first microelectronics element are electrically coupled to the conductive elements of the second microelectronics element.

A semiconductor device has a protective layer formed over an active surface of a semiconductor wafer. The semiconductor die with pre-applied protective layer are moved from the semiconductor wafer and mounted on a carrier. The semiconductor die and contact pads on the carrier are encapsulated. The carrier is removed. A first insulating layer is formed over the pre-applied protective layer and contact pads. Vias are formed in the first insulating layer and pre-applied protective layer to expose interconnect sites on the semiconductor die. An interconnect structure is formed over the first insulating layer in electrical contact with the interconnect sites on the semiconductor die and contact pads. The interconnect structure has a redistribution layer formed on the first insulating layer, a second insulating layer formed on the redistribution layer, and an under bump metallization layer formed over the second dielectric in electrical contact with the redistribution layer.

A semiconductor device having favorable electric characteristics and a manufacturing method thereof are provided. A transistor includes an oxide semiconductor layer formed over an insulating layer, a source electrode layer and a drain electrode layer which overlap with part of the oxide semiconductor layer, a gate insulating layer in contact with part of the oxide semiconductor layer, and a gate electrode layer over the gate insulating layer. In the transistor, a buffer layer having n-type conductivity is formed between the source electrode layer and the oxide semiconductor layer and between the drain electrode layer and the oxide semiconductor layer. Thus, parasitic resistance is reduced, resulting in improvement of on-state characteristics of the transistor.