1 Japanese Yen = 94.7636 Uzbekistan Som

1 Japanese Yen = 0.0417 Romanian Leu

1 Japanese Yen = 0.0036 Omani Rial

1 Japanese Yen = 0.1737 Namibian Dollar

1 Japanese Yen = 0.0406 Malaysian Ringgit

1 Japanese Yen = 0.2219 Mexican Peso

1 Japanese Yen = 0.1453 Maldivian Rufiyaa

1 Japanese Yen = 0.3723 Mauritian Rupee

1 Japanese Yen = 0.5327 Macedonian Denar

1 Japanese Yen = 0.1672 Moldovan Leu

1 Japanese Yen = 0.0921 Moroccan Dirham

1 Japanese Yen = 0.0078 Cayman Islands Dollar

1 Japanese Yen = 0.2346 Honduran Lempira

1 Japanese Yen = 0.516 Dominican Peso

1 Japanese Yen = 36.5265 Colombian Peso

1 Japanese Yen = 0.0663 Chinese Yuan Renminbi

1 Japanese Yen = 0.0344 United Arab Emirates Dirham

Which is the only palindromic song by a palindromic group to have entered the US charts?

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Who used to be known as Dileep Kumar, and is now married to Saira Banu?

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“I am a small eye poet.” Who once wrote these words in a letter to his mother?

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In the book “The World of _____” by Bennett Alan Weinberg and Bonnie K Bealer, there is a photograph of a label from a jar of pharmaceutical-grade crystals. It reads:

“WARNING: MAY BE HARMFUL IF INHALED OR SWALLOWED. HAS CAUSED MUTAGENIC AND REPRODUCTIVE EFFECTS IN LABORATORY ANIMALS. INHALATION CAUSES RAPID HEART RATE, EXCITEMENT, DIZZINESS, PAIN, COLLAPSE, HYPOTENSION, FEVER, SHORTNESS OF BREATH. MAY CAUSE HEADACHE, INSOMNIA, VOMITING, STOMACH PAIN, COLLAPSE AND CONVULSIONS.”

Fill in the blank.

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In Texas Hold’em Poker, which hand is known as ‘six tits’?

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This character’s creator described him as “insufferable”, and called him a “detestable, bombastic, tiresome, ego-centric little creep”. On August 6 1975, the New York Times carried his obituary, the only time it has thus honoured a fictional character. Who?

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Orhan Pamuk on his “Turkish Library” and “buying books, as if to take revenge on the life I was fleeing.”

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That’s what Pakistan can become, warns Patrick French. (Via Nikhil Mehra.)

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.. his collection of “vintage knick-knacks, fab furnishings, collectible art, one-of-a-kind porn, and plastic food” and LOTS of books!

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NYT Article: How I Learned to Love Goat Meat

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Check out Norman Mailer’s ten favourite American novels.

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This Salman Khan deserves to be called a hero. Terrific educational videos. (Via Prashant.)

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The buzz about showing and paying for value in EDA has been building over the past few years. People have complained about the high cost of tools and EDA vendors have complained about not getting enough value from the technology that can then be re-invested in the next generation tools. The same complaints can be heard from the foundries regarding their wafer pricing

Companies have tried royalty-based models before in the past (e.g., $/wafer or even profit sharing). But it hasn't been sticky. Is the industry ready for a new model?  I think sharing in the upside and potential downside of a particular design from inception to volume is fair. But it also would mean that EDA companies and foundries would have to participate even earlier (and later) in the product lifecycle - from design spec/marketing through product introduction.

That's a pretty big change that goes beyond just the business model. But maybe at 32nm and below, where designs cost upwards of $75M to bring to market, this type of collaboration and risk/reward model is required and desired

"The number of watchmen required to watch the watchmen watching the watchmen tends to double every 18 months".  This gem is Alan Moore's law, posted years ago by some wag in response to an Intel article on geek.com.  This has, of course, surfaced because of the recent release of the Watchmen movie.  OK so I admit that I haven't read the book or even seen the movie - and based on my recent experiences of superhero movies (with the exception of the Hellboy movies, starring the very wonderful Ron Perlman) I may not bother. 

But when it comes to the "real" Moore's law - Gordon Moore, that is - I think we have all read the book, seen the movie and got the tattoo.  So I hereby pledge that I will never again begin another datasheet, article or white paper with words such as, "With design features getting smaller and smaller...".  With all respect to Dr. Moore, there are plenty of other interesting and less-explored angles on the manifold complexities of electronic design. 

Although we can't take Moore's law for granted, I think we can take it as read. 

Chris Clee

Earning calls sure are interesting! Below is an excerpt from the TSMC Q209 call (transcript from seekingalpha). The discussion revolves around the 40nm yield issues and TSMC's ramp to improving the yield. Dr. Liu really hits on a key element of DFM...(read more)

It was a sunny, Sunday afternoon in Anaheim (across from Disneyland). That combination of weather and entertainment didn't sway a group of 35 engineers from participating in the DFMC (Design for Manufacturability Coalition) Workshop at DAC 2010. On...(read more)

What is the meaning of this error?

I used already two ports (PORT1 and PORT2 for input and output, respectively.

-------------------------------------------------------------------------------------------------------------------------

Also when I apply the PSP analysis for S-parameter the value of maximum S21 value (4.75 dB) is much lower than the maximum power gain (17.6 dB).

while the same circuit is designed using  ADS program the two values are approximately the same around (17.1 dB).

Hi,

I'm doing the "The Targeted Fault Campaign" with ncsim and got stuck at the following message: "ncsim: *E,FLTIGF: [FLT] Failed to inject fault at circuit_tb.U0.n2174." I already tried with other NETs, with SET, SA0, SA1, always the same error occurs.

$nchelp ncsim FLTIGF
$ncsim/FLTIGF =
    Injection time is not within the expected finish
    time for the specified fault node. Failed to inject fault.

As can be seen below, the injection time is at 2ns and the -fault_good_run -fault_tw 1ns:100ns, so in theory 2ns is inside the window 1ns:100ns.

My scripts so far, considering I already compiled the Verilog testbench and also the gates from the technology library (gate-level simulation):

#this runs ok

ncelab -work worklib -cdslib circuit/trunk/backend/synthesis/work/cds.lib -logfile ncelab.log -errormax 15 -access +wc -status -timescale 1ps/1ps worklib.circuit_tb -fault_file circuit/trunk/backend/synthesis/scripts/fi.list

#this runs ok
ncsim -fault_good_run -fault_tw 1ns:100ns -fault_work fault_db -fault_overwrite worklib.circuit_tb:module -input ../scripts/fs_strobe.tcl -exit

#this runs NOT OK
ncsim -fault_sim_run -fault_work fault_db worklib.circuit_tb:module -input ../scripts/injection.tcl -exit

After the above command, I get: "ncsim: *E,FLTIGF: [FLT] Failed to inject fault at circuit_tb.U0.n2174."

Here are the files called from the commands above.

fi.list:

fault_target circuit_tb.U0.n2174 -type SET+SA1+SA0

fs_strobe.tcl:

fs_strobe circuit_tb.WRITE_OUT circuit_tb.PC_OUT[0]

injection.tcl:

fault -stop_severity 3 -inject -time 2ns -type sa1 circuit_tb.U0.n2174

I already checked the NETs with simvision, so their paths are correct.

I'm using as reference the following document: "Functional Safety Simulation - Product Version 15.2 - April 2016"

Any ideas are welcome.

Thank you in advance.

Hi,

I'm doing the "The Targeted Fault Campaign" with ncsim and got stuck at the following message: "ncsim: *E,FLTIGF: [FLT] Failed to inject fault at circuit_tb.U0.n2174." I already tried with other NETs, with SET, SA0, SA1, always the same error occurs.

$nchelp ncsim FLTIGF
$ncsim/FLTIGF =
    Injection time is not within the expected finish
    time for the specified fault node. Failed to inject fault.

As can be seen below, the injection time is at 2ns and the -fault_good_run -fault_tw 1ns:100ns, so in theory 2ns is inside the window 1ns:100ns.

My scripts so far, considering I already compiled the Verilog testbench and also the gates from the technology library (gate-level simulation):

#this runs ok

ncelab -work worklib -cdslib circuit/trunk/backend/synthesis/work/cds.lib -logfile ncelab.log -errormax 15 -access +wc -status -timescale 1ps/1ps worklib.circuit_tb -fault_file circuit/trunk/backend/synthesis/scripts/fi.list

#this runs ok
ncsim -fault_good_run -fault_tw 1ns:100ns -fault_work fault_db -fault_overwrite worklib.circuit_tb:module -input ../scripts/fs_strobe.tcl -exit

#this runs NOT OK
ncsim -fault_sim_run -fault_work fault_db worklib.circuit_tb:module -input ../scripts/injection.tcl -exit

After the above command, I get: "ncsim: *E,FLTIGF: [FLT] Failed to inject fault at circuit_tb.U0.n2174."

Here are the files called from the commands above.

fi.list:

fault_target circuit_tb.U0.n2174 -type SET+SA1+SA0

fs_strobe.tcl:

fs_strobe circuit_tb.WRITE_OUT circuit_tb.PC_OUT[0]

injection.tcl:

fault -stop_severity 3 -inject -time 2ns -type sa1 circuit_tb.U0.n2174

I already checked the NETs with simvision, so their paths are correct.

I'm using as reference the following document: "Functional Safety Simulation - Product Version 15.2 - April 2016"

Any ideas are welcome.

Thank you in advance.

Hi,

I am designing a resistive feedback TIA which needs a capacitor in its feedback loop for stability.

I would like to know the effect of a feedback capacitor on the phase margin to determine the optimal capacitance value.

My plan is to add it to the results after the stb analysis by using the direct plot>main form > phase margin (add to outputs).However it not getting added to my results list.

What could be a problem? Is there a way to add phase margin to the results using the calculator? 

I also find that the gain from the stability analysis(the closed loop gain) is different from that of the gain obtained for the closed loop simulation in AC analysis. Why is the difference, how is it computed in stability analysis?

Thanks,

-Rakesh.

Once while eating dinner in Montreal, our friendly, intoxicated waitress plopped herself in my lap and proceeded to tell us about how obsessed she was with the CD that was playing - singing out the lyrics at an ungodly volume and flinging her arms about. Wow, I thought to myself, people who listen to Morcheeba sure seem to have a lot of fun, and promised to check them out.

Several CDs later, they are firmly one of my favorites. And their trip hop meditation, 2003’s Charango remains one of my most played CDs.

Morcheeba (Mor = more, Cheeba = pot) are brothers Ross and Paul Godfrey with singer Skye Edwards (who has since been replaced). Part trance, part ambience, Charango is full of smooth, snogworthy jams. And just as you surrender to its seductive groove, Slick Rick shows up with a rap called “Women Lose Weight”.

Lamenting his wife putting on weight after having kids and stalled by his mistress who wants a clean break before she shacks up with him, he decides the easiest way out of it all is to kill the spouse. Considering different ways to do the deed, he finally rams his car into her Chevy over a long lunch break one fine day. It is an unexpected, stunning, tongue-in-cheek social commentary that makes it a CD you won’t forget easily.

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This new film is the latest remake of Devdas, but what is equally interesting is the fact that it is in conversation with films made in the West. Unlike Bhansali’s more spectacular version of the older story, Anurag Kashyap’s Dev.D is a genuine rewriting of Sarat Chandra’s novel. Kashyap doesn’t flinch from depicting the individual’s downward spiral, but he also gives women their own strength. He has set out to right a wrong—or, at least, tell a more realistic, even redemptive, story. If these characters have lost some of the affective depth of the original creations, they have also gained the hard edges of modern lives.

We don’t always feel the pain of Kashyap’s characters, but we are able to more readily recognize them. Take Chandramukhi, or Chanda, who is a school-girl humiliated by the MMS sex-scandal. Her father, protective and patriarchal, says that he has seen the tape and thinks she knew what she was doing. “How could you watch it?” the girl asks angrily. And then, “Did you get off on it?” When was the last time a father was asked such a question on the Hindi screen? With its frankness toward sex and masturbation, Dev.D takes a huge step toward honesty. In fact, more than the obvious tributes to Danny Boyle’s Trainspotting, or the over-extended psychedelic adventure on screen, in fact, as much as the moody style of film-making, the candour of such questions make Dev.D a film that is truly a part of world cinema.

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I loved Nina Paley’s brilliant animated film Sita Sings the Blues. If you’re reading this, stop right now—and watch the film here.

Paley has set the story of the Ramayana to the 1920s jazz vocals of Annette Hanshaw. The epic tale is interwoven with Paley’s account of her husband’s move to India from where he dumps her by e-mail. The Ramayana is presented with the tagline: “The Greatest Break-Up Story Ever Told.”

All of this should make us curious. But there are other reasons for admiring this film:

The film returns us to the message that is made clear by every village-performance of the Ramlila: the epics are for everyone. Also, there is no authoritative narration of an epic. This film is aided by three shadow puppets who, drawing upon memory and unabashedly incomplete knowledge, boldly go where only pundits and philosophers have gone before. The result is a rendition of the epic that is gloriously a part of the everyday.

This idea is taken even further. Paley says that the work came from a shared culture, and it is to a shared culture that it must return: she has put the film on Creative Commons—viewers are invited to distribute, copy, remix the film.

Of course, such art drives the purists and fundamentalists crazy. On the Channel 13 website, “Durgadevi” and “Shridhar” rant about the evil done to Hinduism. It is as if Paley had lit her tail (tale!) and set our houses on fire!

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Best Practices for Optimization What should be my considerations while preparing data? Libraries, HDL, Constraints... A good result from a synthesis tool depends greatly on the input data. An old saying "garbage in garbage out" is also true for...(read more)

Cadence is hosting a Front End Design Summit on Thursday, December 6, 2012 9:30am – 5:00pm at Cadence San Jose headquarters, 2655 Seely Avenue, Building 10. Logic designers will hear from customers including Cisco, Chelsio, PMC, Spansion, and Via Technologies...(read more)

Cadence Encounter® Test uses breakthrough timing-aware and power-aware technologies to enable customers to manufacture higher quality, power-efficient silicon faster and at lower cost. Encounter Diagnostics identifies critical yield-limiting issues and...(read more)

With shrinking design nodes, a significant portion of the delays are contributed by the wires rather than the cells. Traditional synthesis tools use fan-out-based wire-load models to provide wire delay information, which has led to significant differences...(read more)

How to use Encounter® RTL Compiler support Interface Logic Models during synthesis.(read more)

Cadence's Digital Front-End Design Team first introduced the concept of a Rapid Adoption Kit (RAK) , self-guided and learn-by-doing training material, over two and a half years ago, helping its users across the globe deploy new products and flows. These...(read more)

The design and physical implementation engineers involved in early to late stage synthesis require a flow that helps them investigate timing using a structured and physically aware approach. Cadence Encounter® RTL Compiler (RC) Timing Analyzer was developed...(read more)

Cadence offers a new Rapid Adoption Kit for logic built in self test tasks.(read more)

Hello Encounter Test Users, In this blog, I would like to introduce a few knowledge artifacts that will provide an easy way for you to learn about and stay productive with this product, technology, and methodology. In addition, this will also help to...(read more)

એક શ્રમિકમાં કોરોનાના લક્ષણ જોવા મળતાં તકેદારીના ભાગ રૂપે ટ્રકમાં લાદેલી તમામ કેરી નષ્ટ કરી દેવામાં આવી