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Following is Editor Len Tashman's preview of the new issue of Foresight: The International Journal of Applied Forecasting.  Preview of Foresight #62 (2021:Q3) This 62nd issue of Foresight has been heavily “infected” by the COVID pandemic. Stephan Kolassa’s book review of Resurrecting Retail by Doug Stephens raises the question of whether the [...]

The post Preview of Foresight #62 (2021-Q3) appeared first on The Business Forecasting Deal.

Following is editor Len Tashman's preview of the 2021-Q4 issue of Foresight: The International Journal of Applied Forecasting. Preview of Foresight #63 (2021-Q4) FORESIGHT HALL OF FAME Adopting the idea from other journals that recognize outstanding contributions to the field through best paper awards, we are pleased to announce that [...]

The post Preview of Foresight #63 (2021-Q4) appeared first on The Business Forecasting Deal.

A previous article shows a simulation of two different models of a foraging animal. The first model is a random walk, which assumes that the animal chooses a random direction, then takes a step that is distributed according to a Gaussian random variable. In the second model, the animal again [...]

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Jimmy Carter celebrated his 100th birthday on Tuesday - the first ever US president to reach the century mark and another extraordinary milestone for the one-time peanut farmer who found his way to the White House.

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[Parliament of South Africa] Parliament, Tuesday, 12 November 2024 - The National Assembly (NA) will hold a plenary session scheduled to start at 10:00. Among the items on the agenda from 10:00 to 13:00 is the statement by the Minister of Water and Sanitation on water security in the country and a debate on 16 Days of Activism for no violence against women and children. The debate will be held under the theme, "Marking 30 years of democratic rights for women and fostering national unity to end gender-based violence".

PCI-SIG DevCon 2024 – 32^nd Anniversary

For more than a decade, Cadence has been well-known in the industry for its strong commitment and support for PCIe technology. We recognize the importance of ensuring a robust PCIe ecosystem and appreciate the leadership PCI-SIG provides. To honor the 32^nd anniversary of the PCI-SIG Developer’s Conference, Cadence is announcing a complete PCIe 7.0 IP solution for HPC/AI markets.

Why Are Standards Like PCIe So Important?

From the simplest building blocks like GPIOs to the most advanced high-speed interfaces, IP subsystems are the lifeblood of the chipmaking ecosystem. A key enabler for IP has been the collaboration between industry and academia in the creation of standards and protocols for interfaces. PCI-SIG drives some of the key definitions and compliance specifications and ensures the interoperability of interface IP.

HPC/AI markets continue to demand high throughput, low latency, and power efficiency. This is fueling technology advancements, ensuring the sustainability of PCIe technology for generations to come. As a close PCI-SIG member, we gain valuable early insights into the evolving specs and the latest compliance standards. PCIe 7.0 specifications and beyond will enable the market to scale, and we look forward to helping our customers build best-in-class cutting-edge SoCs using Cadence IP solutions.

Figure 1. Evolution of PCIe Data Rates (source PCI-SIG)

What’s New This Year at DevCon?

At DevCon ’24, the PCIe 7.0 standard will take center stage, and Cadence is showing off a full suite of IP subsystem solutions for PCIe 7.0 this year.

What Sets Cadence Apart?

At Cadence, we believe in building a full subsystem for our testchips with eight lanes of PHY along with a full 8-lane controller. Adding a controller to our testchip significantly increases the efficiency and granularity in characterization and stress testing and enables us to demonstrate interoperability with real-world systems. We are also able to test the entire protocol stack as an 8-lane solution that encompasses many of the applications our customers use in practice. This approach significantly reduces the risks in our customers’ SoC designs.

Figure 2: Piper - Cadence PHY IP for PCIe 7.0

Figure 3: Industry’s first IP subsystem for PCIe 7.0

Which Market Is This For?

At a time when accelerated computing has gone mainstream, PCIe links are going to take on a role of higher importance in systems. Direct GPU-to-GPU communication is crucial for scaling out complex computational tasks across multiple graphics processing units (GPUs) or accelerators within servers or computing pods. There is a growing recognition within the industry of a need for scalable, open architecture in high-performance computing. As AI and data-intensive applications evolve, the demand for such technologies will likely increase, positioning PCIe 7.0 as a critical component in the next generation of interface IP.

Here's a recent article describing a potential use case for PCIe 7.0.

Figure 4: Example use case for PCIe 7.0

Why Are Optical Links Important?

It takes multiple buildings of data centers to train AI/ML models today. These buildings are increasingly being distributed across geographies, requiring optical fiber networks that are great at handling the increased bandwidth over long distances. However, these optical modules soon hit a power wall where all the budgeted power is used to drive the signal from point A to point B, and there is not enough power left to run the actual CPUs and GPUs. Such scenarios create a need for non-retimed, linear topologies. Linear Pluggable Optics (LPO) links can significantly reduce module power consumption and latency when compared to traditional Digital Signal Processing (DSP) based retimed optical solutions, which is critical for accelerating AI performance. Swapping from DSP-based solutions to LPO results in significant cost savings that help drive down expenditure due to lower power and cooling requirements, but this requires a robust high-performance ASIC to drive the optics rather than retimers/DSP.

To showcase the robustness of Cadence IP, we have demonstrated that our subsystem testchip board for PCIe 7.0 can successfully transmit and receive 128GT/s signals through a non-retimed opto-electrical link configured in an external loopback mode with multiple orders of margin to spare.

Figure 5: Example of ASIC driving linear optics

Compliance Is Key

For PCIe 6.0, the official compliance program has not started yet; this is typical for the SIG where the official compliance follows a few years after the spec is ratified to give enough time for the ecosystem to have initial products ready, and for test and equipment vendors to get their hardware/software up and running. At this time, PCIe Gen6 implementations can only be officially certified up to PCIe 5.0 level (the highest official compliance test suite that the SIG supports). We have taken our PCIe 6.0 IP subsystem solution to the SIG for multiple process nodes, and they are all listed as compliant. You can run this query on the pcisig.com website under the Developers->Integrators list by making the following selections:

Due to space limitations, not all combinations could be tested at the May workshop (e.g., N3 root port) – this will be tested in the next workshop.

Also, the SIG just held an “FYI” compliance event this week to bring together the ecosystem for confidential testing (no results were reported, and data cannot be shared outside without violating the PCI-SIG NDA). We participated in the event with multiple systems and can report that our systems have done quite well. The test ecosystem is not mature yet, and a few more FYI workshops will be conducted before the official compliance for 6.0 is launched. We have collaborated with all the key test vendors for electrical and protocol testing throughout the year. As early as the middle of last year, we were able to provide test cards to all these vendors to demo PCIe 6.0 capabilities in their booths at various events. Many of them recorded these videos, and they can be found online.

• Cadence Subsystem IP for PCIe 6.0: Protocol and Electrical Testing
• Cadence Subsystem IP for CXL Protocol Test Demo
• Cadence Subsystem IP for CXL2.0/3.0 Protocol Test Demo
• Cadence Subsystem IP for PCIe 6.0: Protocol Stack Demo

More at the PCI-SIG Developers Conference

Check us out at the PCI-SIG Developer’s conference on June 12 and 13 to see the following demonstrations:

• Robust performance of Cadence IP for PCIe 7.0 transmitting and receiving 128GT/s signals over non-retimed optics
• Capabilities of Cadence IP for PCIe 7.0 measured using oscilloscope instrumentation detailing its stable electrical performance and margin
• The reliability of Cadence IP for PCIe 6.0 interface using Test Equipment to characterize the PHY receiver quality
• A PCI-SIG-compliant Cadence IP subsystem for PCIe 6.0 optimized for both power and performance

As a leader in PCI Express, Anish Mathew of Cadence will share his valuable insights on an important topic: “Impact of UIO ECN on PCIe Controller Design and Performance,” highlighting the strides made by the Cadence design team in achieving this implementation.

Figure 6: Cadence UIO Implementation Summary

Summary

Cadence showcased PCIe 7.0-ready IP at PCI-SIG Developers Conference 2023 and continues to lead in PCIe IP development, offering complete solutions in advanced nodes for PCIe 7.0 that will be generally available early next year. With a full suite of solutions encompassing PHYs, Controllers, Software, and Verification IP, Cadence is proud to be a member of the PCI-SIG community and is heavily invested in PCIe. Cadence was the first IP provider to bring complete subsystem solutions for PCIe 3.0, 4.0, 5.0, and 6.0 with industry-leading PPA and we are proud to continue this trend with our latest IP subsystem solution for PCIe 7.0, which sets new benchmarks for power, performance, area, and time to market.

We live in a rapidly growing “digitalized world,” with an ever-increasing need for video/music streaming, gaming, AI/machine learning, etc. All of these propel demand on modern SoC design to quickly evolve the SoC by fitting more sophisti...(read more)

The automotive industry is currently on the cusp of a radical evolution, steering towards a future where cars are not just vehicles but sophisticated, software-defined vehicles (SDV). This shift is marked by an increased reliance on automation and a significant increase in the use of sensors to improve safety and reliability. However, the increasing number of sensors has led to higher compute demands and poses challenges in managing a wide variety of data. The traditional method of using separate processors to manage each sensor's data is becoming obsolete. The current trends necessitate a unified processing system that can deal with multimodal sensor data, utilizing traditional Digital Signal Processing (DSP) and AI-driven algorithms. This approach allows for more efficient and reliable sensor fusion, significantly enhancing vehicle perception. Developers often face difficulties adhering to stringent power, performance, area, and cost (PPAC) and timing constraints while designing automotive SoCs.

Cadence, with its groundbreaking products and AI-powered processors, is enabling designers and automotive manufacturers to meet the future sensor fusion demands within the automotive sector. At the recent CadenceLive Silicon Valley 2024, Amol Borkar, product marketing director at Cadence, showcased the company's dedication and forward-thinking solutions in a captivating presentation titled "Addressing Tomorrow’s Sensor Fusion Needs in Automotive Computing with Cadence." This blog aims to encapsulate the pivotal takeaways from the presentation. If you missed the chance to watch this presentation live, please click here to watch it.

Significant Trends in the Automotive Market – Industry Landscape

We are witnessing a revolution in automotive technology. Innovations like occupant and driver monitoring systems (OMS, DMS), 4D radar imaging, LiDAR technology, and 360-degree view are pushing the boundaries of what's possible, leading us into an era of remarkable autonomy levels—ranging from no feet or hands required to eventually no eyes needed on the road.

Sensor Fusion and Increasing Processing Demands—Sensor fusion effectively integrates data from different sensors to help vehicles understand their surroundings better. Its main benefit is in overcoming the limitations of individual sensors. For example, cameras provide detailed visual information but struggle in low-light or lousy weather. On the other hand, radar is excellent at detecting objects in these conditions but lacks the detail that cameras provide. By combining the data from multiple sensors, automotive computing can take advantage of their strengths while compensating for their weaknesses, resulting in a more reliable and robust system overall.

One thing to note is that the increased number of sensors produces various data types, leading to more pre-processing.

On-Device Processing—As the industry moves towards autonomy, there is an increasing need for on-device data processing instead of cloud computing to enable vehicles to make informed decisions. Embracing on-device processing is a significant advancement for facilitating real-time decisions and avoiding round-trip latency.

AI Adoption—AI has become integral to automotive applications, driving safety, efficiency, and user experience advancements. AI models offer superior performance and adaptability, making future-proofing a crucial consideration for automotive manufacturers. AI significantly enhances sensor fusion algorithms, offering scalability and adaptability beyond traditional rule-based approaches. Neural networks enable various fusion techniques, such as early fusion, late fusion, and mid-fusion, to optimize the integration and processing of sensor data.

Future Sensor Fusion Needs

Automotive architectures are continually evolving. With current trends and AI integration into radar and sensor fusion applications, SoCs should be modular, flexible, and programmable to meet market demands.

Heterogeneous Architecture- Today's vehicles are loaded with various sensors, each with a unique processing requirement. Running the application on the most suitable processor is essential to achieve the best PPA. To meet such requirements, modern automotive solutions require a heterogeneous compute approach, integrating domain-specific digital signal processors (DSPs), neural processing units (NPUs), central processing unit (CPU) clusters, graphics processing unit (GPU) clusters, and hardware accelerator blocks. A balanced heterogeneous architecture gives the best PPA solution.

Flexibility and Programmability- The industry has come a long way from using computer vision algorithms such as HOG (Histogram Oriented Gradient) to detect people and objects, HAR classifier to detect faces, etc., to CNN and LSTM-based AI to Transformer models and graphical neural networks (GNN). AI has evolved tremendously over the last ten years and continues to evolve. To keep up with the evolving rate of AI, SoC design must be flexible and programmable for updates if needed in the future.

Addressing the Sensor Fusion Needs with Cadence

Cadence offers a complete suite of hardware and software products to address the increasing compute requirements in automotive. The comprehensive portfolio of Tensilica products built on the robust 32-bit RISC architecture caters to various automotive CPU and AI needs. What makes them particularly appealing is their scalability, flexibility, and configurability, offering many options to meet diverse needs.

The Xtensa family of products offers high-quality, power-efficient CPUs. Tensilica family also includes AI processors like Neo NPUs for the best power, performance, and area (PPA) for AI inference on devices or more extensive applications. Cadence also offers domain-specific products for DSPs such as HIFI DSPs, specialized DSPs and accelerators for radar and vision-based processing, and a general-purpose family of products for floating point applications.

The ConnX family offers a wide range of DSPs, from compact and low-power to high-performance, optimized for radar, lidar, and communications applications in ADAS, autonomous driving, V2X, 5G/LTE/4G, wireless communications, drones, and robotics. Tensilica's ISO26262 certification ensures compliance with automotive safety standards, making it a trusted partner for advanced automotive solutions. The Cadence NeuroWeave Software Development Kit (SDK) provides customers with a uniform, scalable, and configurable ML interface and tooling that significantly improves time to market and better prepares them for a continuously evolving AI market. Cadence Tensilica offers an entire ecosystem of software frameworks and compilers for all programming styles.

Tensilica's comprehensive software stack supports programming for DSPs, NPUs, and accelerators using C++, OpenCL, Halide, and various neural network approaches. Middleware libraries facilitate applications such as SLAM, radar processing, and Eigen libraries, providing robust support for automotive software development.

Conclusion

Cadence’s Tensilica products offer a development toolchain and various IPs tailored for the automotive industry, covering audio, vision, radar, unified DSPs, and NPUs. With ISO certification and a robust partner ecosystem, Tensilica solutions are designed to meet the future needs of automotive computing, ensuring safety, efficiency, and innovation.

Learn More

• Cadence Automotive Solutions
• Cadence Automotive IP
• Sensor Fusion and ADAS in TSMC Automotive Processes
• Revolution on the Road: How Cadence is Driving the Future of Automotive Design!
• Taming Design Complexity in Chiplet-Based Automotive Electronics
• UCIe and Automotive Electronics: Pioneering the Chiplet Revolution

Hi,

I hope you are doing well.

I have designed and simulated a PA system in Cadence using high-level blocks, which include both ideal components and some defined with Verilog-A. My goal is to calculate the Bit Error Rate (BER) and Error Vector Magnitude (EVM) in the system. I am using an LTE source from RFLib, and everything functions correctly in the transient simulation.

To calculate these parameters, I intended to use envelope simulation. However, when I attempt to run the envelope simulation, I encounter convergence errors, which prevent it from working as expected.

Given this issue, I believe I need to work with transient data instead. Could you please advise on how to approach this in Cadence without exporting the data to MATLAB?

Thank you for your assistance.