1 Czech Republic Koruna = 0.7302 South African Rand

1 Czech Republic Koruna = 24.0723 CFA Franc BCEAO

1 Czech Republic Koruna = 0.3974 Venezuelan Bolivar Fuerte

1 Czech Republic Koruna = 0.6169 Maldivian Rufiyaa

1 Czech Republic Koruna = 12.8574 Hungarian Forint

1 Czech Republic Koruna = 0.0896 Fiji Dollar

1 Czech Republic Koruna = 0.0386 Swiss Franc

1 Bolivian Boliviano = 2.6612 South African Rand

1 Bolivian Boliviano = 87.7361 CFA Franc BCEAO

1 Bolivian Boliviano = 1.4484 Venezuelan Bolivar Fuerte

1 Bolivian Boliviano = 2.2483 Maldivian Rufiyaa

1 Bolivian Boliviano = 46.8612 Hungarian Forint

1 Bolivian Boliviano = 0.3267 Fiji Dollar

1 Bolivian Boliviano = 0.1408 Swiss Franc

1 Japanese Yen = 0.172 South African Rand

1 Japanese Yen = 5.6714 CFA Franc BCEAO

1 Japanese Yen = 0.0936 Venezuelan Bolivar Fuerte

1 Japanese Yen = 0.1453 Maldivian Rufiyaa

1 Japanese Yen = 3.0292 Hungarian Forint

1 Japanese Yen = 0.0211 Fiji Dollar

1 Japanese Yen = 0.0091 Swiss Franc

Herodotus once wrote:

“The counting was done by first packing ten thousand men as close together as they could stand and drawing a circle round them on the ground; they were then dismissed, and a fence, about navel high, was constructed around the circle; finally, other troops were marched into the area thus enclosed and dismissed in their turn, until the whole army had been counted.”

Whose army?

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In the book “The World of _____” by Bennett Alan Weinberg and Bonnie K Bealer, there is a photograph of a label from a jar of pharmaceutical-grade crystals. It reads:

“WARNING: MAY BE HARMFUL IF INHALED OR SWALLOWED. HAS CAUSED MUTAGENIC AND REPRODUCTIVE EFFECTS IN LABORATORY ANIMALS. INHALATION CAUSES RAPID HEART RATE, EXCITEMENT, DIZZINESS, PAIN, COLLAPSE, HYPOTENSION, FEVER, SHORTNESS OF BREATH. MAY CAUSE HEADACHE, INSOMNIA, VOMITING, STOMACH PAIN, COLLAPSE AND CONVULSIONS.”

Fill in the blank.

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In Texas Hold’em Poker, which hand is known as ‘six tits’?

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That’s what Pakistan can become, warns Patrick French. (Via Nikhil Mehra.)

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Finally, sanity.  Concerned about the level of electronic waste created by discarded phone chargers, the European Commission has told mobile phone manufacturers that they must adopt a standard.  This will hopefully have the additional advantage of reducing blood pressures if we no longer need to rummage in our desk drawers frantically searching for the right charger. 

I wonder whether manufacturers would have voluntarily adopted a standard without external influence.  The choice of how to wire our "wireless" appliances seems to offer so little differentiation, and standards are so freely available that I am surprised that this hasn't happened sooner. 

Unfortunately, there are few parallels in the EDA/manufacturability world.  EDA products derive a significant part of their differentiation from the range and types of data that they can connect to, particularly in the case of enabling information such as library and technology files. 

The good news is that technology file standards are becoming available that could replace what were once proprietary formats, and there is motivation to adopt the standards because our foundry partners (as well as our customers) evidently recognize the value of common formats.  Whether the foundries can agree among themselves on common formats remains to be seen. 

I've been blogging a lot about Assura recently, so I thought I would continue by talking about rule decks. 

Inside Cadence, we maintain a database that shows which foundries support which process for which products.  This means that we can quickly give you an answer if you are considering using a new process or foundry, and you want to know whether Assura is supported.  Your friendly local Cadence physical verification AE has access to this information and should be able to answer your questions about rule deck support. 

Our Assura R&D team is constantly working with the foundries to help update existing rule decks and create new ones.  But with all due respect to our foundry partners, their field support teams are not always aware of the latest efforts on rule deck creation and support. 

Of course, it's important to check the status of Assura support with your foundry.  This has the added benefit to Cadence that it lets them know that you're using Assura.  But please also double-check with your Cadence AE, who can ping me to make sure that you're getting the latest information. 

Earning calls sure are interesting! Below is an excerpt from the TSMC Q209 call (transcript from seekingalpha). The discussion revolves around the 40nm yield issues and TSMC's ramp to improving the yield. Dr. Liu really hits on a key element of DFM...(read more)

It was a sunny, Sunday afternoon in Anaheim (across from Disneyland). That combination of weather and entertainment didn't sway a group of 35 engineers from participating in the DFMC (Design for Manufacturability Coalition) Workshop at DAC 2010. On...(read more)

What is the meaning of this error?

I used already two ports (PORT1 and PORT2 for input and output, respectively.

-------------------------------------------------------------------------------------------------------------------------

Also when I apply the PSP analysis for S-parameter the value of maximum S21 value (4.75 dB) is much lower than the maximum power gain (17.6 dB).

while the same circuit is designed using  ADS program the two values are approximately the same around (17.1 dB).

Hi,

I'm doing the "The Targeted Fault Campaign" with ncsim and got stuck at the following message: "ncsim: *E,FLTIGF: [FLT] Failed to inject fault at circuit_tb.U0.n2174." I already tried with other NETs, with SET, SA0, SA1, always the same error occurs.

$nchelp ncsim FLTIGF
$ncsim/FLTIGF =
    Injection time is not within the expected finish
    time for the specified fault node. Failed to inject fault.

As can be seen below, the injection time is at 2ns and the -fault_good_run -fault_tw 1ns:100ns, so in theory 2ns is inside the window 1ns:100ns.

My scripts so far, considering I already compiled the Verilog testbench and also the gates from the technology library (gate-level simulation):

#this runs ok

ncelab -work worklib -cdslib circuit/trunk/backend/synthesis/work/cds.lib -logfile ncelab.log -errormax 15 -access +wc -status -timescale 1ps/1ps worklib.circuit_tb -fault_file circuit/trunk/backend/synthesis/scripts/fi.list

#this runs ok
ncsim -fault_good_run -fault_tw 1ns:100ns -fault_work fault_db -fault_overwrite worklib.circuit_tb:module -input ../scripts/fs_strobe.tcl -exit

#this runs NOT OK
ncsim -fault_sim_run -fault_work fault_db worklib.circuit_tb:module -input ../scripts/injection.tcl -exit

After the above command, I get: "ncsim: *E,FLTIGF: [FLT] Failed to inject fault at circuit_tb.U0.n2174."

Here are the files called from the commands above.

fi.list:

fault_target circuit_tb.U0.n2174 -type SET+SA1+SA0

fs_strobe.tcl:

fs_strobe circuit_tb.WRITE_OUT circuit_tb.PC_OUT[0]

injection.tcl:

fault -stop_severity 3 -inject -time 2ns -type sa1 circuit_tb.U0.n2174

I already checked the NETs with simvision, so their paths are correct.

I'm using as reference the following document: "Functional Safety Simulation - Product Version 15.2 - April 2016"

Any ideas are welcome.

Thank you in advance.

Hi,

I'm doing the "The Targeted Fault Campaign" with ncsim and got stuck at the following message: "ncsim: *E,FLTIGF: [FLT] Failed to inject fault at circuit_tb.U0.n2174." I already tried with other NETs, with SET, SA0, SA1, always the same error occurs.

$nchelp ncsim FLTIGF
$ncsim/FLTIGF =
    Injection time is not within the expected finish
    time for the specified fault node. Failed to inject fault.

As can be seen below, the injection time is at 2ns and the -fault_good_run -fault_tw 1ns:100ns, so in theory 2ns is inside the window 1ns:100ns.

My scripts so far, considering I already compiled the Verilog testbench and also the gates from the technology library (gate-level simulation):

#this runs ok

ncelab -work worklib -cdslib circuit/trunk/backend/synthesis/work/cds.lib -logfile ncelab.log -errormax 15 -access +wc -status -timescale 1ps/1ps worklib.circuit_tb -fault_file circuit/trunk/backend/synthesis/scripts/fi.list

#this runs ok
ncsim -fault_good_run -fault_tw 1ns:100ns -fault_work fault_db -fault_overwrite worklib.circuit_tb:module -input ../scripts/fs_strobe.tcl -exit

#this runs NOT OK
ncsim -fault_sim_run -fault_work fault_db worklib.circuit_tb:module -input ../scripts/injection.tcl -exit

After the above command, I get: "ncsim: *E,FLTIGF: [FLT] Failed to inject fault at circuit_tb.U0.n2174."

Here are the files called from the commands above.

fi.list:

fault_target circuit_tb.U0.n2174 -type SET+SA1+SA0

fs_strobe.tcl:

fs_strobe circuit_tb.WRITE_OUT circuit_tb.PC_OUT[0]

injection.tcl:

fault -stop_severity 3 -inject -time 2ns -type sa1 circuit_tb.U0.n2174

I already checked the NETs with simvision, so their paths are correct.

I'm using as reference the following document: "Functional Safety Simulation - Product Version 15.2 - April 2016"

Any ideas are welcome.

Thank you in advance.

I could barely recognize Ben Foster in 3:10 to Yuma, but I was blown away just the same by him as in his star making turn from Hostage. What makes Foster so special in Yuma?

Yuma contains two of Hollywood’s finest: Russell Crowe and Christian Bale. Bale is excellent, Crowe a little too relaxed to be cock-sure-dangerous. Both are unable to provide the powder-keg relationship that the movie demands.

Into this void steps Ben Foster. He plays Charlie Prince, sidekick to Crowe’s dangerous and celebrated outlaw Ben Wade. When Wade is captured, Prince is infuriated. He initiates an effort suffused with desperate passion to rescue his boss.

Playing Prince with a mildly effeminate gait, Foster quickly becomes the movie’s beating heart. What struck me in particular was that Foster was able to balance method acting with just plain good acting. He plays his character organically but isn’t above drawing attention with controlled staginess.

Gradually, Foster’s willingness to control a scene blend in with that of Prince’s. Is the character manipulating his circumstances in the movie or is it the actor playing a fine hand? Foster is so entertaining, the answer is immaterial.

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This new film is the latest remake of Devdas, but what is equally interesting is the fact that it is in conversation with films made in the West. Unlike Bhansali’s more spectacular version of the older story, Anurag Kashyap’s Dev.D is a genuine rewriting of Sarat Chandra’s novel. Kashyap doesn’t flinch from depicting the individual’s downward spiral, but he also gives women their own strength. He has set out to right a wrong—or, at least, tell a more realistic, even redemptive, story. If these characters have lost some of the affective depth of the original creations, they have also gained the hard edges of modern lives.

We don’t always feel the pain of Kashyap’s characters, but we are able to more readily recognize them. Take Chandramukhi, or Chanda, who is a school-girl humiliated by the MMS sex-scandal. Her father, protective and patriarchal, says that he has seen the tape and thinks she knew what she was doing. “How could you watch it?” the girl asks angrily. And then, “Did you get off on it?” When was the last time a father was asked such a question on the Hindi screen? With its frankness toward sex and masturbation, Dev.D takes a huge step toward honesty. In fact, more than the obvious tributes to Danny Boyle’s Trainspotting, or the over-extended psychedelic adventure on screen, in fact, as much as the moody style of film-making, the candour of such questions make Dev.D a film that is truly a part of world cinema.

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I loved Nina Paley’s brilliant animated film Sita Sings the Blues. If you’re reading this, stop right now—and watch the film here.

Paley has set the story of the Ramayana to the 1920s jazz vocals of Annette Hanshaw. The epic tale is interwoven with Paley’s account of her husband’s move to India from where he dumps her by e-mail. The Ramayana is presented with the tagline: “The Greatest Break-Up Story Ever Told.”

All of this should make us curious. But there are other reasons for admiring this film:

The film returns us to the message that is made clear by every village-performance of the Ramlila: the epics are for everyone. Also, there is no authoritative narration of an epic. This film is aided by three shadow puppets who, drawing upon memory and unabashedly incomplete knowledge, boldly go where only pundits and philosophers have gone before. The result is a rendition of the epic that is gloriously a part of the everyday.

This idea is taken even further. Paley says that the work came from a shared culture, and it is to a shared culture that it must return: she has put the film on Creative Commons—viewers are invited to distribute, copy, remix the film.

Of course, such art drives the purists and fundamentalists crazy. On the Channel 13 website, “Durgadevi” and “Shridhar” rant about the evil done to Hinduism. It is as if Paley had lit her tail (tale!) and set our houses on fire!

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A focus on customer enablement across all Cadence sub-organizations has led to a cross-functional effort to identify opportunities to bring our customers to proficiency with our products and flows. Hence, Rapid Adoption Kits -- RAKs -- for Synthesis...(read more)

Best Practices for Optimization What should be my considerations while preparing data? Libraries, HDL, Constraints... A good result from a synthesis tool depends greatly on the input data. An old saying "garbage in garbage out" is also true for...(read more)

Cadence is hosting a Front End Design Summit on Thursday, December 6, 2012 9:30am – 5:00pm at Cadence San Jose headquarters, 2655 Seely Avenue, Building 10. Logic designers will hear from customers including Cisco, Chelsio, PMC, Spansion, and Via Technologies...(read more)

Cadence Encounter® Test uses breakthrough timing-aware and power-aware technologies to enable customers to manufacture higher quality, power-efficient silicon faster and at lower cost. Encounter Diagnostics identifies critical yield-limiting issues and...(read more)

How to use Encounter® RTL Compiler support Interface Logic Models during synthesis.(read more)

Cadence's Digital Front-End Design Team first introduced the concept of a Rapid Adoption Kit (RAK) , self-guided and learn-by-doing training material, over two and a half years ago, helping its users across the globe deploy new products and flows. These...(read more)

The design and physical implementation engineers involved in early to late stage synthesis require a flow that helps them investigate timing using a structured and physically aware approach. Cadence Encounter® RTL Compiler (RC) Timing Analyzer was developed...(read more)

Cadence offers a new Rapid Adoption Kit for logic built in self test tasks.(read more)

Hello Encounter Test Users, In this blog, I would like to introduce a few knowledge artifacts that will provide an easy way for you to learn about and stay productive with this product, technology, and methodology. In addition, this will also help to...(read more)

Limny CMS version 2.0 suffers from a cross site request forgery vulnerability that allows for a malicious attacker to have an administrator account created. Proof of concept code included.

FileExecutive suffers from file disclosure, path disclosure, shell upload, edit administrator and add administrator vulnerabilities.

NinkoBB version 1.3RC4 change / add administrator cross site request forgery exploit.

Advanced Management For Services Sites remote add administrator exploit.

112 bytes small Win32/PerfectXp-pc1/sp3 (Tr) add administrator shellcode.