Make no mistake, it still has a brake pedal, but in regular driving conditions you might not need to use it

Product announcements from day one of Medallia Experience 2018

After 21 employees of Ahmedabad-based Cadila Pharmaceuticals were found to be corona positive, the administration acted quickly and sanitised the entire campus of the company near Dholka.

The doors of the eleventh jyotirlinga at Kedarnath in the Garhwal Himalayas were opened at 6.10 am.

The company manufactures 38 APIs and intermediates across various therapeutic categories — respiratory, diabetology, gastroenterology, pain management, orthopedics, etc. The company has more than 850 formulation products.

1. PUBG Mobile Lite BC Generator: All you need to know  Sportskeeda
2. PUBG Mobile 0.18.0 adds sandstorm weather effects to Miramar, Cheer Park, and a bunch of other changes  XDA Developers
3. PUBG Mobile: Here’s a crash course in all the game pointers a newbie will ever need  Hindustan Times
4. PUBG Mobile Mad Miramar Sandstorm Mode to Arrive on May 12  News18
5. How To Earn free 1800 UC in PUBG Mobile with Bonus Challenge  Sportskeeda
6. View Full coverage on Google News

First, the good news. The EDA industry will grow from $6.2 billion in 2015 to $9.0 billion in 2019, according to Gary Smith, chief analyst at Gary Smith EDA. Year-to-year growth rates will range from +4% to +11.2%.

But in his annual presentation on the eve of the Design Automation Conference (DAC 2015), Smith noted that Wall Street is unimpressed. “The people I talk to want long-term steady growth, no sharp up-turns, no sharp downturns,” Smith said. “To the rest of Wall Street, we’re boring.”

Smith spent the rest of his talk noting how EDA can be a lot less boring and, potentially, a whole lot bigger. For starters, what if we add semiconductor IP to EDA revenues? Now we’re looking at $12.2 billion in revenue by 2019, Smith said. (He acknowledged, however, that the IP market itself is going to take a “dip” due to the move towards platform-based IP and away from conventional piecemeal IP).

This still is not enough to get Wall Street’s attention. Another possibility is to bring embedded software development into the EDA industry. This is not a huge market – about $2.6 billion today – but it is an “easy growth market for us,” according to Smith.

Chasing the Big Bucks

But the “big bucks” are in mechanical CAD (MCAD), Smith said. In the past the MCAD market has always been bigger than EDA, but now EDA is catching up. The MCAD market is about $6.6 billion now. Synopsys and Cadence are larger than PTC and Siemens, two of the main players in MCAD.

There may be some good acquisition possibilities coming up for EDA vendors, Smith said – and if we don’t buy MCAD companies, they might buy EDA companies. Consider, for example, that Ansoft bought Apache and Dassault bought Synchronicity. (Note: Siemens PLM Software is a first-time exhibitor at DAC 2015).

What about other domains? Smith said that EDA companies could conceivably move into optical design, applications development software, biomedical design, and chemical design. The last if these is probably the most tenuous; Smith noted that EDA vendors have yet to look into chemical design.

Applications development software is the biggest market on the above list, but that means competing with Microsoft, IBM, and Oracle. “You’re in with the big boys – is that a good idea?” Smith asked.

Perhaps there’s an opening for a “big play” for an MCAD provider. Smith noted that mechanical vendors are focusing on product data management (PDM). This “is really the IT of design,” Smith said. “They have a lot of hope that the IoT [Internet of things] market is going to give them an opportunity to capture the software that goes from the ground to the cloud. Maybe we can let them have PDM and see if we can take the tool market away from them, or acquire it away from them.”

In conclusion, Smith asked, should the EDA industry accelerate its growth? “The mechanical vendors have already shown interest in acquiring EDA vendors,” he said. “We may not have a choice.”

Richard Goering

NOTE: Catch our live blog from DAC 2015, beginning Monday morning, June 8! Click here

As a leading venture capitalist in the electronics technology, as well as CEO of Cadence, Lip-Bu Tan has unique insights into ongoing changes that will impact EDA providers and users. Tan shared some of those insights in a “fireside chat” with Ed Sperling, editor in chief of Semiconductor Engineering, at the Design Automation Conference (DAC 2015) on June 9.

Topics of this discussion included industry consolidation, the need for more talent and more startups, Internet of Things (IoT) opportunities and challenges, the shift from ICs to full product development, and the challenges of advanced nodes. Following are some excerpts from this conversation, held at the DAC Pavilion theater on the exhibit floor.

Ed Sperling (left) and Lip-Bu Tan (right) discuss trends in semiconductors and EDA

Q: As you look out over the semiconductor and EDA industries these days, what worries you most?

Tan: At the top of my list is all the consolidation that is going on. Secondly, chip design complexity is increasing substantially. Time-to-market pressure is growing and advanced nodes have challenges.

The other thing I worry about is that we need to have more startups. There’s a lot of innovation that needs to happen. And this industry needs more top talent. At Cadence, we have a program to recruit over 10% of new hires every year from college graduates. We need new blood and new ideas.

Q: EDA vendors were acquiring companies for many years, but now the startups are pretty much gone. Where does the next wave of innovation come from?

Tan: I’ve been an EDA CEO for the last seven years and I really enjoy it because so much innovation is needed. System providers have very big challenges and very different needs. You have to find the opportunities and go out and provide the solutions.

The opportunities are not just in basic tools. Massive parallelism is critical, and the power challenge is huge. Time to market is critical, and for the IoT companies, cost is going to be critical. If you want to take on some good engineering challenges, this is the most exciting time.

Q: You live two lives—you’re a CEO but you’re also an investor. Where are the investments going these days and where are we likely to see new startups?

Tan: Clearly everybody is chasing the IoT. There is a lot of opportunity in the cloud, in the data center. Also, I’m a big believer in video, so I back companies that are video related. A big area is automotive. ADAS [Advanced Driver Assistance Systems] is a tremendous opportunity.

These companies can help us understand how the industry is transforming, and then we can provide solutions, either in terms of IP, tools, or the PCB. Then we need to connect from the system level down to semiconductors. I think it’s a different way to design.

Q: What happens as we start moving from companies looking to design a semiconductor to system companies who are doing things from the perspective that we have this purpose for our software?

Tan: We are extending from EDA to what we call system design enablement, and we are becoming more application driven. The application at the system level will drive the silicon design. We need to help companies look at the whole system including the power envelope and signal integrity. You don’t want to be in a position where you design a chip all the way to fabrication and then find the power is too high.

We help the customers with hardware/software co-design and co-verification. We have a design suite and a verification suite that can provide customers with high-level abstractions, as well as verify IP blocks at the system level. Then we can break things down to the component level with system constraints in mind, and drive power-aware, system-aware design.

We are starting to move into vertical markets. For example, medical is a tremendous opportunity.

Q: How does this approach change what you provide to customers?

Tan: Every year I spend time meeting with customers. I think it is very important to understand what they are trying to design, and it is also important to know the customer’s customer requirements. We might say, “Wait a minute, for this design you may want to think about power or the library you’re using.” We help them understand what foundry they should use and what process they should use. They don’t view me as a vendor—they view me as a partner.

We also work very closely with our IP and foundry partners. We work as one team—the ultimate goal is customer success.

Q: Is everybody going to say, FinFETs are beautiful, we’re going to go down to 10nm or 7nm—or is it a smaller number of companies who will continue down that path?

Tan: Some of the analog/mixed-signal companies don’t need to go that far. We love those customers—we have close to 50% of that business. But we also have customers in the graphics or processor area who are really pushing the envelope, and need to be in 16nm, 14nm, or 10nm. We work very closely with those guys to make sure they can go into FinFETs.

We always want to work with the customer to make sure they have a first-time silicon success. If you have to do a re-spin, you miss the opportunity and it’s very costly.

Q: There’s a new market that is starting to explode—IoT. How real is that world to you? Everyone talks about large numbers, but is it showing up in terms of tools?

Tan: Everybody is talking about huge profits, but a lot of the time I think it is just connecting old devices that you have. Billions of units, absolutely yes, but if you look close enough the silicon percentage of that revenue is very tiny. A lot of the profit is on the service side. So you really need to look at the service killer app you are trying to provide.

What’s most important to us in the IoT market is the IP business. That’s why we bought Tensilica—it’s programmable, so you can find the killer app more quickly. The other challenges are time to market, low power, and low cost.

Q: Where is system design enablement going? Does it expand outside the traditional market for EDA?

Tan: It’s not just about tools. IP is now 11% of our revenue. At the PCB level, we acquired a company called Sigrity, and through that we are able to drive system analysis for power, signal integrity, and thermal. And then we look at some of the verticals and provide modeling all the way from the system level to the component level. We make sure that we provide a solution to the end customer, rather than something piecemeal.

Q: What do you think DAC will look like in five years?

Tan: It’s getting smaller. We need to see more startups and innovative IP solutions. I saw a few here this year, and that’s good. We need to encourage small startups.

Q: Where do we get the people to pull this off? I don’t see too many people coming into EDA.

Tan: I talk to a lot of university students, and I tell them that this small industry is a gold mine. A lot of innovation is needed. We need them to come in [to EDA] rather than join Google or Facebook. Those are great companies, but there is a lot of fundamental physical innovation we need.

Richard Goering

Related Blog Posts

- Gary Smith at DAC 2015: How EDA Can Expand Into New Directions

- DAC 2015: Google Smart Contact Lens Project Stretches Limits of IC Design

- Q&A with Nimish Modi: Going Beyond Traditional EDA

Let’s face it – the EDA industry needs new people and new ideas. One of the best places to find both is academia, and a presentation at the Cadence Theater at the recent Design Automation Conference (DAC 2015) described collaboration models that are working today.

The presentation was titled “Industry/Academia Engagement Models – From PhD Contests to R&D Collaborations.” It included these speakers, shown from left to right in the photo below:

• Prof. Xin Li, Electrical and Computer Engineering, Carnegie-Mellon University (CMU)
• Chuck Alpert, Senior Software Architect, Cadence
• Prof. Laleh Behjat, Department of Electrical and Computer Engineering, University of Calgary

Alpert, who was filling in for Zhuo Li, Software Architect at Cadence, was the vice chair of DAC 2015 and will be the general chair of DAC 2016 in Austin, Texas. “My team at Cadence really likes to collaborate with universities,” he said. “We’re a big proponent of education because we really need the best and brightest students in our industry.”

Contests Boost EDA Research

One way that Cadence collaborates with academia is participation in contests. “It’s a great way to formulate problems to academia,” Alpert said. “We can have the universities work on these problems and get some strategic direction.”

For example, Cadence has been involved with the annual CAD contest at the International Conference on Computer-Aided Design (ICCAD) since the contest was launched in 2012. This is the largest worldwide EDA R&D contest, and it is sponsored by the IEEE Council on EDA (CEDA) and the Taiwan Ministry of Education. Its goals are to boost EDA research in advanced real-world problems and to foster industry-academia collaboration.

Contestants can participate in one of more problems in the three areas of system design, logic synthesis and verification, and physical design. The 2015 contest has attracted 112 teams from 12 regions. Cadence contributes one problem per year in the logic synthesis area. Zhuo Li was the 2012 co-chair and the 2013 chair. The awards will be given at ICCAD in November 2015.

Another step that Cadence has taken, Alpert said, is to “hire lots of interns.” His own team has four interns at the moment. One advantage to interning at Cadence, he said, is that students get to see real-world designs and understand how the tools work. “It helps you drive your research in a more practical and useful direction,” he said.

The Cadence Academic Network co-sponsors the ACM SIGDA PhD Forum at DAC, and Xin Li and Zhuo Li are on the organizing committee. This event is a poster session for PhD students to present and discuss their dissertation research with people in the EDA community. This year’s forum was “packed,” Alpert said, and it’s clear that the event needs a bigger room.

Finally, Alpert noted, Cadence researchers write and publish technical papers at DAC and other conferences, and Cadence people serve on the DAC technical program committee. “We try to be involved with the academic community on a regular basis,” Alpert said. “We want the best and the brightest people to go into EDA because there is still so much innovation that’s needed. It’s a really cool place to be.”

Research Collaboration Exposes Failure Rates

Xin Li presented an example of a successful research collaboration between CMU and Cadence. The challenge was to find a better way to estimate potential failure rates in memory. As noted in a previous blog post, PhD student Shupeng Sun met this challenge with a new statistical methodology that won a Best Poster award at the ACM SIGDA PhD Forum at DAC 2014.

The new methodology is called Scaled-Sigma Sampling (SSS). It calculates the failure rate and accounts for variability in the manufacturing process while only requiring a few hundred, or a few thousand, sample circuit blocks. Previously, millions of samples were required for an accurate validation of a new design, and each sample could take minutes or hours to simulate. It could take a few weeks or months to run one validation.

The SSS methodology requires greatly reduced simulation times. It makes it possible, Li noted, to run simulations overnight and see the results in the morning.

Li shared his secret for success in collaborations. “I want to emphasize that before the collaboration, you have to understand the goal. If you don’t have a clear goal, don’t collaborate. Once you define the goal, stick to it and make it happen.”

Contest Provides Learning Experience

Last year Laleh Behjat handed two of her new PhD students a challenge. “I told them there is an ISPD [International Symposium for Physical Design] contest on placement, and I expect you to participate and I expect you to win. Not knowing anything about placement, I don’t think they realized what I was asking them.”

The 2015 contest was called the Blockage-Aware Detailed Routing-Driven Placement Contest. Results were announced at the end of March at ISPD. And the University of Calgary team, despite its lack of placement experience, took second place.

Such contests provide a good learning tool, according to Behjat. Graduate students in EDA, she said, “have to be good programmers. They have to work in teams and be collaborative, be able to innovate, and solve the hardest problems I have seen in engineering and science. And they have to think outside the box.” A contest can bring out all these attributes, she said.

Further, Behjat noted, contest participants had access to benchmarks and to a placement tool. They didn’t have to write tools to find out if their results were good. Industry sponsors, meanwhile, got access to good students and new approaches for solving problems.

“You can see Cadence putting a big amount of time, effort and money to get students here and get them excited about doing contests,” she said. She advised students in the theater audience to “talk to people in the Cadence booth and see if you can have more ideas for collaboration.”

Richard Goering

Related Blog Posts

EDA Plus Academia: A Perfect Game, Set and Match

Cadence Aims to Strengthen Academic Partnerships

BSIM-CMG FinFET Model – How Academia and Industry Empowered the Next Transistor

In 1985, as a relatively new editor at Computer Design magazine, I was asked to go forth and cover a new business called CAE (computer-aided engineering). I knew nothing about it, but I had been writing about design for test, so there seemed to be somewhat of a connection. Little did I know that “CAE” would turn into “EDA” and that I’d write about it for the next 30 years, for Computer Design, EE Times, Cadence, and a few others.

Now that I’m about to retire, I’m looking back over those 30 years. What a ride it has been! By the numbers I covered 31 Design Automation Conferences (DACs), hundreds of new products, dozens of acquisitions and startups, dozens of lawsuits, and some blind alleys that didn’t work out (like “silicon compilation”). Chip design went from gate arrays and PLDs with a few thousand gates to processors and SoCs with billions of transistors.

In 1985 there were three big CAE vendors – Daisy Systems, Mentor Graphics, and Valid Logic. All sold bundled packages that included workstations and CAE software; in fact, Daisy and Valid designed and manufactured their own workstations. In the early 1980s a workstation with schematic capture and gate-level logic simulation might have set you back $120,000. In 1985 OrCAD, now part of Cadence, came out with a $500 schematic capture package running on IBM PCs.

Cadence and Synopsys emerged in the late 1980s, and by the 1990s the EDA industry was pretty much a software-only business (apart from specialized machines like simulation accelerators). Since the early 1990s the “big three” EDA vendors have been Cadence, Synopsys, and Mentor, giving the industry stability but allowing for competition and innovation.

Here, in my view, are some of the highlights that occurred during the past 30 years of EDA.

EDA is a Highlight

The biggest highlight in EDA is the existence of a commercial EDA industry! Marching hand in hand with the fabless semiconductor revolution, commercial EDA made it possible for hundreds of companies to design semiconductors, as opposed to a small handful that could afford large internal CAD operations and fabs. With hundreds of semiconductor companies as opposed to a half-dozen, there’s a lot more creativity, and you get the level of sophistication and intelligence that you see in your smartphone, video camera, tablet, gaming console, and car today.

CAE + CAD = EDA. This is not just a terminology issue. By the mid-1980s it became clear that front-end design (CAE) and physical design (CAD) belonged together. The big CAE vendors got involved in IC and PCB CAD, and presented increasingly integrated solutions. People got tired of writing “CAE/CAD” and “EDA” was born.

The move from gate-level design to RTL. This move happened around 1990, and in my view this is EDA’s primary technology success story during the past 30 years. Moving up in abstraction made the design and verification of much larger chips possible. Going from gate-level schematics to a hardware description language (HDL) revolutionized logic design and verification. Which would you rather do – draw all the gates that form an adder, or write a few lines of code and let a synthesis tool find an adder in your chosen technology?

Two developments made this shift in design possible. One was the emergence of commercial RTL synthesis (or “logic synthesis”) tools from Synopsys and other companies, which happened around 1990. Another was the availability of Verilog, developed by Gateway Design Automation and purchased by Cadence in 1989, as a standard RTL HDL. Although most EDA vendors at the time were pushing VHDL, designers wanted Verilog and that’s what most still use (with SystemVerilog coming on strong in the verification space).

IC functional verification underwent huge changes in the late 1990s and early 2000s, largely due to new technology developed by Verisity, which was acquired by Cadence in 2005. Before Verisity, verification engineers were writing and running directed tests in an ad-hoc manner. Verisity introduced or improved technologies such as pseudo-random test generation, coverage metrics, reusable verification IP, and semi-automated verification planning. The Verisity “e” language became a widely used hardware verification language (HVL).

The biggest way that EDA has expanded its focus has been through semiconductor IP. Today Synopsys and Cadence are leading providers in this area. Thanks to the availability of design and verification IP, many SoC designs today reuse as much as 80% of previous content. This makes it much, much faster to design the remaining portion. While IP began with fairly simple elements, today commercially available IP can include whole subsystems along with the software that runs on them. With IP, EDA vendors are providing not only design tools but design content.

Finally, the EDA industry has done an amazing job of keeping up with SoC complexity and with advanced process nodes. Thanks to intense and early collaboration between foundries, IP, and EDA providers, tools and IP have been ready for process nodes going down to 10nm.

Where Does ESL Fit?

In some ways, electronic system level (ESL) design is both a lowlight and a highlight. It’s a lowlight because people have been talking about it for 30 years and the acceptance and adoption have come very slowly. ESL is a highlight because it’s finally starting to happen, and its impact on design and verification flows could be dramatic. Still, ESL is vaguely defined and can be used to describe almost anything that happens at a higher abstraction level than RTL.

High-level synthesis (HLS) is an ESL technology that is seeing increasing use in production environments. Current HLS tools are not restricted to datapaths, and they produce RTL code that gives better quality of results than hand-written RTL. Another ESL methodology that’s catching on is virtual prototyping, which lets software developers write software pre-silicon using SystemC models. Both HLS and virtual prototyping are made possible by the standardization of SystemC and transaction-level modeling (TLM). However, it’s still not easy to use the same SystemC code for HLS and virtual prototyping.

And Now, Some Lowlights

Every new industry has some twists and turns, and EDA is no exception. For example, the EDA industry in the 1980s and 1990s sparked a lot of lawsuits. At EE Times my colleagues and I wrote a number of articles about EDA legal disputes, mostly about intellectual property, trade secrets, or patent issues. Over the past decade, fortunately, there have been far fewer EDA lawsuits than we had before the turn of the century.

Another issue that was troublesome in the 1980s and 1990s was so-called “standards wars.” These would occur as EDA vendors picked one side or the other in a standards dispute. For example, power intent formats were a point of conflict in the early 2000s, but the Common Power Format (CPF) and the Unified Power Format (UPF) are on the road to convergence today with the IEEE 1801 effort. As mentioned previously, Verilog and VHDL were competing for adoption in the early 1990s. For the most part, Verilog won, showing that the designer community makes the final decision about which standards will be used.

How on earth did there get to be something like 30 DFM (design for manufacturability) companies 10-12 years ago? To my knowledge, none of these companies are around today. A few were acquired, but most simply faded away. A lot of investors lost money. Today, VCs and angel investors are funding very few EDA or IP startups. There are fewer EDA startups than there used to be, and that’s too bad, because that’s where a lot of the innovation comes from.

Here’s another current lowlight -- not enough bright engineering or computer science students are joining EDA companies. They’re going to Google, Apple, Facebook, and the like. EDA is perceived as a mature industry that is still technically very difficult. We need to bring some excitement back into EDA.

Where Is EDA Headed?

Now we come to what you might call “headlights” and look at what’s coming. My list includes:

• System Design Enablement. This term has been coined by Cadence to describe a focus on whole systems or end products including chips, packages, boards, embedded software, and mechanical components. There are far more systems companies than semiconductor companies, leaving a large untapped market that’s looking for solutions.
• New frontiers for EDA. At a 2015 Design Automation Conference speech, analyst Gary Smith suggested that EDA can move into markets such as embedded software, mechanical CAD, biomedical, optics, and more.
• Vertical markets. EDA has until now been “horizontal,” providing the same solution for all market segments. Going forward, markets like consumer, automotive, and industrial will have differing needs and will need optimized tools and IP.
• Internet of Things. This is a current buzzword, but the impact on EDA remains uncertain. Many IoT devices will be heavily analog, use mature process nodes, and be dirt cheap. Lip-Bu Tan, Cadence CEO, recently pointed out that the silicon percentage of IoT revenue will be small and that a lot of the profits will be on the service side.

Moving On

For the past six years I’ve been writing the Industry Insights blog at Cadence.com. All things change, and with this post comes a farewell – I am retiring in late June and will be pursuing a variety of interests other than EDA. I’ll be watching, though, to see what happens next in this small but vital industry. Thanks for reading!

Richard Goering

Have you ever manufactured a printed circuit board (PCB) without analyzing all the routed signal traces? Most designers will say “yes, all the time.” Trace widths and spacing are set by constraints,...

[[ Click on the title to access the full blog on the Cadence Community site. ]]

Cadence has a new white paper out on Computational Software . I've written on these topics in Breakfast Bytes, most recently in the posts: Computational Software System Analysis: Computational...

[[ Click on the title to access the full blog on the Cadence Community site. ]]

Have you ever manufactured a printed circuit board (PCB) without analyzing all the routed signal traces? Most designers will say “yes, all the time.” Trace widths and spacing are set by constraints, and many designers simply don’t h...(read more)

Hi,
I am new to the circuit design and troubleshooting. My project is to design a trans-impedance amplifier using Cadence that can amplify a signal coming from a photodiode. I started out with the regulated cascode configuration as shown in the circuit below. I look at the frequency response using AC simulation and it looks like a high pass (/net 5). The results doesn ot show any gain (transient response), or expected low-pass roll-off in the AC response.

First thing, I looked into the operating regions of the MOSFETs and adjusted the input dc voltage of the Vsin to 0.5 to make sure that the T0, T1 mosfets are in saturation(checked this with the print->dc operating points). Beyond this point, I am not sure on how to proceed and interpret the results to make changes. Any help would be greatly appreciated.

Thanks,

-Rakesh.

visit News18 Urdu for latest news, breaking news, news headlines and updates from Kheda on politics, sports, entertainment, cricket, crime and more.

visit News18 Urdu for latest news, breaking news, news headlines and updates from Medak on politics, sports, entertainment, cricket, crime and more.

visit News18 Urdu for latest news, breaking news, news headlines and updates from Ahmedabad on politics, sports, entertainment, cricket, crime and more.

This Metasploit module exploits a vulnerability on Microsoft Silverlight. The vulnerability exists on the Initialize() method from System.Windows.Browser.ScriptObject, which access memory in an unsafe manner. Since it is accessible for untrusted code (user controlled) it's possible to dereference arbitrary memory which easily leverages to arbitrary code execution. In order to bypass DEP/ASLR a second vulnerability is used, in the public WriteableBitmap class from System.Windows.dll. This Metasploit module has been tested successfully on IE6 - IE10, Windows XP SP3 / Windows 7 SP1 on both x32 and x64 architectures.

Utilities are — and have been for a long time — seeking better ways through which they can engage with their customers. According to Jeff Hamel, director of energy and housing partnerships at Google, the Nest smart thermostat, which is part of the hardware product line that Google provides, is a good example of a simple way that utilities are partnering with their customers.

La enseñanza bíblica en profundidad de John MacArthur lleva la verdad transformadora de la Palabra de Dios a millones de personas cada día.

La enseñanza bíblica en profundidad de John MacArthur lleva la verdad transformadora de la Palabra de Dios a millones de personas cada día.

Shinichiro Ueda reunites the cast of his hit comedy "One Cut of the Dead" for an innovative teleworking sequel

The 48 year old man, who understood to have a substance abuse problem, had been aggressive towards a doctor sent to treat him and died after force had to be used to subdue him.

Investments in climate-resilient infrastructure should be the centerpiece of the billions of dollars in economic stimulus being used to rebuild Asia’s economies.

Functional Safety Manual and FMEDA Access for dsPIC33C Family