Centrios is a cloud-based access control solution developed to radically simplify the needs of small and growing businesses.

During and since the two-week government shutdown, there has been a lot of analysis from across the political spectrum. The analysis includes a lot of finger pointing and blame assessment. At the end of the day, it was the abdication of leadership by all parties and no coherent strategy for how to end the stalemate that lengthen the shutdown.

With the recent creation of Plano Texas Dental Care's website, patients can now access valuable dental health care information 24/7.

The conservative design, introduced by major brands like Rolex, Casino, and others, continues to remain popular amongst wall clock buyers.

Many so-called luxury wall clocks and expensive handmade clocks use cheap mechanisms, according to Best Wall Clock.

Best Wall Clock has cut prices of their highly popular Rolex Submariner Wall Clock, an offer that's available for customers in the UK, Europe, and North America.

Gauging Biological Age and Disease Risk with a Proteomic Clock  Harvard Medical School

Proteomic aging clock predicts mortality and risk of common age-related diseases in diverse populations  Nature.com

ExakTime’s wireless field time clock has been awarded a patent for its unique method of tracking, storing, and sending employee time records from the field to the office automatically via a cellular communication network.

Want to know the kind of performance you will see at 1440p on an NVIDIA GeForce RTX 2060 SUPER FE when it is overclocked? Check out our gaming review.... [PCSTATS]

Timing characteristics of an enhanced synchronous equipment slave clock

The Kia Forum, outside of Los Angeles, was under pressure to have its existing rooftop logo removed and replaced. Contractor Centimark, using GAF products, got the job done on time. Learn how in this GAF case study.

Carraig Stanwyck, vice president and head of global cybersecurity and compliance at Avnet, explains why preparation for CMMC should start now.

The post The CMMC clock is ticking for the defense industrial base first appeared on Federal News Network.

Richard Weatherly has always had time on his side…

If the Broncos flushed Russell Wilson and beaucoup bucks after only 30 starts in a Denver uniform, how long does Sean Payton get to prove that his let-’em-eat-cake approach wins football games?

Mammalian circadian clocks are driven by transcription/translation feedback loops composed of positive transcriptional activators (BMAL1 and CLOCK) and negative repressors (CRYPTOCHROMEs (CRYs) and PERIODs (PERs)). CRYs, in complex with PERs, bind to the BMAL1/CLOCK complex and repress E-box–driven transcription of clock-associated genes. There are two individual CRYs, with CRY1 exhibiting higher affinity to the BMAL1/CLOCK complex than CRY2. It is known that this differential binding is regulated by a dynamic serine-rich loop adjacent to the secondary pocket of both CRYs, but the underlying features controlling loop dynamics are not known. Here we report that allosteric regulation of the serine-rich loop is mediated by Arg-293 of CRY1, identified as a rare CRY1 SNP in the Ensembl and 1000 Genomes databases. The p.Arg293His CRY1 variant caused a shortened circadian period in a Cry1−/−Cry2−/− double knockout mouse embryonic fibroblast cell line. Moreover, the variant displayed reduced repressor activity on BMAL1/CLOCK driven transcription, which is explained by reduced affinity to BMAL1/CLOCK in the absence of PER2 compared with CRY1. Molecular dynamics simulations revealed that the p.Arg293His CRY1 variant altered a communication pathway between Arg-293 and the serine loop by reducing its dynamicity. Collectively, this study provides direct evidence that allosterism in CRY1 is critical for the regulation of circadian rhythm.

The technology, enabled by thorium atoms, could keep time more accurately than atomic clocks and enable new discoveries about gravity, gravitational waves and dark matter

A measure to renew the Elementary and Secondary Education Act faces steep political hurdles.

anyone know what is "cell with Zero maximum clock transition time"  ?

not zero transition, not maximum transtion, it is zero maximum clock transition time.

it means X0 cell? (drive-strength)

can you explain? 

thanks :-)

Hi all,

I have been following the tutorial "Innovus Block Implementation with Stylus Common UI", version 23.1.

While I was doing the clock tree synthesis, the tutorial calls for a command

clock_opt_design

But my tool tells me this is a beta feature which needs to be enabled.

Warning: clock_opt_design requires beta feature innovusClockOptFlow enabled.

Can I ask how do I enable this beta feature?

My version of Innovus is v21.35-s114_1, is it because of the version incompatibility?

Many thanks

Hi all,

I'm trying to model the clock of a clock doubler. The doubler consists of a delay cell and an XOR gate, which generates a pulse on both the rising and falling edge of the input clock. I've created a simple module to evaluate this. In this case, DEL1 and XOR2 are standard library cells. There is a don_touch constraint on both library cells as well as on clk_d.

module top (
input wire clk,
output reg Q);

//Doubler
wire clk_d;
wire clk_2x;
DEL1 u_delay (.I(clk),.Z(clk_d));
XOR2 u_xor (.A1(clk),.A2(clk_d),.Z(clk_2x));

//FF for connecting the clock to some leaf:
always @(posedge clk_2x) Q<=~Q;

endmodule

My SDC looks like this:

create_clock [get_ports {clk}] -name clk_i -period 100
set_clock_latency -rise 0.1 [get_pins u_xor/Z]
set_clock_latency -fall 0.4 [get_pins u_xor/Z]
create_generated_clock -name clk_2x -edges {1 1 2 2 3} -source clk [get_pins u_xor/Z]

The generated clock is correctly generated but the pulse width is zero. I would be expecting that the pulse width is the difference between fall and rise latency but is not applied:

report_clocks:

report_clocks -generated:

clk_2x is disconnected from the FF after syn_generic. What can I do to model some minimum pulse width? Will innovus later on model this correctly with the delay of DEL1?

In a network containing multiple nodes, the need for synchronization between the various nodes is not just instrumental but also a complicated and highly complex process. This process becomes even more tricky if we synchronize the clocks between the Manager and the Peripheral. As we know, in a real-time network, some of the nodes would behave like Managers while some would be a Peripheral. If we must make the communication process smooth, then the local clocks of these nodes must be synchronized. 

The problem with this synchronization is that we have the clock running in the Manager as well. If we send the value of the Manager clock to the Peripheral, the synchronization doesn’t happen as we have a propagation delay of the messages, along with the propagation delay of the electronic circuits of Manager and the Peripheral.  

The cherry on the cake is that these electronic circuit propagation delays are not random and remain constant, so we can add a time offset to it to match the clock. To tackle this challenge, IEEE has come up with a protocol named “Precision Timing Protocol.” 

Operation of PTP: 

To synchronize the clocks, a Sync message is sent by the Manager to the Peripheral, which then timestamps the receiving time of the same. Following this, a ‘Follow up’ message is issued by the Manager stating the timestamp at which the Sync message was sent. 

The Peripheral then finds the difference between the two values and adds this to its current time. After this, the time difference between the Manager and the Peripheral narrows down to only the propagation delay of the messages.  

To overcome this, the Peripheral issues a ‘Delay Request’ to the Manager, and the Manager, in turn, issues a ‘Delay Response.’ Both these messages have the timestamp of when they were issued. The time at which they are received is then noted. Since two messages are sent, one from the Peripheral and the other from the Manager, there are two propagation delays. Then half of this value is our propagation delay. 

The Peripheral then adds this propagation delay to its clock, and hence the clock gets synchronized. 

Advantages of PTP: 

1. It provides accurate time stamping. 
2. It is a well-known clock synchronization protocol. 
3. It provides intensified security inside the premises. 
4. It provides the possibility of setting coordinated actions and synchronized communication. 

There are various versions of PTP that have been developed over time, namely PTPv1, PTPv2, PTPv2_1, and the latest PTP-AS. 

Cadence Verification IP for Ethernet is available to support the newer version of PTP, allowing simulation of the device for efficient IP, SoC, and system-level design verification. Semiconductor companies can start using it to fully verify their controller design and achieve functional verification closure on it within no time. 

DDR5 is the latest generation of PCDDR memory that is used in a wide range of application like data centers, Laptops and personal computers, autonomous driving systems, servers, cloud computing, and gaming are now increasingly being used for AI applications with advances in memory bandwidth and density to allow DDR5 DIMMs (Dual Inline Memory Modules) to support densities higher then 256 GB per DIMM card. The highest speed DDR5 SDRAM devices can support data rates of up to 8800 MTps.

DDR5 SO-DIMMs and UDIMMs

One of the most recognized uses of PCDDR is with client devices like laptops and personal computers. These client devices mostly use two types of DDR5 DIMMs called SO-DIMM (Small Outline Dual Inline Memory Module) and UDIMM (Unbuffered Dual Inline Memory Module).

These types of DIMMs have no signal regeneration or buffering (which, for example, the Registering Clock Driver or the RCD does for clocks/command/control signals for a registered DIMMs). A typical 2-Rank UDIMM with x8 DDR5 SDRAM components has 8 or 10 components per rank depending on the system ECC (Error Correction Code) memory being part of the DIMM.

Why DDR5 Clock Buffer and CUDIMM?

Clocks are one of the most important signals for synchronous devices, and DDR5 SDRAMs are no exception. The host is responsible for the fanout to all the DRAM input ports, such as clocks for UDIMMs. Driving of all these DRAM clocks can put quite a bit of load on the host output drivers, thus affecting the signal quality, which can result in unexpected memory errors. This issue gets amplified when operating at the higher clock and data rates where the clock signals transition from one logic value to the next over a very short time. To solve these signal integrity issues with DRAM clocks, JEDEC has come up with a new type of DDR5 DIMM component that is called DDR5 clock buffer. Clock buffers can be used for both DDR5 SO-DIMMs and DDR5 UDIMMs. DDR5 UDIMMs that include a clock buffer component as part of the DIMM card are called DDR5 CUDIMMs (Clock Buffered UDIMMs).

DDR5 Clock Buffer Overview

DDR5 Clock Buffer is a simple logic device that takes in two sets of input clock pins and drives two sets of clock pins as output per channel. The clock buffer device can operate in three types of clock modes: -

• PLL bypass mode: In this mode, the clock buffer just passes on the input clocks to output without any kind of signal buffering. The PLL bypass mode enabled CUDIMM devices behave like traditional UDIMMs without any buffering of the clocks. This is why it’s also referred to as legacy mode. Recommended CUDIMM operating speeds in PLL bypass mode are typically limited to 3000 MHz.

• Single PLL mode: In the single PLL Mode, the clock buffer device will use a Phase Lock Loop (PLL) for the regeneration of the incoming host clock to create a better-quality clock that is sent to the DRAMs. However, since there is only one PLL that is used in this mode, both sub channel output clocks will be driven based on only one set of input clocks with the other set of input clocks remaining unused.

• Dual PLL mode: In this mode, the clock buffer will use two PLLs to independently generate each sub channel output clock based on each set of incoming host clocks. The second set of PLL can be turned on or off on the fly if needed to save power.

Beyond the clock modes, clock buffers provide additional flexibility to the system designers with register-controlled additional signal delays, optional output clock enable/disable per bit feature, drive strength and termination choices, etc. All DDR5 clock buffer device control word registers are accessible via DDR5 DIMM sideband.

Cadence VIPs offers a compressive memory subsystem solution that includes memory models for DDR5 SDRAM, DDR5 RCD, DDR5 DB, DDR5 clock buffer, all types of DDR5 DIMMs, including the DDR5 CUDIMMs, DFI Memory Controller/PHY VIPs, and a system VIP compliant to JEDEC specifications defined for each of those devices along with latest DFI Specification.

More information on Cadence DDR5 DIMM VIP is available at the Cadence VIP Memory Models website.

In the era of Artificial Intelligence, front-end designers need a magical key to empower them with technology that enables fully optimized RTL for implementation handoff and provides RTL designers with capabilities to accurately assist in the implementation convergence process.

The magic lies with Cadence Joules RTL Design Studio, an expert system that leverages generative AI for RTL design exploration, triages possible causes of violations, and additional insights that empower designers to understand how to address issues in their RTL, leading to smarter and more efficient chip design.

This unlocks the immense debugging and design analysis capabilities from a single, unified cockpit, enabling fully optimized RTL design prior to implementation handoff for the front-end designers and addresses all aspects of physical design by adding visibility into power, performance, area, and congestion (PPAC)

One critical component is the clock tree, which distributes the clock signal to all sequential elements, such as flip-flops and latches. Designers need the right techniques in the beginning stage to optimize the clock tree structure, ensuring that their designs meet the required timing specifications, reduce power consumption, maintain signal integrity, and increase reliability.

 This incredible feature is part of the Joules RTL Design Studio.

How do you efficiently explore the clock tree structure to optimize the results using Joules RTL Design Studio?

Joules Studio allows viewing a simplified version of the clock structure. This feature is primarily designed to help display clock frequency scaling through clock dividers. You can customize colors, symbols, and design elements using an input file. Additionally, you can cross-probe the custom clock tree structure to other widgets and the main schematic view in Joules Studio.

Moreover, with the clock tree preference features of the ideal clock tree wizard in Joules Studio GUI, you can highlight clock path, generate clocks and master clock, set case analysis, fold and unfold instances, undo and redo, set sense and disable timing, color preference, etc.

You can binge on these features through the channel videos posted on the support portal, which covers the Joules RTL Design Studio GUI Clock Tree Structure and Features of Ideal Clock Tree Wizard.

You can refer to the videos on Cadence Online Support (Cadence login required).

​Video Links:
Viewing Custom Clock Tree Structure in Joules RTL Design Studio (Video) 

Exploring Clock Tree Preference Widget of Ideal Clock Tree Wizard in Joules RTL Design Studio (Video) 

Want to learn more?

Explore the one-stop solution Joules RTL Design Studio Product Page on Cadence Online Support (Cadence login required).

Related Resources 

Related Training Bytes:

Understanding Prototype Design Flow in Joules RTL Design Studio (Video)

Running Prototype Implementation Flow in Joules RTL Design Studio (Video)

Understanding Analyze Timing By Hierarchy In Joules RTL Design Studio (Video)

Related Courses:

• Joules Power Calculator

Want to Enroll in this Course?

We organize this training for you as a "Blended" or "Live" training. Please reach out to Cadence Training for further information.

Please don't forget to obtain your Digital Badge after completing the training.

Related Blogs:

Let's Discover the Secret to Enhance Design's PPAC in a Single Cockpit! - Digital Design - Cadence Blogs - Cadence Community

Joules RTL Design Studio: Accelerating Fully Optimized RTL - Digital Design - Cadence Blogs - Cadence Community

Let's Replay the Process of Power Estimation with the Power of 'x'! - Digital Design - Cadence Blogs - Cadence Community

Is Design Power Estimation Lowering Your Power? Delegate and Relax! - Digital Design - Cadence Blogs - Cadence Community

In most vertebrates, a pattern of chemical marks on the genome is a reliable indicator of age, but in axolotls this clock seems to stop after the first four years of life

Forget atomic clocks. Nuclear clocks, which only drop a second every 300 billion years, can test whether nature's fundamental constants are constant after all

A set of mathematical equations can help turn apparently random observations into a clock – and then measure its accuracy

Forget atomic clocks. Nuclear clocks, which only drop a second every 300 billion years, can test whether nature's fundamental constants are constant after all

Modern life disrupts the circadian rhythms controlling our biology – increasing our risk of developing conditions ranging from diabetes to dementia. Lynne Peeples's new book The Inner Clock explores and offers solutions

Is Fortnite old enough to elicit nostalgia? Last year’s trial run of bringing back the battle royale game’s original map, weapons and early seasons would suggest so — at least for folks of a certain age. That test led to record-breaking player counts, topping 44.7 million in October 2023. Epic Games said on Tuesday that the OG Fortnite rewind is coming back again, and this time, it’s for good.

OG Fortnite will let you play the original map, along with the loot and seasons as they were in 2017. In addition to the nostalgia factor, many players appreciate that era’s simpler gameplay mechanics, map designs, weapons and items. It was also before expansion updates that added new game modes (it was Battle Royale only) and vehicles like cars, boats and helicopters.

Old-school Fortnite fans have less than a month to wait. The OG version returns to the game on December 6.

Blizzard must have seen something it liked in the 2023 trial. It borrowed a page from Epic and brought back Overwatch in its original form for a three-week event starting today.

Everyday Health Inc. Introduces the What to Expect Pregnancy Clock Apple Watch� app.

Probability of operating an alarm clock

Daylight saving time adjustments, moving clocks forward in spring and back in autumn, significantly impact sleep duration but only for a short period,

Public sector banks (PSBs) showed strong performance in the first half of current fiscal (FY25) with 11 per cent annual growth.

Tiger Woods cast serious doubt on his competitive golf future in his first press conference since a life-threatening February car crash, saying that his ability to compete will never be the same after the devastating leg injuries. Photo: Doug Ferguson/Associated Press

Every one of Rick Stanley's clocks is an inventive journey. He makes clocks using everything from bottles to bicycles; each one of them completely unique and accurate. "Even when I'm on vacation I think of different clocks to make," says Rick, talking about how he always has clocks on the brain. Rick gets inspiration from nearly everything, fueling his whimsical timekeeping inventions. Director: Charlie Jordan Director of Photography: Chad Jenkins Editor: Richard Trammell Expert: Rick Stanley Senior Producer: Efrat Kashai Creative Producer: Wendi Jonassen Line Producer: Joseph Buscemi Associate Producer: Brandon White Production Manager: Eric Martinez Production Coordinator: Fernando Davila Camera Operator: Pete Kuhn Audio: Michael Competielle Production Assistant: Bill Storms Post Production Supervisor: Alexa Deutsch Post Production Coordinator: Ian Bryant Supervising Editor: Doug Larsen Assistant Editor: Andy Morell Special thanks to: Elizabeth Gorbey Willow Springs Photography http://willowspringsphotography.com

The operating and net profit for H1 FY25 was Rs 1,50,023 crore (14.4 per cent YoY growth) and Rs 85,520 crore (25.6 per cent YoY growth). 

While the initial projection for Phase I was 1 to 1.5 million cargo units per annum, the seaport has already handled 1.08 lakh cargo units – just three months into the trial run period

This next generation smart clock is a simple device with a colour touchscreen

The BJP MLC said that while seeking votes for him, she felt like she was receiving a "send-off party" and was being freed of a responsibility.

Coal Secretary Anil Jain said FY20 coal production was lower than the target of 660 million tonnes because of flooding of a key coal mine.

In his third update from Serbian/Croatian border, Volker Sachse says that in spite of increasingly difficulties, he can see God’s peace touch local people.

Feb. 29 approaches, with advocates pushing hard for long-shot changes

It has become the accepted wisdom that meeting the global climate challenge will require zero net greenhouse gas (GHG) emissions by the end of this century. Read the full op-ed by Gabriela Ramos, OECD Special Advisor to the OECD Secretary-General.