Are they basically the same thing? I am trying to get as much experience with Allegro since a lot of jobs I am looking at right now are asking for Cadence Allegro experience (I wish they asked for Altium experience...). I currently have access to PCB Editor, but I don't want to commit to learning Editor if Allegro is completely different. Also walmart one, are the Cadence Allegro courses worth it? I won't be paying for it and if it's worth it, I figure I might as well use the opportunity to say I know how to use two complex CAD tools.

Hello, I am using Encounter 8.1. My mouse is working fine, but my keyboard is not working well in Encounter. I can type in some boxes, but in many boxes I cannot type. The binding key is also not responding. How do I fix this issue? Thanks.

RF Enthusiasts, Come connect with Cadence RF experts and discover the latest advances in Cadence RF technologies, including Spectre RF at the IEEE International Microwave Symposium (IMS) 2014. This year, IMS will be held in Tampa, Florida. Cadence...(read more)

Hello Spectre RF Users, Next week is my all time favorite technical conference - the International Microwave Symposium IMS2016 , May 22-27 in San Francisco, CA at the Moscone Center. If you're at the conference, please stop by the Cadence booth and...(read more)

The Cadence® Connections® Verification Program brings together a worldwide network of services, training, and IP development experts that support Cadence verification solutions. The program members help customer accelerate the adoption of new...(read more)

There’s nothing like the heat of a DAC demo to stress new technology and the engineers behind it! Such was the case at DAC 2018 at the new locale of Moscone Center West, San Francisco. Cadence and AMIQ were two of several vendors who announced ...(read more)

Cadence continues to be a leader in SoC verification and has expanded our industry investment in Accellera portable stimulus language standardization. Some customers have expressed reservations that portable stimulus requires the effort of learn...(read more)

I'm trying to generate IBIS models for the parts that I'm designing.  I'm designing using CADENCE Virtuoso.  

I'm wondering if there is a tutorial for generating IBIS models in CADENCE Virtuoso.   Please pardon me if my question is broad.      

Complexity is driving the urgency for advanced artificial intelligence systems more than ever—and that means someone has to supply the tools to create those systems. Cadence is up to the task: we’ve been expanding our AI offerings. If you haven’t already seen what Cadence can do for your AI needs, or if you’re not quite up-to-date on this whole AI boom, let this presentation given by K.T. Moore at the Cadence Theater at DAC bring you up to speed.

The technology behind AI isn’t as new as you’d think—the principles that govern how AI learns have been in development since 1959, when Arthur Samuel defined the concept of “machine learning.” At the time, there was nothing even resembling the necessary compute power to put Samuel’s concepts into practice—but now we can. AI designs are huge, and they’re massively parallel—simulating them on older computers and simulators would have taken ages; never mind how long it would take to do some by-hand measure like they had to do in the '60s.

But with advancements in server technology and the parallelization technology in products like Xcelium Parallel Logic Simulator and JasperGold smart technology, plus hardware-based engines like the Palladium and Protium platforms, verifying AI designs is not only possible—it’s easy.  But, read on, its not just about simulation technology.

AI tech is flooding the industry. It’s applicable to almost every vertical—cloud computing can use AI to intelligently manage a user’s required resources, consumer electronics are using it to tailor a user experience based on a whole host of collected data, automotive companies want to use AI to drive cars, healthcare to assist in diagnoses given a set of symptoms and a database of other, similar patients—and that’s saying nothing of the multitude of industrial applications. AI is also useful in the creation of developers’ tools themselves. Part of what’s causing the semiconductor industry boom is just this—an exploding interest in AI chips. And with 5G technology imminent, and with the looming billion-gate plus sizes of the SoCs that implement 5G, AI-assisted developers' tools might need to become the norm, not an outlier.

So: in all of this, where is Cadence?

Cadence is focusing its efforts on two areas, dubbed “machine learning inside” and “machine learning outside.” ML inside in the digital design flow refers to improving PPA, faster engines, and better testing and diagnostics. None of this physically affects how you use a tool, but it makes using that tool a much better experience. ML outside talks about the design flow in general, working toward an automated design flow, as well as productivity improvements across the flow. These things do change how you use a tool, but don’t worry, it’s all for the better.

Additionally, Cadence is working to improve design enablement; that is, hardware and software co-design. Smart Genus and Innovus solutions make designing your SoC easier than ever—using the full flow can result in up to a 21% PPA gain.

If you’re looking specifically for IP to enable AI on your SoC, the Tensilica DNA 100 processor has you covered, too. It’s great for companies designing edge or AI chips, offers great compression rates and efficient power usage, and has 4.7X the performance of other AI SoC IP on similar array sizes.

Cadence has you covered no matter where you’re going in this new world of AI systems—with our AI-enabled tools, IP,  and our strong partner ecosystem, you can be at ease knowing you’ll be supported no matter how complex your needs are.

DAC is right around the corner! On the demo floor at Cadence® Booth #2214, we will demonstrate how to use the Cadence mixed-signal and low-power solution to design, verify, and implement a microcontroller-based mixed-signal design. The demo design architecture is very similar to practical designs of many applications like power management ICs, automotive controllers, and the Internet of Things (IoT). Cadene tools demonstrated in this design include Virtuoso® Schematic Editor, Virtuoso Analog Design Environment, Virtuoso AMS Designer, Virtuoso Schematic Model Generator, Virtuoso Power Intent Assistant, Incisive® Enterprise Simulator with DMS option, Virtuoso Digital Implementation, Virtuoso Layout Suite, Encounter® RTL Compiler, Encounter Test, and Conformal Low Power. An extended version of this demo will also be shown at the ARM® Connected Community Pavilion Booth #921.

For additional highlights on Cadence mixed-signal and low-power solutions, stop by our booth for:

• The popular book, Mixed-signal Methodology Guide, which will be on sale during DAC week!
• A sneak preview of the eBook version of the Mixed-signal Methodology Guide
• Customer presentations at the Cadence DAC Theater
  • 9am, Tuesday, June 4  ARM  Low-Power Verification of A15 Hard Macro Using CLP 
  • 10:30am, Tuesday, June 4  Silicon Labs  Power Mode Verification in Mixed-Signal Chip
  • 12:00pm, Tuesday, June 4  IBM  An Interoperable Flow with Unified OA and QRC Technology Files
  • 9am, Wednesday, June 5  Marvell  Low-Power Verification Using CLP
  • 4pm, Wednesday, June 5  Texas Instruments  An Inter-Operable Flow with Unified OA and QRC Technology Files
• Partner presentations at the Cadence DAC Theater
  • 10am, Monday, June 3  X-Fab  Rapid Adoption of Advanced Cadence Design Flows Using X-FAB's AMS Reference Kit
  • 3:30pm, Monday, June 3  TSMC TSMC Custom Reference Flow for 20nm -  Cadence Track
  • 9:30am,Tuesday, June 4  TowerJazz   Substrate Noise Isolation Extraction/Model Using Cadence Analog Flow
  • 12:30pm, Wednesday, June 5  GLOBALFOUNDRIES  20nm/14nm Analog/Mixed-signal Flow
  • 2:30pm, Wednesday, June 5  ARM  Cortex®-M0 and Cortex-M0+: Tiny, Easy, and Energy-efficient Processors for Mixed-signal Applications
• Technology sessions at suites
  • 10am, Monday, June 3    Low-power Verification of Mixed-signal Designs
  • 2pm, Monday, June 3      Advanced Implementation Techniques for Mixed-signal Designs
  • 2pm, Monday, June 3      LP Simulation: Are You Really Done?
  • 4pm, Monday, June 3      Power Format Update: Latest on CPF and IEEE 1801  
  • 11am, Wednesday, June 5   Mixed-signal Verification
  • 11am, Wednesday, June 5   LP Simulation: Are You Really Done?
  • 4pm, Wednesday, June 5   Successful RTL-to-GDSII Low-Power Design (FULL)
  • 5pm, Wednesday, June 5   Custom/AMS Design at Advanced Nodes

We will also have three presentations at the Si2 booth (#1427):

• 10:30am, Monday, June 3   An Interoperable Implementation Solution for Mixed-signal Design
• 11:30am, Tuesday, June 4   Low-power Verification for Mixed-signal Designs Using CPF
• 10:30am, Wednesday, June 5   System-level Low-power Verification Using Palladium

We have a great program at DAC. Click the link for complete Cadence DAC Theater and Technology Sessions. Look forward to seeing you at DAC!     

Hello, i saw that MAESTRO is a plotting addon is it a part of ADE EXPLORER?

i cant see the relation between the two.i started to read manual and regarding MAESTRO i only see code.

is there some simple examples?
Thanks.

Hello, i have a realy mistick thing going with copying libraries in cadence virtuoso,

When i copy straight forwart the whole library it gives me a warning that accsess was denied,but when i go into the library and copy it as a single file, then it goes fine.

another problem is it doesnt show in the massage console  ALL the files which could not be copied.(which is the much bigger problem,becuase i would have to pass threw all the subdirectories to verify if all files are there)

Is there a way to see which files wasnt able to be copied?

Thanks. 

Hi,
I am new to the circuit design and troubleshooting. My project is to design a trans-impedance amplifier using Cadence that can amplify a signal coming from a photodiode. I started out with the regulated cascode configuration as shown in the circuit below. I look at the frequency response using AC simulation and it looks like a high pass (/net 5). The results doesn ot show any gain (transient response), or expected low-pass roll-off in the AC response.

First thing, I looked into the operating regions of the MOSFETs and adjusted the input dc voltage of the Vsin to 0.5 to make sure that the T0, T1 mosfets are in saturation(checked this with the print->dc operating points). Beyond this point, I am not sure on how to proceed and interpret the results to make changes. Any help would be greatly appreciated.

Thanks,

-Rakesh.

Hello , i am trying to extract netlist from a circuit  in assembler

I have found the manual shown bellow , however there is no such option in tools in assembler.

how do i view the NETLIST of this circuit?

Thanks.

ASSEMBLER VIEW menu

Hello, I have a problem with a certain type of transistor,my hyrarchy has a lot components an sub components and visually inspecting them is very hard.

is there a way like in other cadence layout viewer tools , to enter the name of the component or a NET somewhere and it will focus on it visualy or give the hyrarchy path to it?

Thanks.

Hello

The document I referenced is https://filebox.ece.vt.edu/~symort/rfworkshop/Mixer_workshop_instruction.pdf. (This is cadence workshop document)

While following the pxf simulation in the above article, the results are different and I have a question.

My result picture is shown below.

<my result error>

<document result>

<my direct plot>

<document direct plot>

The difference with the documentation is that in the direct plot screen after the pxf simulation,

1.output harmonics-> input sideband

2.Frequency axis: out-> frequency axis: absin

3.The results for port0 (RF port) are also different (see photo below).

4.The frequency values in the box are different.

My screen shows 5G, 10G, 1K ~ 10M, but the document is the same as 1K ~ 10M.

Ask for a solution. Thank you.

Hi, all

Recently, I meet the simulation error as the picture shows when I simulate my circuit with transient.  how can I solve this problem?

thank you~

Hello, i am trying to produce a gain circles on a simple transistor as shown bellow.

i have defined the range from 1 til 30 dB and i dont get any circle just dots in infinity?

Where did i go wrong?
Thanks.

Hello, i have built a matching network of 13dB gain and  NF as shown bellow step by step.(including all the plots and matlab )

its just not working at all,i am doing it exacly by the thoery

taking a point inside the circle-> converting its gamma to Z_source->converting gamma_s into gamma_L with the formulla bellow as shown in the matlab->converting the gamma_L into Z_L-> building the matching network for conjugate of Z_L and Z_c.Its just not working.

where did i got  wrong?

Thanks.

gamma_s=75.8966*exp(deg2rad(280.88)*i);
z_s=gamma2z(gamma_s,50);
s11=0.99875-0.03202*i
s12=721.33*10^(-6)+8.622*10^(-3)*i
s21=-188.37*10^(-3)+30.611*10^(-3)*i
s22=875.51*10^(-3)-100.72*10^(-3)*i
gamma_L=conj((s22+(s12*s21*gamma_s)/(1-s11*gamma_s)))
z_L=gamma2z(gamma_L,50)

Hello, There is a manual in matlab of matching LNA  shown in the link bellow.

In it as shown in the plot bellow they mention input and output circle plots.

Is there such option of input and output circle in cadence virtuoso?

https://www.mathworks.com/help/rf/examples/designing-matching-networks-part-1-networks-with-an-lna-and-lumped-elements.html

Hello folks,

Greetings.

One of my customer claims that he is using Cadence IES version 18.09.011 with Vivado 2019.2. The version of IES that we officially support with Vivado 2019.2 is 15.20.073. Though the tool is forward compatible, I am not sure what are the versions of IES that are released after 15.20.073. Could you please give me a list of the versions of Cadence IES released after 15.20.073 and which is the latest version as of now ?

Best regards,

Chinmay

Hi all,

Is there any tutorial which explains the process of plotting the ISF function for a certain oscillator ?

Thank you.

Hello,

I am trying to import multiple verilog modules defined in a single file with "`define" directive in the top using Verilog In. The code below is an example of what my file contains.

When I use the settings below to import the modules into a library, it imports it correctly but completely ignores all `define directive; hence when I simulate using any of the modules below the simulator errors out requesting these variables.

My question: Is there a way to make Verilog In consider `define directives in every module cell created? 

Code to be imported by Cadence Verilog In:

--------------------------------------------------------

`timescale 1ns/1ps
`define PROP_DELAY 1.1
`define INVALID_DELAY 1.3

`define PERIOD 1.1
`define WIDTH 1.6
`define SETUP_TIME 2.0
`define HOLD_TIME 0.5
`define RECOVERY_TIME 3.0
`define REMOVAL_TIME 0.5
`define WIDTH_THD 0.0

`celldefine
module MY_FF (QN, VDD, VSS, A, B, CK);

inout VDD, VSS;
output QN;
input A, B, CK;
reg NOTIFIER;
supply1 xSN,xRN;
buf IC (clk, CK);
and IA (n1, A, B);
udp_dff_PWR I0 (n0, n1, clk, xRN, xSN, VDD, VSS, NOTIFIER);
not I2 (QN, n0);

wire ENABLE_B ;
wire ENABLE_A ;
assign ENABLE_B = (B) ? 1'b1:1'b0;
assign ENABLE_A = (A) ? 1'b1:1'b0;

specify
$setuphold(posedge CK &&& (ENABLE_B == 1'b1), posedge A,  `SETUP_TIME, `HOLD_TIME, NOTIFIER);
$setuphold(posedge CK &&& (ENABLE_B == 1'b1), negedge A, `SETUP_TIME, `HOLD_TIME, NOTIFIER);
$setuphold(posedge CK &&& (ENABLE_A == 1'b1), posedge B, `SETUP_TIME, `HOLD_TIME, NOTIFIER);
$setuphold(posedge CK &&& (ENABLE_A == 1'b1), negedge B, `SETUP_TIME, `HOLD_TIME, NOTIFIER);
$width(posedge CK,1.0,0.0,NOTIFIER);
$width(negedge CK,1.0,0.0,NOTIFIER);
if (A==1'b0 && B==1'b0)
(posedge CK => (QN:1'bx)) = (1.0, 1.0);
if (A==1'b1 && B==1'b0)
(posedge CK => (QN:1'bx)) = (1.0, 1.0);
if (B==1'b1)
(posedge CK => (QN:1'bx)) = (1.0,1.0);

endspecify

endmodule // MY_FF
`endcelldefine

`timescale 1ns/1ps
`celldefine
module MY_FF2 (QN, VDD, VSS, A, B, CK);

inout VDD, VSS;
output QN;
input A, B, CK;
reg NOTIFIER;
supply1 xSN,xRN;
buf IC (clk, CK);
and IA (n1, A, B);
udp_dff_PWR I0 (n0, n1, clk, xRN, xSN, VDD, VSS, NOTIFIER);
not I2 (QN, n0);

wire ENABLE_B ;
wire ENABLE_A ;
assign ENABLE_B = (B) ? 1'b1:1'b0;
assign ENABLE_A = (A) ? 1'b1:1'b0;

specify
$setuphold(posedge CK &&& (ENABLE_B == 1'b1), posedge A,  `SETUP_TIME, `HOLD_TIME, NOTIFIER);
$setuphold(posedge CK &&& (ENABLE_B == 1'b1), negedge A,  `SETUP_TIME, `HOLD_TIME, NOTIFIER);
$setuphold(posedge CK &&& (ENABLE_A == 1'b1), posedge B,  `SETUP_TIME, `HOLD_TIME, NOTIFIER);
$setuphold(posedge CK &&& (ENABLE_A == 1'b1), negedge B,  `SETUP_TIME, `HOLD_TIME, NOTIFIER);
$width(posedge CK,1.0,0.0,NOTIFIER);
$width(negedge CK,1.0,0.0,NOTIFIER);
if (A==1'b0 && B==1'b0)
(posedge CK => (QN:1'bx)) = (1.0, 1.0);
if (A==1'b1 && B==1'b0)
(posedge CK => (QN:1'bx)) = (1.0, 1.0);
if (B==1'b1)
(posedge CK => (QN:1'bx)) = (1.0,1.0);

endspecify

endmodule // MY_FF2
`endcelldefine

--------------------------------------------------------

I am using the following Cadence versions:

MMSIM Version: 13.1.1.660.isr18

Virtuoso Version: IC6.1.8-64b.500.1

irun Version: 14.10-s039

Spectre Version: 18.1.0.421.isr9

Hi,

This question is related to the constraint measurement criteria used by the Liberate inside view. I am trying to characterize a specific D flip-flop for low voltage operation (0.6V) using Cadence Liberate (V16). 

When the "define_arcs" are not explicitly specified in the settings for the circuit (but the input/outputs are indeed correct in define_cell), the inside view seems to probe an internal node (i.e. master latch output)  for constraint measurements instead of the Q output of the flip flop. So to force the tool to probe Q output I added following coder in constraint arcs :

# constraint arcs from CK => D
define_arc
-type hold
-vector {RRx}
-related_pin CP
-pin D
-probe Q
DFFXXX

define_arc
-type hold
-vector {RFx}
-related_pin CP
-pin D
-probe Q
DFFXXX

define_arc
-type setup
-vector {RRx}
-related_pin CP
-pin D
-probe Q
DFFXXX

define_arc
-type setup
-vector {RFx}
-related_pin CP
-pin D
-probe Q
DFFXXX

with -probe Q liberate identifies Q as the output, but uses Glitch-Peak criteria instead of delay degradation method. So what could be the exact reason for this unintended behavior ? In my external (spectre) spice simulation, the Flip-Flop works well and it does not show any issues in the output delay degradation when the input sweeps.

Thanks

Anuradha

Cadence Liberate Trio Characterization Suite, ARM-based Graviton Processors, and Amazon Web Services (AWS) Cloud have joined forces to cater to the High-Performance Computing, Machine Learning/Artificial Intelligence, and Big Data Analytics sectors. (read more)

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