The science major in the Penn State Eberly College of Science has been renamed integrative science as part of a modern refresh to reflect its interdisciplinary nature.

A rejection from an au pair organisation in the U.S. made it possible for Carolina from Argentina to grow in relationship with Jesus.

One man's encounter with an OM team leads to his son’s discovery of his talent as a tailor and desire to know God.

The journey of a young Albanian girl from the Roma and Gypsy community who went from being a troubled teenager to excitedly following Jesus!

As black-white achievement gaps widen in schools, so, too, do disparities in discipline rates between black and white students, according to a study published Wednesday of 2,000 schools.

God uses OMers to show His love to local believers, who then spread that love to their own communities.

Former Australia skipper Ricky Ponting and his longtime teammate Justin Langer could potentially miss out commentating on the opening Test against India at Perth

Attorney General Kathy Jennings announced Tuesday that a Pennsylvania man has been formally charged with 41 felonies, including the murders of two people and the attempted murder, assaults, and/or robbery of four other victims, among other offenses. Prosecutors allege that Keith Gibson, 39, went on a brutal crime spree in Delaware, killing two victims and […]

Jennings successfully appealed from original deal, more than doubling Delaware’s recovery with up to $25 million extra Institutions may remove Sackler name from buildings, scholarships; Sacklers to be banned from opioid business and Purdue to dissolve Attorney General Jennings announced today a tentative settlement worth as much as $6 billion with Purdue Pharma and the Sackler family […]

Delaware Attorney General Kathy Jennings today announced a multistate settlement in principle with opioid manufacturer Amneal Pharmaceuticals (Amneal) for its role in fueling the nationwide epidemic of opioid addictions and overdoses. Amneal produces several generic opioid products and was one of the largest manufacturers of opioids from 2006 to 2019, selling nearly nine billion pills. […]

Attorney General Kathy Jennings today announced a $10.25 million 50-jurisdiction settlement with AT&T Mobility, LLC, Cricket Wireless, LLC, T-Mobile USA, Inc., Cellco Partnership, d/b/a Verizon Wireless, and TracFone Wireless, Inc. (collectively, the “Wireless Carriers”), which resolves the state attorneys general investigations into the Wireless Carriers’ deceptive and misleading advertising practices.   “Today’s settlement further demonstrates […]

The Pinarayi Vijayan government in Kerala has suspended two officers of the Indian Administrative Service (IAS) on disciplinary grounds. K Gopalakrishnan, director of Industries and Commerce, faced the action over a religion-based WhatsApp group for

In the rapidly evolving landscape of automotive electronics, traditional monolithic design approaches are giving way to something more flexible and powerful—chiplets. These modular microchips, which are themselves parts of a whole silicon system, offer unparalleled potential for improving system performance, reducing manufacturing costs, and accelerating time-to-market in the automotive sector. However, the transition to working with chiplets in automotive electronics is not without its challenges.

Designers must now grapple with a new set of considerations, such as die-to-die interconnect standards, complex processes, and the integration of diverse IPs. Advanced toolsets and standardized design approaches are required to meet these challenges head-on and elevate the potential of chiplets in automotive innovation. In the following discourse, we will explore in detail the significance of chiplets in the context of automotive electronics, the obstacles designers face when working with this paradigm, and how Cadence comprehensive suite of IPs, tools, and flows is pioneering solutions to streamline the chiplet design process.

Unveiling Chiplets in Automotive Electronics

For automotive electronics, chiplets offer a methodology to modularize complex functionalities, integrate different chiplets into a package, and significantly enhance scalability and manufacturability. By breaking down semiconductor designs into a collection of chiplets, each fulfilling specific functions, automotive manufacturers can mix and match chiplets to rapidly prototype new designs, update existing ones, and specialize for the myriad of use cases found in vehicles today.

The increasing significance of chiplets in automotive electronics comes as a response to several industry-impacting phenomena. The most obvious among these is the physical restriction of Moore's Law, as large die sizes lead to poor yields and escalating production costs. Chiplets with localized process specialization can offer superior functionality at a more digestible cost, maintaining a growth trajectory where monolithic designs cannot. Furthermore, chiplets support the assembly of disparate technologies onto a single subsystem, providing a comprehensive yet adaptive solution to the diverse demands present in modern vehicles, such as central computing units, advanced driver-assistance systems (ADAS), infotainment units, and in-vehicle networks. This chiplet-based approach to functional integration in automotive electronics necessitates intricate design, optimization, and validation strategies across multiple domains.

The Complexity Within Chiplets

Yet, with the promise of chiplets comes a series of intricate design challenges. Chiplets necessitate working across multiple substrates and technologies, rendering the once-familiar 2-dimensional design space into the complex reality of multi-layered, sometimes even three-dimensional domains. The intricacies embedded within this design modality mandate devoting considerable attention to partitioning trade-offs, signal integrity across multiple substrates, thermal behavior of stacked dies, and the emergence of new assembly design kits to complement process design kits (PDKs).

To effectively address these complexities, designers must wield sophisticated tools that facilitate co-design, co-analysis, and the creation of a robust virtual platform for architectural exploration. Standardizations like the Universal Chip Interconnect Express (UCIe) have been influential, providing a die-to-die interconnect foundation for chiplets that is both standardized and automotive-ready. The availability of UCIe PHY and controller IP from Cadence and other leading developers further eases the integration of chiplets in automotive designs.

The Role of Foundries and Packaging in Chiplets

Foundries have also pivoted their services to become a vital part of the chiplet process, providing specialized design kits that cater to the unique requirements of chiplets. In tandem, packaging has morphed from being a mere logistical afterthought to a value-added aspect of chiplets. Organizations now look to packaging to deliver enhanced performance, reduced power consumption, and the integrity required by the diverse range of technologies encompassed in a single chip or package. This shift requires advanced multiscale design and analysis strategies that resonate across a spectrum of design domains.

Tooling Up for Chiplets with Cadence

Cadence exemplifies the rise of comprehensive tooling and workflows to facilitate chiplet-based automotive electronics design. Their integrations address the challenges that chiplet-based SoCs present, ensuring a seamless design process from the initial concept to production. The Cadence suite of tools is tailored to work across design domains, ensuring coherence and efficiency at every step of the chiplet integration process.

For instance, Cadence Virtuoso RF subflows have become critical in navigating radio frequency (RF) challenges within the chiplets, while tools such as the Integrity 3D-IC Platform and the Allegro Advanced Multi-Die Package Design Solution have surfaced to enable comprehensive multi-die package designs. The Integrity Signal Planner extends its capabilities into the chiplet ecosystem, providing a centralized platform where system-wide signal integrity can be proactively managed. Sigrity and Celsius, on the other hand, offer universally applicable solutions that take on the challenges of chiplets in signal integrity and thermal considerations, irrespective of the design domain. Each of these integrated analysis solutions underscores the intricate symphony between technology, design, and packaging essential in unlocking the potential of chiplets for automotive electronics.

Cadence portfolio includes solutions for system analysis, optimization, and signoff to complement these domain-specific tools, ensuring that the challenges of chiplet designs don't halt progress toward innovative automotive electronics. Cadence enables designers to engage in power- and thermal-aware design practices through their toolset, a necessity as automotive systems become increasingly sophisticated and power-efficient.

A Standardized Approach to Success with Chiplets

Cadence’s support for UCIe underscores the criticality of standardized approaches for heterogeneous integration by conforming to UCIe standards, which numerous industry stakeholders back. By co-chairing the UCIe Automotive working group, Cadence ensures that automotive designs have a universal and standardized Die-to-Die (D2D) high-speed interface through which chiplets can intercommunicate, unleashing the true potential of modular design.

Furthermore, Cadence champions the utilization of virtual platforms by providing transaction-level models (TLMs) for their UCIe D2D IP to simulate the interaction between chiplets at a higher level of abstraction. Moreover, individual chiplets can be simulated within a chiplet-based SoC context leveraging virtual platforms. Utilizing UVM or SCE-MI methodologies, TLMs, and virtual platforms serve as first lines of defense in identifying and addressing issues early in the design process before physical silicon even enters the picture.

Navigating With the Right Tools

The road to chiplet-driven automotive electronics is one paved with complexity, but with a commitment to standards, it is a path that promises significant rewards. By leveraging Cadence UCIe Design and Verification IP, tools, and methodologies, automotive designers are empowered to chart a course toward chiplets and help to establish a chiplet ecosystem. With challenges ranging from die-to-die interconnect to standardization, heterogeneous integration, and advanced packaging, the need for a seamless integrated flow and highly automated design approaches has never been more apparent. Companies like Cadence are tackling these challenges, providing the key technology for automotive designers seeking to utilize chiplets for the next-generation E/E architecture of vehicular technology.

In summary, chiplets have the potential to revolutionize the automotive electronics industry, breathing new life into the way vehicles are designed, manufactured, and operated. By understanding the significance of chiplets and addressing the challenges they present, automotive electronics is poised for a paradigm shift—one that combines the art of human ingenuity with the power of modular and scalable microchips to shape a future that is not only efficient but truly intelligent.

Learn more about how Cadence can help to enable automakers and OEMs with various aspects of automotive design.

LEF allows the same port with multiple shape definitions. Does anybody know if innovus can create multiple duplicate shapes associated with the same port? Assume they are connected outside the block with perfect timing synchronization. Thank you!

Does anyone know whether it is possible to have multiple contact points for a bond wire on a large die pad? Note: This is different from adding multiple wires which I will also be doing. I need to add multiple bond connections to the same large die pad for redundancy connections to each pad for each wire. I have a large die pad which I need to have 5 wires with each wire having 3 bond connections to the same die pad.

An increasing number of embedded designs are multi-core systems. At the pre-silicon stage, customers use a simulation platform for architectural exploration and software development. Architects want to quantify the impact of the number of cores, local memory size, system memory latency, and interconnect bandwidth. Software teams wish to have a practical development platform that is not excruciatingly slow. This blog shares a recipe for simulating Cadence DSPs in a multi-core design as separate x86 processes. The purpose is to reduce simulation time for customers with simple multi-core models where cores interact only through shared memory. It uses a Vision Q8 multi-core design to share details of the XTSC (Xtensa SystemC) model, software application, commands, and debugging. Note the details shared are for a simulation run on an Ubuntu Linux machine, Xtensa tools version RI-2023.11, and core configuration XRC_Vision_Q8_AODP. Complex vs. Simple Model A complex model (Figure 1) is one in which one core accesses another core's local memory, or there are inter-core interrupts. Simulation runs as a single x86 process. Figure 1 A simple model (Figure 2) is one in which cores interact only through shared memory. Shared memory is a file on the Linux host. Figure 2 Multiple x86 Process – Simple Model As depicted in Figure 3, each core is simulated using a separate x86 process. Cores use barriers and locks placed in shared memory for synchronization and data sharing. Locks are placed in un-cached memory that support exclusive subordinate access. The XTSC memory component, xtsc_memory , supports exclusive subordinate access. Cadence software tools provide a way to define memory regions as cached or uncached. For more details, please refer to Cadence's Linker Support Packages (LSP) Reference Manual for Xtensa SDK . Figure 3 Demo Application A demo application performs a 128x128 matrix multiplication. Work is divided so that each of the 32 cores computes four rows of the 128x128 result matrix. Cores use barriers to synchronize. Cadence tools provide APIs for synchronization and locking. Please refer to Cadence's System Software Reference Manual for more details. Note without a higher-level lock, prints from all cores will get mixed up. Therefore, in the demo application, only core#0 prints. SystemC Simulation The following sample command runs the 32-core simulation in such a way that each core is a separate x86 process. It runs a matrix multiplication application in cycle-accurate mode with logging off. >>for (( N=0; N >xtsc-run -define=NumCores=32 -define=N=0 -define=LOGGING=0 -define=TURBO=0 --xxdebug=sync -i=coreNN.inc -sc_main=sc_main.cpp -no_sim Modify the sc_main.cpp generated for core#0 to create a generic sc_main.cpp to build a single simulation executable for all cores. The Xtensa SDK includes Makefile targets to build custom simulations. By default, the simulation runs in cycle-accurate mode. Fast functional (Turbo) mode provides additional improvement over cycle-accurate mode. Note that the fast functional mode has an initialization phase, so gains are visible only when running an application with longer run times. Simulation Wall Time The table captures simulation wall time improvements. Note that these are illustrative wall time numbers. Actual wall time numbers and improvements will depend on your host machine's performance and your application. Simulation Type Wall Time Comments Single process cycle accurate mode 17500 seconds Multiple x86 processes cycle accurate mode 1385 seconds 12X faster than single process Multiple x86 processes turbo mode 415 seconds 3X faster than cycle accurate mode Debugging Attaching a debugger to each of the individual x86 core simulation processes is possible. Synchronous stop/resume and core-specific breakpoints are also supported. Configure the Xplorer launch configuration and attach it to the running simulation processes as follows (Figure 5) Figure 5 Figure 6 shows 32 debug contexts. Figure 6 As shown, using Xtensa SDK, you can create a multi-core simulation that functions as a practical software development platform. Please visit the Cadence support site for information on building and simulating multi-core Xtensa systems.

This is the 24th installment of The Rationalist, my column for the Times of India.

Back in the last decade, I was a cricket journalist for a few years. Then, around 12 years ago, I quit. I was jaded as hell. Every game seemed like déjà vu, nothing new, just another round on the treadmill. Although I would remember her fondly, I thought me and cricket were done.

And then I fell in love again. Cricket has changed in the last few years in glorious ways. There have been new ways of thinking about the game. There have been new ways of playing the game. Every season, new kinds of drama form, new nuances spring up into sight. This is true even of what had once seemed the dullest form of the game, one-day cricket. We are entering into a brave new world, and the team leading us there is England. No matter what happens in the World Cup final today – a single game involves a huge amount of luck – this England side are extraordinary. They are the bridge between eras, leading us into a Golden Age of Cricket.

I know that sounds hyperbolic, so let me stun you further by saying that I give the IPL credit for this. And now, having woken up you up with such a jolt on this lovely Sunday morning, let me explain.

Twenty20 cricket changed the game in two fundamental ways. Both ended up changing one-day cricket. The first was strategy.

When the first T20 games took place, teams applied an ODI template to innings-building: pinch-hit, build, slog. But this was not an optimal approach. In ODIs, teams have 11 players over 50 overs. In T20s, they have 11 players over 20 overs. The equation between resources and constraints is different. This means that the cost of a wicket goes down, and the cost of a dot ball goes up. Critically, it means that the value of aggression rises. A team need not follow the ODI template. In some instances, attacking for all 20 overs – or as I call it, ‘frontloading’ – may be optimal.

West Indies won the T20 World Cup in 2016 by doing just this, and England played similarly. And some sides began to realise was that they had been underestimating the value of aggression in one-day cricket as well.

The second fundamental way in which T20 cricket changed cricket was in terms of skills. The IPL and other leagues brought big money into the game. This changed incentives for budding cricketers. Relatively few people break into Test or ODI cricket, and play for their countries. A much wider pool can aspire to play T20 cricket – which also provides much more money. So it makes sense to spend the hundreds of hours you are in the nets honing T20 skills rather than Test match skills. Go to any nets practice, and you will find many more kids practising innovative aggressive strokes than playing the forward defensive.

As a result, batsmen today have a wider array of attacking strokes than earlier generations. Because every run counts more in T20 cricket, the standard of fielding has also shot up. And bowlers have also reacted to this by expanding their arsenal of tricks. Everyone has had to lift their game.

In one-day cricket, thus, two things have happened. One, there is better strategic understanding about the value of aggression. Two, batsmen are better equipped to act on the aggressive imperative. The game has continued to evolve.

Bowlers have reacted to this with greater aggression on their part, and this ongoing dialogue has been fascinating. The cricket writer Gideon Haigh once told me on my podcast that the 2015 World Cup featured a battle between T20 batting and Test match bowling.

This England team is the high watermark so far. Their aggression does not come from slogging. They bat with a combination of intent and skills that allows them to coast at 6-an-over, without needing to take too many risks. In normal conditions, thus, they can coast to 300 – any hitting they do beyond that is the bonus that takes them to 350 or 400. It’s a whole new level, illustrated by the fact that at one point a few days ago, they had seven consecutive scores of 300 to their name. Look at their scores over the last few years, in fact, and it is clear that this is the greatest batting side in the history of one-day cricket – by a margin.

There have been stumbles in this World Cup, but in the bigger picture, those are outliers. If England have a bad day in the final and New Zealand play their A-game, England might even lose today. But if Captain Morgan’s men play their A-game, they will coast to victory. New Zealand does not have those gears. No other team in the world does – for now.

But one day, they will all have to learn to play like this.

The India Uncut Blog © 2010 Amit Varma. All rights reserved.
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Hello everyone,

I hope you're all doing well. I’ve set up two testbenches (TB1 and TB2) for my Design Under Test (DUT) using Cadence IC6.1.8-64b.500.21 tools, as shown in the attached figure. The DUT has multiple views available: schematic, Calibre, Maestro, and Symbol, and each testbench uses the same DUT in different scenarios. Currently, I have to manually switch between these views, but I would like to streamline this process.

My goal is to use a single config view that allows me to switch between the schematic and the extracted (Calibre) views. Ideally, I would like to have a configuration file where making changes once would update both testbenches (TB1 and TB2) automatically. In other words, when I modify one config, both testbenches should reflect this update for a single simulation run.

I would really appreciate it if you could guide me on the following:

1. How to create a config view for my DUT that can be used to easily switch between the schematic and extracted views, impacting both TB1 and TB2.
2. Where to specify view priorities or other settings to control which view is used during simulation.
3. Best practices for using a config file in this scenario, so that it ensures consistency across multiple testbenches.

Please refer to the attached figure to get a better understanding of the setup I’m using, where both TB1 and TB2 include the same DUT with multiple available views.

Thank you so much for your time and assistance!

I want to use jaspergold to formally verify functionality of my custom multiplier. I am computing the expected result using A*B to check against output of my multiplier. Here, A and B are two logic signed operands. However, jaspergold is performing the operation A*B incorrectly.

I have reproduced this issue using the attached example. JasperGold compiles and elaborates the module and subsequently runs a formal proof. The tool raises a counterexample to assertion whose screenshot is attached below:

I simulated the same example using xrun and it was giving the correct product output in simvision waveform. Please help me resolve this issue. I am using 2023.03 version of Jasper Apps.

Thanks and regards

Anubhav Agarwal

When analyzing multiple sessions simultaneously Verisium Manager crashed and reported below error messages:

# A fatal error has been detected by the Java Runtime Environment:
#
#  SIGSEGV (0xb) at pc=0x00007efc52861b74, pid=14182, tid=18380
#
# JRE version: OpenJDK Runtime Environment Temurin-17.0.3+7 (17.0.3+7) (build 17.0.3+7)
# Java VM: OpenJDK 64-Bit Server VM Temurin-17.0.3+7 (17.0.3+7, mixed mode, sharing, tiered, compressed oops, compressed class ptrs, g1 gc, linux-amd64)
# Problematic frame:
# C  [libucis.so+0x238b74]

......

For more details please refer to the attached log file "hs_err_pid21143.log".

Two approaches were tried to solve this problem but neither has worked.
Method.1:

Setting larger heap size of Java process by "-memlimit" options.For example "vmanager -memlimit 8G".

Method.2:

Enlarging stack memory size limit of the Coverage engine by setting "IMC_NATIVE_STACKSIZE" environment variable to a larger value. For example "setenv IMC_NATIVE_STACKSIZE 1024000"

According to "hs_err_pid*.log" it is almost certain that the memory overflow triggered Java's CrashOnOutOfMemoryError and caused Verisium Manager to crash. There are some arguments about memory management of Java like "Xms, Xmx, ThreadStackSize, Xss5048k etc" and maybe this problem can be fixed by setting these arguments during analysis. However, how exactly does Verisium Manager specify these arguments during analysis? I tried to set them by the form of setting environment variables before analysis but it didn't work in analysis and their values didn't change.

Is there something wrong with my operation or is there a better solution?

Thank you very much.

I want to do a 2-step build->simulate as follow:

1. Make multiple builds using xrun -elaborate [other options]. The purpose is to create multiple builds with different compile-time macros (+define+MACROA +define+MACROB=ABC). Each build is located in a different directory.

2. Run simulation with xrun -r. This is where I need help. How do I specify which build to simulate? Also, I need the simulation directory (with log files, …) to be different than the build directory.

Has anyone been able to achieve this or similar solutions?

The two macros below introduce new syntax for adding definitions to more than one 'when' determinant value at the same time. The first macro overloads 'extend' keyword and the second is the equivalent for 'when' keyword.

A use example:

extend [HUGE, BIG] packet {
    // definitions that pertain to these subtypes
};

The above code would be expanded in the following (naive) way:

extend HUGE packet {
    // definitions that pertain to these subtypes
};
extend BIG packet {
    // definitions that pertain to these subtypes
};


The macros code:

define 'statement>
       "extend ['name>,...] 'name> ({;...})" as computed {
    for each in 'names> do {
        result = appendf("%sextend %s %s %s;",result,it,'name>,);
    };
    result = appendf("{%s}",result); // required only for versions 6.1.1 or earlier
};

define 'struct_member>
       "when ['name>,...] 'name> ({;...})" as computed {
    for each in 'names> do {
        result = appendf("%swhen %s %s %s;",result,it,'name>,);
    };
    result = appendf("{%s}",result); // required only for versions 6.1.1 or earlier
};

Check here each week to keep up with the latest from John MacArthur's pulpit at Grace Community Church.

The Nigeria Civil Aviation Authority has warned flight crew members, especially pilots against working for multiple airlines concurrently with their approved privileges simulators and proficiency checks endorsed on their licence. The authority stated that such action posed a serious threat to safety and would be treated as a serious violation of the NCAA Regulations. This

"Cain brought an offering to the Lord of the fruit of the ground. And Abel . . . brought of the firstlings of his flock and of their fat portions. And the Lord had regard for Abel and for his offering; but for Cain and for his offering He had no regard" (Gen. 4:3-5).

True discipleship is characterized by obedience to God’s Word.

In John 8:31 Jesus issued an important statement to a group of people who were showing an interest in Him: "If you abide in My word, then you are truly disciples of Mine." Sadly, they rejected His words, proving themselves to be less than true disciples. Jesus went on to explain why: "He who is of God hears the words of God; for this reason you do not hear them, because you are not of God" (v. 47). They listened but didn't really hear. They were interested but not truly committed. They were hearers of the Word but not doers (James 1:22).

In contrast, Abel did what God told him to do. He was, in effect, the first disciple. He was probably a better person than Cain—more friendly, moral, and dependable—but that's not why God accepted his sacrifice and rejected Cain's. Abel trusted God, and his faith was counted as righteousness. Like Abraham, whose faith was evidenced by his willingness to obey God and sacrifice his son Isaac (James 2:21-22), Abel's faith was evidenced in his obedient offering. He didn't rely on his own goodness but acknowledged his sin and made the prescribed sacrifice.

Perhaps God indicated His acceptance of Abel's sacrifice by consuming it with fire, as He did on other occasions in Scripture (Judg. 6:21; 1 Kings 18:38). But whatever means He used, God made his pleasure known to Abel.

Abel's brief life conveys a simple three-point message: we must come to God by faith; we must receive and obey God's Word; and sin brings serious consequences. If you hear and heed that message, you'll walk the path of true discipleship and be assured of God's pleasure.

Suggestions for Prayer

Make it your goal to please the Lord in everything you do today. Seek His wisdom and grace to do so faithfully.

For Further Study

Read these verses, noting what they say about pleasing God: 2 Corinthians 5:9; Ephesians 5:6-10; Philippians 2:12-13; Hebrews 11:6; and Hebrews 13:15-16, 20-21.

From Drawing Near by John MacArthur Copyright © 1993. Used by permission of Crossway Books, a division of Good News Publishers, Wheaton, IL 60187, www.crossway.com.

• The Study Bible (mobile app)
• Grace to You Sermons (mobile app)
• John MacArthur’s complete sermon archive
• The MacArthur Study Bible
• The complete MacArthur New Testament Commentary series

Diplomacy is in full swing as U.S. President Joe Biden meets with Israel's president, and President-elect Donald Trump speaks with Israel's prime minister. Fast-rising methane emissions could undermine efforts to limit global warming by mid-century, prompting scientists and policymakers to urge aggressive action to curb the output of the potent greenhouse gas. An election in Somaliland, and the fight against Boko Haram in Chad. Plus, Trump’s foreign policy.

Around 500 participants took part, including representatives from ASEAN, the EU and its Member States, youth and individuals with special needs. The event took place along Jalan Sudirman, leading to Gelora Bung Karno, Senayan, Jakarta.

Women in Buddhism Principles of Civility

La enseñanza bíblica en profundidad de John MacArthur lleva la verdad transformadora de la Palabra de Dios a millones de personas cada día.

La enseñanza bíblica en profundidad de John MacArthur lleva la verdad transformadora de la Palabra de Dios a millones de personas cada día.

La enseñanza bíblica en profundidad de John MacArthur lleva la verdad transformadora de la Palabra de Dios a millones de personas cada día.

La enseñanza bíblica en profundidad de John MacArthur lleva la verdad transformadora de la Palabra de Dios a millones de personas cada día.

GENEVA — The U.N. weather agency is predicting that the phenomenon known as La Nina is poised to last through the end of this year, a mysterious “triple dip” — the first this century — caused by three straight years of its effect on climate patterns like drought and flooding worldwide. The World Meteorological Organization on Wednesday said La Nina conditions, which involve a large-scale cooling of ocean surface temperatures, have strengthened in the eastern and central equatorial Pacific with an increase in trade winds in recent weeks. The agency’s top official was quick to caution that the “triple dip” doesn’t mean global warming is easing. “It is exceptional to have three consecutive years with a La Nina event. Its cooling influence is temporarily slowing the rise in global temperatures, but it will not halt or reverse the long-term warming trend,” WMO Secretary-General Petteri Taalas said. La Nina is a natural and cyclical cooling of parts of the equatorial Pacific that changes weather patterns worldwide, as opposed to warming caused by the better-known El Nino — an opposite phenomenon. La Nina often leads to more Atlantic hurricanes, less rain and more wildfires in the western United States, and agricultural losses in the central U.S. Studies have shown La Nina is more expensive to the United States than the El Nino. Together El Nino, La Nina and the neutral condition are called ENSO, which stands for El Nino Southern Oscillation, and they have one of the largest natural effects on climate, at times augmenting and other times dampening the big effects of human-caused climate change from the burning of coal, oil and gas, scientists say.

With ISIS continuing to terrorize and control broad swaths of the country, and with international intervention now underway, Iraq also faces a potential political crisis.

[Radio Dalsan] In a move that has captured international attention, Somalia's Minister of Foreign Affairs, Ahmed Moalim Fiqi, has announced plans to relocate the Ethiopian Embassy currently housed within the Somali presidential compound.

A weekly selection of opinions and analyses from the Arab media around the world.

Some of the creeping impacts of this triple crisis are possibly the most debilitating: Africa is the most severely impacted region by desertification and land degradation, with approximately 45% of its land area affected. In the Horn of Africa and the Sahel alone, it imposes food shortages on more than 23 million people. Just last […]