1 Jordanian Dinar = 71.1694 Philippine Peso

1 Lebanese Pound = 0.0334 Philippine Peso

1 Bahraini Dinar = 133.5214 Philippine Peso

1 Chilean Peso = 0.0611 Philippine Peso

1 Maldivian Rufiyaa = 3.257 Philippine Peso

1 Malaysian Ringgit = 11.6508 Philippine Peso

1 Nicaraguan Cordoba Oro = 1.4677 Philippine Peso

1 Netherlands Antillean Guilder = 28.1278 Philippine Peso

1 Estonian Kroon = 3.5404 Philippine Peso

1 Danish Krone = 7.3384 Philippine Peso

1 Fiji Dollar = 22.4119 Philippine Peso

1 New Zealand Dollar = 30.9937 Philippine Peso

1 Croatian Kuna = 7.2774 Philippine Peso

1 Peruvian Nuevo Sol = 14.8557 Philippine Peso

1 Dominican Peso = 0.9174 Philippine Peso

1 Papua New Guinean Kina = 14.7199 Philippine Peso

1 Brunei Dollar = 35.7294 Philippine Peso

Hi,

When I import the top level Verilog file generated by Genus into Virtuoso, the power pins are left unconnected. I tried different configurations in "Global Net Options" tab. However, nothing changed. 

The cell is imported with three views, namely functional, schematic, and symbol. In www krogerfeedback com functional view everything looks OK, that is the top level Verilog file. In schematic, I can see the digital cells but VDD and VSS pins of the blocks are not connected. In the symbol view there are no pins for VDD and VSS. 

On top, we are trying to implement a digital block into Virtuoso. The technology is TSMC 65nm. On Genus and Innovus, everything goes straight and layout is generated successfully.

Thanks.

Hi,

I am doing layout for a mixed-signal circuit in Innovus. I want to create a digital donut style of layout (i.e. put analog circuit in the middle, and circle analog part with digital circuits).

To do that, I need to place some pins inside the edge to connect to analog circuit (as shown in my attachment), but the problems is that I cannot place pins inside the edge by using "pin editor" within Innovus. Any suggestions to place pins inside?

Thank you so much for your time and effort.

Vegas, here we come. All of us fun EDA engineers at once. Be prepared, next week’s Design Automation Conference will be busy! The trends I had outlined after last DAC in 2018—system design, cloud, and machine learning—have...(read more)

I have created a die and other components as symbols in sip and placed the symbols in sip through logic import capture netlist. It shows net connectivity but i couldn't add bond finger from the die pins. Please help on this. 

Freescale was a successful Incisive® simulation CPF low-power user when they decided to step up their game. In November 2013, at CDNLive India, they presented a paper explaining how they improved their ability to find power-related bugs using a more sophisticated verification flow.  We were able to catch up with Abhinav Nawal just after his presentation to capture this video explaining the key points in his paper.

Abhinav had already established a low-power simulation process using directed tests for a design with power intent captured in CPF. While that is a sound approach, it tends to focus on the states associated with each power control module and at least some of the critical power mode changes.  Since the full system can potentially exercise unforeseen combinations of power states, the directed test approach may be insufficient. Abhinav built a more complete low-power verification approach rooted in a low-power verification plan captured in Cadence® Incisive Enterprise Manager.  He still used Incisive Enterprise Simulator and the SimVision debugger to execute and debug his design, but he also added Incisive Metric Center to analyze coverage from his low-power tests and connect that data back to the low-power verification plan.  As a result, he was able to find many critical system-level corner case issues, which, left undetected, would have been catastrophic for his SoC.  In the paper, Abhinav presents some of the key problems this approach was able to find.

You can achieve results similar to Abhinav. Incisive Enterprise Simulator can generate a low-power verification plan from the power format, power-aware assertions, and it can collect power-aware knowledge.  To get started, you can use the Incisive Low-Power Simulation Rapid Adoption Kit (RAK) for CPF available on Cadence Online Support.

Just another happy Cadence low-power verification user!

Regards,

Adam "The Jouler" Sherer  

Hello All,

After selecting a cline (using axlSingleSelectBox), may I know how to obtain the dbid of the 'pin' connected to the end of the cline?

Thanks All

Hi,

I wanted to find the location of a pin in the design using skill program. pin_dbids = axlDBGetDesign()->pins, this gives me all the dbids of the pins that are present in my design. But when im entering that dbid, pad = axlDBGetPad("000001EA8FD8B9F8" "package geometry/assembly_top" "regular") it is throwing an error stating "This dbid is not user defined. Please enter the user defined". So please provide me a snippet so that I can get the exact pin location in the design using skill script.

Hi, I'm trying to create a circle from a pin with 10 mil air gap and at 45 degree rotation. The problem that im facing is that, I'm unable to get the bBox upper left coordinates. Because I want my circle to be placed from that coordinate with a 10 mil air gap. And the pins are "regular" and are placed on "Etch/Top" Layer. Kindly help me in solving this issue.

Hi All,

I'm trying to understand checkpoint concept. When I found save and restart concept in cdnshelp, There is just describing about "$save" and "xrun -r "~~~".

and I found also the below link about save restart and it saves your time.

But I can't find any benefits from my experiment from save&restart article( I fully agree..the article)

Ok, So I'v got some experiment  Here.

1. I declared $save and got the below result as I expected within the simple UVM code.

In UVM code...

$display("TEST1");
$display("TEST2");
$save("SAVE_TEST");
$display("TEST3");
$display("TEST4");

And I restart at "SAVE_TEST" point by xrun -r "SAVE_TEST", I've got the below log

xcelium> run
TEST3
TEST4

Ok, It's Good what I expected.(The concept of Save and Restore is simple: instead of re-initializing your simulation every time you want to run a test, only initialize it once. Then you can save the simulation as a “snapshot” and re-run it from that point to avoid hours of initialization times. It used to be inconvenient. I agree..)

2. But The Problem is that I can't restart with modified code. Let's see the below example.

I just modified TEST5 instead of "TEST3"

$display("TEST1");
$display("TEST2");
$save("SAVE_TEST");
$display("TEST5"); //$display("TEST3");
$display("TEST4");

and I rerun with xrun -r "SAVE_TEST", then I've got the same log

xcelium> run
TEST3
TEST4

There is no "TEST5". Actually I expected "TEST5" in the log.From here We know $save can't support partially modified code after $save. 

Actually, through this, we can approach to our goal about saving developing time. 

So I want to know Is there any possible way that instead of re-initializing our simulation every time we want to run a test, only initialize it once and keep developing(debugging) our code ?

If we do, Could you let me know the simple example?

Hi all,

I need to develop a digital design/verification solution to compile,elaborate and simulate SV designs (basically a complex xrun wrapper). I am an experienced user of xrun and I have done a number of these wrappers over the years but this one is to be more of a tool, intented to be used Company-wise, so it needs to be very well thought and engineered.

It needs to be robust, simple and extensible. It needs to support multi-snapshot elaboration, run regressions on machine farms, collect coverage, create reports, etc.

I've been browsing the vast amount of documentation on XCELIUM and, although very good, I can't find any document which puts together all the pieces of what I am trying to achieve. I suppose I am more clear on the elaboration, compilation and simulation part but I am really lacking on the other areas like : LSF, regressions coverage, where does vManager fits in all this, etc.

I'd appreciate if someone can comment on whether there is a document which depicts how such a DV flow can be put together from scratch, or whether there is a kind of RAK with some example xrun wrapper.

Thanks

When I run simulation with irun, it may use may license features. How can I know which feature(s) a product use? I get below message in cdnshelp:

-------------------------------------------------------------

Which Products Are in the License File?

One Cadence product can require more than one license (FEATURE). The product to feature mapping in the license file lists the licenses each product needs.

For example, if the license file lists these features for the NC-VHDL Simulator:

Product Name: Cadence(R) NC-VHDL Simulator
#
Type: Floating Exp Date: 31-jul-2006 Qty: 1
#
Feature: NC_VHDL_Simulator [Version: 9999.999]
#
Feature: Affirma_sim_analysis_env [Version: 9999.999]

-------------------------------------------------------------------

But, in my license file, I can't find such info. There is only "FEATURE" lines in my license file. How can I get product to feature mapping info?

Thanks!

Here are two screen capture of Before and After Autorouting my board. Padstacks have all been revised and corrected. The Capture Schematic is correct. All Footprints have been verified after Padstack revision. a new NETLIST generation have been done after some corrections made in Capture. I have imported the new Logic. I revised my Layout Cross Section as such: TOP, GND, VCC, BOTTOM. Both VCC and GND shapes have been assigned to their respective logical GND and VCC Nets (verified). Yet, I still have the Autorouter to systematically use extra vias to make GND and VCC connections to the VCC and GND planes. Where a simple utilisation of the part padstack inner layer would have been indicated. What Im I missing ?

Hi,

I have a new customer that uses Allegro Design entry HDL for the schematic and have a few questions.

1. How do you get pin/gate swaps into the symbols in the schematic ?

2. How do you transfer them to the pcb editor ?

3. How do you back annotate the swaps from the pcb editor to the schematic ?

4. How do you stop the export/Import physical from updating the constraints in the pcb file ? 

We have all heard the sayings “Less is more” and “Keep it simple”. Electromagnetic simulation is an activity where following that advice has enormous payoffs. In this blog I’ll talk about some of my experiences with how Virtuoso RF Solution’s shape simplification feature has helped my customers get significant performance improvements with minimal impacts on accuracy. (read more)

CDS Bipin Rawan: Air Force રવિવારે કોરોના યોદ્ધાઓને સલામ કરવા Flypast કરશે

Super Pink moon: 8 એપ્રિલે ચૈત્રી પૂર્ણિમાનો શુભ સંયોગ, આ સમયે જુઓ સુપરમૂન

An ICMP Type 8 (ping) flooder for Windows 95 and above. Includes Delphi source code.