Set of compositions for preparing system-in-package type semiconductor device. The composition set consists of underfill composition for preparing underfill part and encapsulation resin composition for preparing resin encapsulation part. 1) A cured product of the underfill composition has a glass transition temperature, Tg, ≧100° C. and is the same with or differs from a Tg of a cured product of the encapsulation resin composition by ≦20° C. 2) Total linear expansion coefficient of the cured product of the underfill composition at a temperature not higher than (Tg−30)° C. and a linear expansion coefficient of the cured product of the encapsulation resin composition at a temperature not higher than (Tg−30)° C. is ≦42 ppm/° C. 3) A ratio of the linear expansion coefficient of the cured product of the encapsulation resin composition to the linear expansion coefficient of the cured product of the underfill composition ranges from 0.3 to 1.0.

Disclosed is an epoxy resin composition used for encapsulation of a semiconductor containing an epoxy resin (A), a curing agent (B), an inorganic filler (C) and a mold releasing agent, in which the mold releasing agent contains a compound (D) having a copolymer of an α-olefin having 28 to 60 carbon atoms and a maleic anhydride esterified with a long chain aliphatic alcohol having 10 to 25 carbon atoms.

A heat-resistant cured product is efficiently produced by obtaining a semi-cured product where a curable resin composition containing a (meth)acrylate monomer, a non-conjugated vinylidene group-containing compound and a thermal radical-polymerization initiator is processed by at least one of photoirradiation and heating to give a semi-cured product having a complex viscosity of from 105 to 108 mPa·s at 25° C. and at a frequency of 10 Hz; and putting the semi-cured product in a forming die for pressure formation therein, and heating it therein for thermal polymerization to give a cured product.

A semiconductor memory device includes a selection signal generation unit configured to generate a plurality of selection signals that are sequentially activated, a path selection unit configured to select a transmission path of sequentially input information data in response to the plurality of selection signals, a plurality of first storage units, each configured to have a first storage completion time and store an output signal of the path selection unit, and a plurality of second storage units, each configured to have a second storage completion time, which is longer than the first storage completion time, and store a respective output signal of the plurality of first storage units.

A method for bypassing a defective through silicon via x in a group of n adjacent through silicon vias, includes receiving a plurality of relief signals to identify the defective through silicon via x, activating x−1 switch circuits to connect x−1 data circuits to through silicon vias 1 to x−1 in the group of n adjacent through silicon vias, activating n-x switch circuits to connect n-x data circuits to through silicon vias x+1 to n in the group of n adjacent through silicon vias, and activating a switch circuit to connect a data circuit to an auxiliary through silicon via which is adjacent through silicon via n in the group of n adjacent through silicon vias.

A relationship between distance from a back bias control section which outputs a control signal for controlling a back bias of a transistor and an amount of noise in the control signal outputted from the back bias control section is found. An increase of jitter corresponding to the amount of the noise in a clock transmitted on a clock path connected to a circuit section (IP macro) is found on the basis of the relationship between the distance from the back bias control section and the amount of the noise. The circuit section and the clock path are placed on the basis of the increase of the jitter and an allowable jitter value for the circuit section.

A method and apparatus for partitioning of the input design into repeating patterns called template cores for the application of reticle enhancement methods, design verification for manufacturability and design corrections for optical and process effects is accomplished by hierarchy analysis to extract cell overlap information. Also hierarchy analysis is performed to extract hierarchy statistics. Finally template core candidates are identified. This allows to the design to be made amenable for design corrections or other analyses or modifications that are able to leverage the hierarchy of the design since the cell hierarchy could otherwise be very deep or cells could have significant overlap with each other.

A method for accurately determining the shape of currents in a current spectrum for a circuit design is provided. The method includes determining timing and power consumption characteristics. In one embodiment, timing characteristics are provided through a electronic design automation tool. The timing characteristics yield a current pulse time width. In another embodiment, power consumption characteristics are provided by an EDA tool. The power consumption characteristics yield a current pulse amplitude. The shape of the current pulse is obtained by incrementally processing a power analyzer tool over relatively small time increments over one or more clock cycles while capturing the switching nodes of a simulation of the circuit design for each time increment. In one embodiment, the time increments are one nanosecond or less.

The present invention is directed to provide a semiconductor surface treating agent; composition which is capable of stripping an anti-reflection coating layer, a resist layer, and a cured resist layer in the production process of a semiconductor device and the like easily and in a short time, as well as a method for treating a semiconductor surface, comprising that the composition is used. The present invention relates to a semiconductor surface treating agent; composition, comprising [I] a compound generating a fluorine ion in water, [II] a carbon radical generating agent; , [III] water, [IV] an organic solvent, and [V] at least one kind of compound selected from a group consisting of hydroxylamine and a hydroxylamine derivative represented by the general formula [1], as well as a method for treating the semiconductor surface, comprising that the composition is used: (wherein R1 represents a linear, branched or cyclic C1-6 alkyl group, or a linear or branched C1-4 substituted alkyl group having 1 to 3 hydroxyl groups; R2 represents a hydrogen atom, a linear, branched or cyclic C1-6 alkyl group, or a linear or branched C1-4 substituted alkyl group having 1 to 3 hydroxyl groups).

Provided is a method of producing an organic transistor, including collectively forming a gate insulating film and an organic semiconductor film by applying, onto a gate electrode, a solution including a polymer and at least one of compounds represented by General Formulas 1 to 4 and 5 to 7, a compound having a structure represented by General Formula 4, a compound having a structure represented by General Formula 5 or 6, and forming a source electrode and a drain electrode on the organic semiconductor film. (where R is a linear or branched alkyl group) (where R is an alkyl group) (where R is an alkyl group) (where A1 and A2 are represented by Formula 8) (where R is an alkyl group or another substituent).

A system for testing a plurality of transistors on a wafer having a storage device or personal computer connected via a bus to a plurality of drivers. Each of the voltage drivers having a microcontroller adapted to receive test parameters and provide test data from a plurality of voltage drivers. By utilizing a bus structure, the personal computer can look on one bus for flags indicating test data is available from a driver and receive the data. In addition a bus may be used to provide test parameters to the drivers. In this manner, multiple drivers may be run at the same time incorporating multiple tests. When data is available it is transferred to the personal computer, for providing test parameters to a plurality of drivers, and connected via a second bus for receiving test results from the plurality of drivers.

Disclosed are polysulfone-based materials that can be used as active and/or passive components in various electronic, optical, and optoelectronic devices, particularly, metal-oxide-semiconductor field-effect transistors. For example, various metal-oxide-semiconductor field-effect transistors can include a dielectric layer and/or a passivation layer prepared from such polysulfone-based materials and exhibit good device performance.

An apparatus for fabricating a semiconductor package may include a mold and a molding plate. The mold may define a mold cavity with the mold being configured to receive a circuit board in the mold cavity, and the circuit board may include a semiconductor chip mounted thereon. A molding plate may be moveable in the mold cavity with the molding plate being configured to adjust a volume of the mold cavity. Related methods are also discussed.

Disclosed is a positive photosensitive resin composition that includes (A) an alkali soluble resin prepared by a phosphorous-containing diamine represented by the following Chemical Formula 1, (B) a photosensitive diazoquinone compound, and (C) a solvent. A photosensitive resin film prepared using the same and a semiconductor device including the photosensitive resin film are also disclosed. In Chemical Formula 1, each substituent is the same as defined in the detailed description.

A method for forming patterns of a semiconductor device includes providing a photomask that includes an array of contact holes in an active region, a plurality of first dummy contact holes for restricting pattern distortion of the contact holes in an area outside of the array of the contact holes, a plurality of first assist features for restricting pattern distortion of the first dummy contact holes disposed inside a corresponding one of the first dummy contact holes, and an array of second assist features for additionally restricting pattern distortion of the first dummy contact holes. The array of second assist features is disposed outside of the first dummy contact holes. The method also includes forming an array of contact holes and first dummy contact holes on a wafer by using the photomask as an exposure mask.

A mask blank for use in the manufacture of a binary mask adapted to be applied with ArF excimer laser exposure light has, on a transparent substrate, a light-shielding film for forming a transfer pattern. The light-shielding film has a laminated structure of a lower layer and an upper layer and has an optical density of 2.8 or more for exposure light and a thickness of 45 nm or less. The lower layer is made of a material in which the total content of a transition metal and silicon is 90 at % or more, and has a thickness of 30 nm or more. The upper layer has a thickness of 3 nm or more and 6 nm or less. The phase difference between exposure light transmitted through the light-shielding film and exposure light transmitted in air for a distance equal to the thickness of the light-shielding film is 30 degrees or less.

A polishing pad, having a polishing layer comprising a thermoset polyurethane foam, wherein the polishing layer has an in-plane variation of 12 or less in microrubber A hardness, the variation being obtained by measuring the polishing layer from a polishing surface side of the layer, the thermoset polyurethane foam contains, as raw material components, an isocyanate component and active-hydrogen-containing compounds, and the active-hydrogen-containing compounds comprise a trifunctional polyol having at least one terminated hydroxyl group that is a secondary hydroxyl group, and having a hydroxyl group value of 150 to 1,000 mg KOH/g in an amount of 10 to 50 parts by weight for 100 parts by weight of the active-hydrogen-containing compounds.

Provided is a configuration in which it is possible to mount an applied voltage suppression circuit configured to prevent voltage breakdown of a semiconductor switching element, and a set voltage thereof can be inspected without damaging an IC or the like of a peripheral circuit. In a power converter having a semiconductor switching element, an applied voltage suppression circuit configured to suppress a voltage applied to the semiconductor switching element and at least one component of constituent components of a driving circuit which causes the semiconductor switching element to be turned off if the component is absent are transferred to and disposed on a slave substrate (separate unit) which is divided from and electrically connected to a master substrate including the semiconductor switching element, the driving circuit, a control circuit, and the like mounted thereon.

A semiconductor device of a three-level inverter circuit with a reduced number of power supplies for driving IGBTs. The semiconductor device includes a series-connected circuit of IGBTs between P and N of a DC power supply and an AC switch element that is connected between a series connection point of the series-connected circuit and a neutral point of the DC power supply. The series-connected circuit and the AC switch element are integrated into one module. The AC switch element is formed by connecting a collector of a first IGBT to which a diode is connected in reverse parallel and a collector of a second IGBT to which a diode is connected in reverse parallel, and an intermediate terminal is provided at a connection point between the collectors.

A lead-free conductive paste composition contains a source of an electrically conductive metal, a fusible material, an optional additive, and an organic vehicle. An article such as a high-efficiency photovoltaic cell is formed by a process of deposition of the lead-free paste composition on a semiconductor substrate (e.g., by screen printing) and firing the paste to remove the organic vehicle and sinter the metal and fusible material.

Provided is a resistive element which has excellent inrush current resistance, and can suppress heat generation in a steady state. The resistive element has an element main body of a semiconductor ceramic in which the main constituent has a structure of R11-xR2xBaMn2O6 in which 0.05≦x≦1.0 when R1 is Nd and R2 is at least one of Sm, Eu and Gd; 0.05≦x≦0.8 when R1 is Nd and R2 is at least one of Tb, Dy, Ho, Er, and Y; 0≦x≦0.4 when R1 is at least one of Sm, Eu, and Gd and R2 is at least one of Tb, Dy, Ho, and Y; and 0≦x≦1.0 when R1 is at least one of Sm, Eu, and Gd and R2 is at least one of Sm, Eu, and Gd, but the Sm, Eu, and/or Gd in R1 is different from that in R2.

Provided is a resistive element which is excellent in inrush current resistance even in the case of having a surface-mountable small chip shape. The resistive element has an element main body composed of a semiconductor ceramic in which a main constituent thereof is composed of a Mn compound represented by the general formula (Nd1-xMx)yBazMn2O6 (M is at least one rare-earth element selected from Sm, Gd, Eu, Tb, Dy, Ho, Er, and Y), and x, y, and z respectively meet the conditions of: 0.05≦x≦0.4; 0.80≦y≦1.2; and 0.80≦z≦1.2 in the chemical formula.

A support disk fixing apparatus which includes an upper surface to which a wafer is bonded, a lower surface, a cylindrical side surface between the upper surface and the lower surface, and a chamfered portion between the upper surface and the side surface, includes a base upon which the support disk is placed; and a fixture that is provided on the base, and that has a first surface that abuts against the side surface of the support disk and covers the side surface of the support disk, and a second surface that abuts against the chamfered portion of the support disk and covers the chamfered portion of the support disk.

A support structure for supporting a semiconductor device during a bonding operation is provided. The support structure comprises a body portion defining an upper surface configured to support a semiconductor device during a bonding operation. The upper surface defines a constraining feature for constraining at least a portion of the semiconductor device during the bonding operation.

A power semiconductor has power terminals arranged in a row at one side of the housing, with control terminals arranged in a row at the other side of the housing. The spacing between adjacent power terminals is greater than the spacing between adjacent control terminals.

An apparatus includes a first substrate having a first land and a second substrate having a second land. A first molding compound is disposed between the first substrate and the second substrate. A first semiconductor chip is disposed on the first substrate and in contact with the first molding portion. A first connector contacts the first land and a second connector contacts the second land. The second connector is disposed on the first connector. A volume of the second connector is greater than a volume of the first connector. A surface of the first semiconductor chip is exposed. The first molding compound is in contact with the second connector, and at least a portion of the second connector is surrounded by the first molding compound.

A semiconductor device effectively suppress the problem of mutual interaction occurring between an inductor element and wires positioned above the inductor element formed over the same chip. A semiconductor device includes a semiconductor substrate and a multi-wiring layer formed overlying that semiconductor substrate, and in which the multi-wiring layer includes: the inductor element and three successive wires and a fourth wire formed above the inductor element; and two shielded conductors at a fixed voltage potential and covering the inductor element as seen from a flat view, and formed between the inductor element and three successive wires and a fourth wire formed above the inductor element.

A power inverter includes a power semiconductor module that includes a power semiconductor device, a control circuit board that outputs a control signal used for controlling the power semiconductor device, a driver circuit board that outputs a driving signal used for driving the power semiconductor device, a conductive metal base plate arranged in a space between the driver circuit board and the control circuit board in which a fine and long opening portion is formed, wiring that connects the driver circuit board and the control circuit board through the opening portion and delivers the control signal to the driver circuit board, and an AC busbar that is arranged on a side opposite to the metal base plate through the driver circuit board and delivers an AC current output from the power semiconductor module to a drive motor. At least a portion of the AC busbar that faces the opening portion extends in a direction directly running in a longitudinal direction of the fine and long opening portion.

Reduction in cooling rate of a substrate having a lower temperature is suppressed because the substrate having a lower temperature is not affected by radiant heat of a substrate having a higher temperature while cooling a plurality of substrates in a cooling chamber. The substrate processing apparatus includes a load lock chamber configured to accommodate stacked substrates; a first transfer mechanism having a first transfer arm provided with a first end effector, and configured to transfer the substrates into/from the load lock chamber at a first side of the load lock chamber; a second transfer mechanism having a second transfer arm provided with a second end effector, and configured to transfer the substrates into/from the load lock chamber at a second side of the load lock chamber; a barrier installed between the substrates to be spaced apart from the substrates supported by a substrate support provided in the load lock chamber; and an auxiliary barrier unit installed between the substrate support and the barrier, wherein the auxiliary barrier unit is installed at places other than standby spaces of the end effectors.

According to one embodiment, a system for manufacturing a semiconductor device includes a spontaneous joining unit and a deformative joining unit. The spontaneous joining unit overlaps a first substrate and a second substrate and spontaneously joins mutual center portions of respective joint faces of the first substrate and the second substrate. The deformative joining unit deforms at least one peripheral portion of the respective joint faces of the first substrate and second substrate joined by the spontaneous joining unit toward the other peripheral portion and joins the mutual peripheral portions of the respective joint faces.

A D/A conversion circuit with a small area is provided. In the D/A conversion circuit, according to a digital signal transmitted from address lines of an address decoder, one of four gradation voltage lines is selected. A circuit including two N-channel TFTs is connected in series to a circuit including two P-channel TFT, and a circuit including the circuits connected in series to each other is connected in parallel to each of the gradation voltage lines. Further, an arrangement of the circuit including the two N-channel TFTs and the circuit including the two P-channel TFTs is reversed for every gradation voltage line. By this, the crossings of wiring lines in the D/A conversion circuit becomes small and the area can be made small.

A conduction cooled high power semiconductor laser and a method for fabricating the same are provided. The conduction cooled high power semiconductor laser comprises a heat sink (2) and one or more semiconductor laser units (1). The semiconductor laser unit consists of a laser chip (3), a substrate (4) bonded to the laser chip for heat dissipation and electrical connection, and an insulation plate (5) soldered to the substrate for insulation and heat dissipation. The semiconductor laser unit is soldered on the heat sink with the insulation plate therebetween. The semiconductor laser unit may be tested, aged, and screened in advance, and thereby the yield of the lasers can be improved and the manufacturing costs can be reduced. The laser has desirable heat dissipation performance, high reliability, and is applicable to high temperature and other complex and volatile environments.

A method of manufacturing an optical semiconductor device including: forming a mesa structure including a first conductivity type cladding layer, an active layer and a second conductivity type cladding layer in this order on a first conductivity type semiconductor substrate, an upper most surface of the mesa structure being constituted of an upper face of the second conductivity type cladding layer; growing a first burying layer burying both sides of the mesa structure at higher position than the active layer; forming an depressed face by etching both edges of the upper face of the second conductivity type cladding layer; and growing a second burying layer of the first conductivity type on the depressed face of the second conductivity type cladding layer and the first burying layer.

An intra-cavity frequency doubled OPS-laser includes a laser-resonator terminated by a plane mirror and a mirror-structure of an OPS-chip. The resonator is folded by three fold-mirrors. The fold-mirrors are supported on a vibration-isolation plate supported by isolation posts above a base-plate. The plane mirror and the mirror-structure of the OPS-chip are mounted back to back on opposite parallel surfaces of a mounting block. The mounting-block is supported on the base-plate and extends through an aperture in the vibration-isolation plate. Movement of the vibration-isolation plate with respect to the base-plate does not change the resonator length.

A method for quasi-synchronous tuning of wavelength or frequency of grating external-cavity semiconductor laser and a corresponding semiconductor laser are provided. A grating or mirror is rotated around a quasi-synchronous tuning point (Pq) as rotation center, so as to achieve the frequency selections by grating and resonance cavity in quasi-synchronous tuning, wherein the angle of the line between the quasi-synchronous tuning point (Pq) and a conventional synchronous tuning point (P0) with respect to the direction of light incident on the grating is determined according to the angle difference between the incidence angle and diffraction angle of light on the grating. According to present invention, approximately synchronous tuning of laser is achieved with a simple and flexible design.

A method for fabricating a group-III nitride semiconductor laser device stably supplies laser cavity mirrors having a low lasing threshold current through the use of a semi-polar plane. A blade 5g is forced down through a first region ER1 to keep the first region ER1 squeezed between a support member H2 and a movable member H1 together with a part of a protective sheet TF in contact with the first region ER1 while the tension generated in the area of the protective sheet TF in contact with the first region ER1 with the movable member H1 increases until the semi-polar principal surface SF at an end face EG1 of the first region ER1 tilts by a deflection angle THETA from the semi-polar principal surface SF of a second region ER2, and a force is thereby generated in the first region ER1 in a direction opposite to the direction of travel of the blade 5g toward the first region ER1. For example, an angle ALPHA is within the range of 71 degrees to 79 degrees, and the deflection angle THETA is within the range of 11 to 19.

Tensile strained germanium is provided that can be sufficiently strained to provide a nearly direct band gap material or a direct band gap material. Compressively stressed or tensile stressed stressor materials in contact with germanium regions induce uniaxial or biaxial tensile strain in the germanium regions. Stressor materials may include silicon nitride or silicon germanium. The resulting strained germanium structure can be used to emit or detect photons including, for example, generating photons within a resonant cavity to provide a laser.

A semiconductor laser includes a semiconductor nanowire of a first conductivity type provided over a substrate, a light emitting layer provided around the semiconductor nanowire and insulated at an upper end and a lower end thereof, a cladding layer of a second conductivity type different from the first conductivity type, the cladding layer being provided at an outer periphery of the light emitting layer, a first electrode electrically coupled to an end portion of the semiconductor nanowire, a second electrode electrically coupled to an outer periphery of the cladding layer, a first reflection mirror provided at a one-end portion side of the semiconductor nanowire, and a second reflection mirror provided at the other end portion side of the semiconductor nanowire.

A fiber coupled semiconductor device and a method of manufacturing of such a device are disclosed. The method provides an improved stability of optical coupling during assembly of the device, whereby a higher optical power levels and higher overall efficiency of the fiber coupled device can be achieved. The improvement is achieved by attaching the optical fiber to a vertical mounting surface of a fiber mount. The platform holding the semiconductor chip and the optical fiber can be mounted onto a spacer mounted on a base. The spacer has an area smaller than the area of the platform, for mechanical decoupling of thermally induced deformation of the base from a deformation of the platform of the semiconductor device. Optionally, attaching the fiber mount to a submount of the semiconductor chip further improves thermal stability of the packaged device.

A method to tune an emission wavelength of a laser diode (LD) finely is disclosed. The method first controls a temperature of the etalon filter in T1 or T2, where the transmittance of the etalon filter becomes 40 to 50%, assuming a height between the peak and the bottom of the periodic transmittance to be 100%, at the grid wavelength λ1 or λ2, respectively. Then, the temperature of the LD is adjusted such that the intensity of light emitted from the LD and transmitted through the etalon filter becomes 40 to 50%.

A device including one or more layers with lateral regions configured to facilitate the transmission of radiation through the layer and lateral regions configured to facilitate current flow through the layer is provided. The layer can comprise a short period superlattice, which includes barriers alternating with wells. In this case, the barriers can include both transparent regions, which are configured to reduce an amount of radiation that is absorbed in the layer, and higher conductive regions, which are configured to keep the voltage drop across the layer within a desired range.

A semiconductor device that includes transistors having the same polarity consumes less power and can prevent a decrease in amplitude of a potential output. The semiconductor device includes a first wiring having a first potential, a second wiring having a second potential, a third wiring having a third potential, a first transistor and a second transistor having the same polarity, and a plurality of third transistors for selecting supply of the first potential to gates of the first transistor and the second transistor or supply of the third potential to the gates of the first transistor and the second transistor and for selecting whether to supply one potential to drain terminals of the first transistor and the second transistor. A source terminal of the first transistor is connected to the second wiring, and a source terminal of the second transistor is connected to the third wiring.

A semiconductor device which shifts a low-level signal is provided. In an example, a first transistor including a first terminal electrically connected to a first wiring and a second terminal electrically connected to a second wiring, a second transistor including a first terminal electrically connected to a third wiring and a second terminal electrically connected to the second wiring, a third transistor including a first terminal electrically connected to a fourth wiring and a second terminal electrically connected to a gate of the second transistor, a fourth transistor including a first terminal electrically connected to a fifth wiring, a second terminal electrically connected to a gate of the third transistor, and a gate electrically connected to a sixth wiring, and a first switch including a first terminal electrically connected to the third wiring and a second terminal electrically connected to a gate of the first transistor are included.

A semiconductor integrated circuit includes: a main-interconnect to which supply voltage or reference voltage is applied; a plurality of sub-interconnects; a plurality of circuit cells configured to be connected to the plurality of sub-interconnects; a power supply switch cell configured to control, in accordance with an input control signal, connection and disconnection between the main-interconnect and the sub-interconnect to which a predetermined one of the circuit cells is connected, of the plurality of sub-interconnects; and an auxiliary interconnect configured to connect the plurality of sub-interconnects to each other.

An isolator circuit capable of two-way electrical disconnection and a semiconductor device including the isolator circuit are provided. A data holding portion is provided in an isolator circuit without the need for additional provision of a data holding portion outside the isolator circuit, and data which is to be input to a logic circuit that is in an off state at this moment is stored in the data holding portion. The data holding portion may be formed using a transistor with small off-state current and a buffer. The buffer can include an inverter circuit and a clocked inverter circuit.

Disclosed herein is a device that includes first and second buffer circuits connected to a data terminal and a first control circuit controlling the first and second buffer circuits. The first control circuit receives n pairs of first and second internal data signals complementary to each other from 2n input signal lines and outputs a pair of third and fourth internal data signals complementary to each other to first and second output signal lines, where n is a natural number more than one. The first and second buffer circuits are controlled based on the third and fourth internal data signals such that one of the first and second buffer circuits turns on and the other of the first and second buffer circuits turns off.

A semiconductor device includes an internal circuit, a power supply control circuit which controls supply of a power supply to the internal circuit upon receipt of a first control signal, and a control signal generation circuit which outputs the first control signal upon receipt of a second control signal. The control signal generation circuit does not deactivate the first control signal when an inactive period of the second control signal is equal to or less than a first period and deactivates the first control signal when the inactive period of the second control signal is more than the first period.

An embodiment of this invention uses a massive parallel interconnect fabric (MPIF) at the flipped interface of a core die substrate (having the core logic blocks) and a context die (used for in circuit programming/context/customization of the core die substrate), to produce ASIC-like density and FPGA-like flexibility/programmability, while reducing the time and cost for development and going from prototyping to production, reducing cost per die, reducing or eliminating NRE, and increasing performance. Other embodiments of this invention enable debugging complex SoC through large contact points provided through the MPIF, provide for multi-platform functionality, and enable incorporating FGPA core in ASIC platform through the MPIF. Various examples are also given for different implementations.

A semiconductor integrated circuit including: a circuit block having an internal voltage line; an annular rail line forming a closed annular line around the circuit block and supplied with one of a power supply voltage and a reference voltage; and a plurality of switch blocks arranged around the circuit block along the annular rail line, the plurality of switch blocks each including a voltage line segment forming a part of the annular rail line and a switch for controlling connection and disconnection between the voltage line segment and the internal voltage line.

An integrated structure of compound semiconductor devices is disclosed. The integrated structure comprises from bottom to top a substrate, a first epitaxial layer, an etching-stop layer, a second epitaxial layer, a sub-collector layer, a collector layer, a base layer, and an emitter layer, in which the first epitaxial layer is a p-type doped layer, the second epitaxial layer is an n-type graded doping layer with a gradually increased or decreased doping concentration, and the sub-collector layer is an n-type doped layer. The integrated structure can be used to form an HBT, a varactor, or an MESFET.