Linkage Tree Genetic Algorithm (LTGA) is an effective Evolutionary Algorithm (EA) to solve complex problems using the linkage information between problem variables. LTGA performs well in various kinds of single-task optimization and yields promising results in comparison with the canonical genetic algorithm. However, LTGA is an unsuitable method for dealing with multi-task optimization problems. On the other hand, Multifactorial Optimization (MFO) can simultaneously solve independent optimization problems, which are encoded in a unified representation to take advantage of the process of knowledge transfer. In this paper, we introduce Multifactorial Linkage Tree Genetic Algorithm (MF-LTGA) by combining the main features of both LTGA and MFO. MF-LTGA is able to tackle multiple optimization tasks at the same time, each task learns the dependency between problem variables from the shared representation. This knowledge serves to determine the high-quality partial solutions for supporting other tasks in exploring the search space. Moreover, MF-LTGA speeds up convergence because of knowledge transfer of relevant problems. We demonstrate the effectiveness of the proposed algorithm on two benchmark problems: Clustered Shortest-Path Tree Problem and Deceptive Trap Function. In comparison to LTGA and existing methods, MF-LTGA outperforms in quality of the solution or in computation time.

Recently, the Edge Computing paradigm has gained significant popularity both in industry and academia. Researchers now increasingly target to improve performance and reduce energy consumption of such devices. Some recent efforts focus on using emerging RRAM technologies for improving energy efficiency, thanks to their no leakage property and high integration density. As the complexity and dynamism of applications supported by such devices escalate, it has become difficult to maintain ideal performance by static RRAM controllers. Machine Learning provides a promising solution for this, and hence, this work focuses on extending such controllers to allow dynamic parameter updates. In this work we propose an Adaptive RRAM Variability-Aware Controller, AVAC, which periodically updates Wait Buffer and batch sizes using on-the-fly learning models and gradient ascent. AVAC allows Edge devices to adapt to different applications and their stages, to improve computation performance and reduce energy consumption. Simulations demonstrate that the proposed model can provide up to 29% increase in performance and 19% decrease in energy, compared to static controllers, using traces of real-life healthcare applications on a Raspberry-Pi based Edge deployment.

Homomorphic encryption (HE) allows direct computations on encrypted data. Despite numerous research efforts, the practicality of HE schemes remains to be demonstrated. In this regard, the enormous size of ciphertexts involved in HE computations degrades computational efficiency. Near-memory Processing (NMP) and Computing-in-memory (CiM) - paradigms where computation is done within the memory boundaries - represent architectural solutions for reducing latency and energy associated with data transfers in data-intensive applications such as HE. This paper introduces CiM-HE, a Computing-in-memory (CiM) architecture that can support operations for the B/FV scheme, a somewhat homomorphic encryption scheme for general computation. CiM-HE hardware consists of customized peripherals such as sense amplifiers, adders, bit-shifters, and sequencing circuits. The peripherals are based on CMOS technology, and could support computations with memory cells of different technologies. Circuit-level simulations are used to evaluate our CiM-HE framework assuming a 6T-SRAM memory. We compare our CiM-HE implementation against (i) two optimized CPU HE implementations, and (ii) an FPGA-based HE accelerator implementation. When compared to a CPU solution, CiM-HE obtains speedups between 4.6x and 9.1x, and energy savings between 266.4x and 532.8x for homomorphic multiplications (the most expensive HE operation). Also, a set of four end-to-end tasks, i.e., mean, variance, linear regression, and inference are up to 1.1x, 7.7x, 7.1x, and 7.5x faster (and 301.1x, 404.6x, 532.3x, and 532.8x more energy efficient). Compared to CPU-based HE in a previous work, CiM-HE obtain 14.3x speed-up and >2600x energy savings. Finally, our design offers 2.2x speed-up with 88.1x energy savings compared to a state-of-the-art FPGA-based accelerator.

If you’re looking to grow your business online, it’s time to start setting up different types of website conversions to help your company succeed. Whether you’re looking to earn more email subscribers or sell more products, you can set conversion goals that grow your business. On this page, we’ll discuss what a conversion goal is, […]

The post Going Beyond Sales: 7 Types of Website Conversions to Optimize for on Your Website appeared first on WebFX Blog.

By Adam Liptak The New York Times Company…

In one embodiment, a plurality of objects associated with a dataset and a specified number of nearest objects to be identified are received. The received objects are sorted in a structured format. Further, a key object and a number of adjacent objects corresponding to the key object are selected from the sorted plurality of objects, wherein the number of adjacent objects is selected based on the specified number of nearest objects to be identified. Furthermore, distances between the key object and the number of adjacent objects are determined to identify the specified number of nearest objects, wherein the distances are determined until the specified number of nearest objects is identified. Based on the determined distances, the specified number of nearest objects in the dataset is identified for data analysis.

Disclosed is a method for preparing optically pure (+)-ambrisentan and (+)-darusentan, comprising: firstly catalyzing the asymmetric epoxidation of a β-unsaturated alkene using a chiral ketone derived from fructose or a hydrate thereof as a catalyst, and then subjecting the product to an epoxy compound ring-opening reaction and substitution reaction successively to obtain optically pure (+)-ambrisentan and (+)-darusentan.

This optical glass contains, as represented by mol %, 18 to 38% P2O5, 0 to 15% B2O3, 23 to 40% P2O5+B2O3, 4 to 28% Nb2O5, 0 to 20% TiO2, 10 to 30% Nb2O5+TiO2, 15 to 35% Li2O+Na2O+K2O, and 21 to 38% ZnO, but does not contain BaO, WO3, Bi2O3 or SiO2, and the ratio of the mol % of ZnO to the total mol % of Li2O+Na2O+K2O (i.e., ZnO/(Li2O+Na2O+K2O)) is 0.8 to 2.0.

A highly refractive and highly transparent optical glass is provided. The use of such a glass, optical elements and processes for producing the glass or the optical elements are also provided.

Provided is an optical glass that has desired optical properties, superior resistance to devitrification, and superior mass productivity. An optical glass is made of a SiO2—Nb2O5—TiO2-based glass having a refractive index (nd) of 1.75 to 1.95 and an Abbe's number (νd) of 15 to 35 and has an operation temperature range (ΔT=(temperature at 100.5 poise)−(liquidus temperature)) of 20° C. or more. The optical glass preferably contains, in percent by mass, 15% to 45% SiO2, 15% to 40% (but excluding 40%) Nb2O5 and 1% to 30% TiO2 as glass components.

An optical glass including B3+, La3+ and Nb5+ as cationic components constituting the glass, wherein the optical glass satisfies the following expressions represented in cation percentages: 10 cat. %≦B3+≦50 cat. %;40 cat. %≦La3+≦65 cat. %;0 cat. %≦Nb5+≦40 cat. %;80 cat. %≦(total amount of B3++La3++Nb5+)≦100 cat. %; and0 cat. %≦Si4+≦10 cat. %;0 cat. %≦Ge4+≦5 cat. %;0 cat. %≦Mg2+≦5 cat. %;0 cat. %≦Ba2+≦10 cat. %;0 cat. %≦Ca2+≦10 cat. %;0 cat. %≦Sr2+≦10 cat. %;0 cat. %≦Zn2+≦20 cat. %;0 cat. %≦W6+≦5 cat. %;0 cat. %≦Zr4+≦5 cat. %;0 cat. %≦Ti4+≦5 cat. %;0 cat. %≦Bi3+≦5 cat. %;0 cat. %≦Ta5+≦10 cat. %;0 cat. %≦(total amount of Y3++Gd3+)≦20 cat. %; and0 cat. %≦(total amount of Yb3++Lu3+)≦10 cat. %.

An adsorption process is disclosed for removal of acid gas contaminants from a liquid or gas which comprises providing an activated alumina adsorbent which is impregnated with a compound selected from the group consisting of one or more alkali metal compounds, one or more alkaline earth metal compounds, or a mixture of such compounds; contacting the liquid or gas containing acid gas contaminants with the activated alumina adsorbent to adsorb enough acid gas contaminant in the liquid or gas to lower the contaminant content of the liquid or gas, the alumina adsorbent being formed from agglomerated calcined alumina powder and provided with a mercury pore volume of pores greater than 500 angstroms at least 0.10 cc/g.

A process according to various approaches includes flushing an intermediate transfer line between a raffinate stream transfer line and a desorbent stream transfer line away from the adsorptive separation chamber to remove residual fluid including desorbent from intermediate transfer line. The process may include directing the residual fluid flushed from the intermediate transfer line to a recycle stream to introduce the residual fluid into the adsorptive separation chamber.

A nanostructure, an optical device including the nanostructure, and methods of manufacturing the nanostructure and the optical device. A method of manufacturing a nanostructure may include forming a block copolymer template layer and a precursor pattern of metal coupled to the block copolymer template layer on a graphene layer, and forming a metal nanopattern on the graphene layer by removing the block copolymer template layer and reducing the precursor pattern.

In certain embodiments novel nanoparticles (nanowontons) are provided that are suitable for multimodal imaging and/or therapy. In one embodiment, the nanoparticles include a first biocompatible (e.g., gold) layer, an inner core layer (e.g., a non-biocompatible material), and a biocompatible (e.g., gold) layer. The first gold layer includes a concave surface that forms a first outer surface of the layered nanoparticle. The second gold layer includes a convex surface that forms a second outer surface of the layered nanoparticle. The first and second gold layers encapsulate the inner core material layer. Methods of fabricating such nanoparticles are also provided.

Described herein are devices, compositions, and methods for improving color discernment.

A method, system and computer program product for intelligently responding to hardware failures so as to optimize system performance. An administrative server monitors the utilization of the hardware as well as the software components running on the hardware to assess a context of the software components running on the hardware. Upon detecting a hardware failure, the administrative server analyzes the hardware failure to determine the type of hardware failure and analyzes the properties of the workload running on the failed hardware. The administrative server then responds to the detected hardware failure based on various factors, including the type of the hardware failure, the properties of the workload running on the failed hardware and the context of the software running on the failed hardware. In this manner, by taking into consideration such factors in responding to the detected hardware failure, a more intelligent response is provided that optimizes system performance.

A method includes determining a read threshold voltage corresponding to a group of storage elements in a non-volatile memory that includes a three-dimensional (3D) memory of a data storage device. The method also includes determining an error metric corresponding to data read from the group of storage elements using the read threshold voltage. The method includes comparing the read threshold voltage and the error metric to one or more criteria corresponding to a corrupting event.

A packet transmission/reception apparatus and method is provided. The packet transmission method of the present invention includes acquiring a source payload including partial source symbols from a source block, generating a source packet including the source payload and an identifier (ID) of the source payload, generating a repair packet including a repair payload corresponding to the source payload and an ID of the repair payload, generating a Forward Error Correction (FEC) packet block including the source and repair packets, and transmitting the FEC packet block. The source payload ID includes a source payload sequence number incrementing by 1 per source packet. The packet transmission/reception method of the present invention is advantageous in improving error correction capability and network resource utilization efficiency.

The present technique relates to a reception device and a reception method which can improve equalization performance. An equalization processing unit has a time domain equalization unit which equalizes a received signal in a time domain and a frequency domain equalization unit which is provided in parallel to the time domain equalization unit and which equalizes the received signal in a frequency domain, and performs control of switching between the time domain equalization unit and the frequency domain equalization unit. The present technique can be applied to, for example, equalize a signal of data transmitted by way of single carrier transmission or data transmitted by way of multicarrier transmission.

A communication device includes a storage unit to store quotients and remainders associated with multiplication values obtained by multiplying a specified integer number, which is expressed in a form of (2β+α) where β is a positive integer number and α is a positive integer number other than integral multiples of 2, respectively, the quotients and the remainders being obtained by dividing the multiplication values by 2β, respectively, a first unit to divide a dividend by 2βand calculate a quotient and a remainder, a second unit to obtain a quotient, which corresponds to the remainder from the storage unit, and a third unit to determine that the data length of the packet data is normal, when a combination of the quotient and the remainder calculated by the first unit is in the storage unit.

The present disclosure relates to a thermally resistant optical siloxane resin composition including siloxane containing photo-cationically polymerizable epoxy group, a photo initiator, and an antioxidant.

An optical component and an electrical board that have a low coefficient of linear expansion and small mold shrinkage, a method for producing the optical component, and a method for producing the electronic board are provided. An optical component includes a polymer having a repeating structural unit represented by general formula (1) where R1 and R2 each independently represent —H or —CH3; m and n each independently represent an integer in the range of 0 to 3; asterisk denotes a dangling bond that bonds to one of Xa and Xb; and —H bonds to the other one of Xa and Xb.

A heat-resistant cured product is efficiently produced by obtaining a semi-cured product where a curable resin composition containing a (meth)acrylate monomer, a non-conjugated vinylidene group-containing compound and a thermal radical-polymerization initiator is processed by at least one of photoirradiation and heating to give a semi-cured product having a complex viscosity of from 105 to 108 mPa·s at 25° C. and at a frequency of 10 Hz; and putting the semi-cured product in a forming die for pressure formation therein, and heating it therein for thermal polymerization to give a cured product.

A bus interconnect interfaces a host system to a radio frequency (RF) generator that is coupled to a plasma chamber. The bus interconnect includes a first set of host ports, which are used to provide a power component setting and a frequency component setting to the RF generator. The ports of the first set of host ports are used to receive distinct variables that change over time. The bus interconnect further includes a second set of generator ports used to send a power read back value and a frequency read back value to the host system. The bus interconnect includes a sampler circuit integrated with the host system. The sampler circuit is configured to sample signals at the ports of the first set at selected clock edges to capture operating state data of the plasma chamber and the RF generator.

Techniques for adaptive thread scheduling on a plurality of cores for reducing system energy are described. In one embodiment, a thread scheduler receives leakage current information associated with the plurality of cores. The leakage current information is employed to schedule a thread on one of the plurality of cores to reduce system energy usage. On chip calibration of the sensors is also described.

An optically active bisbenzyl compound or a racemic bisbenzyl compound represented by formula (2) that has axial chirality: where: R1 represents a halogen, or an optionally substituted: linear, branched, or cyclic C1-8 alkyl, C2-8 alkenyl, C2-8 alkynyl, C6-14 aryl, C3-8 heteroaryl, linear, branched, or cyclic C1-8 alkoxy, or C7-16 aralkyl;R21 each independently represents hydrogen, halogen, nitro, or an optionally substituted: linear, branched, or cyclic C1-8 alkyl, C2-8 alkenyl, C2-8 alkynyl, C6-14 aryl, linear, branched, or cyclic C1-8 alkoxy, or a C7-16 aralkyl;R3 represents hydrogen, or an optionally substituted: C6-14 aryl, a C3-8 heteroaryl, or a C7-16 aralkyl; andY2 represents a halogen, or an optionally substituted: C1-8 alkylsulfonyloxy, C6-14 arylsulfonyloxy, or C7-16 aralkylsulfonyloxy.

Methods and systems for optimizing generation of natively executable code from non-native binary code are disclosed. One method includes receiving a source file including binary code configured for execution according to a non-native instruction set architecture. The method also includes translating one or more code blocks included in the executable binary code to source code, and applying an optimizing algorithm to instructions in the one or more code blocks. The optimizing algorithm is selected to reduce a number of memory address translations performed when translating the source code to native executable binary code, thereby resulting in one or more optimized code blocks. The method further includes compiling the source code to generate an output file comprising natively executable binary code including the one or more optimized code blocks.

An adaptable integrated circuit is disclosed having a plurality of heterogeneous computational elements coupled to an interconnection network. The interconnection network changes interconnections between the plurality of heterogeneous computational elements in response to configuration information. A first group of computational elements is allocated to form a first version of a functional unit to perform a first function by changing interconnections in the interconnection network between the first group of heterogeneous computational elements. A second group of computational elements is allocated to form a second version of a functional unit to perform the first function by changing interconnections in the interconnection network between the second group of heterogeneous computational elements. One or more of the first or second group of heterogeneous computational elements are reallocated to perform a second function by changing the interconnections between the one or more of the first or second group of heterogeneous computational elements.

A data processing system arranged for receiving over a network, according to a data transfer protocol, data directed to any of a plurality of destination identities, the data processing system comprising: data storage for storing data received over the network; and a first processing arrangement for performing processing in accordance with the data transfer protocol on received data in the data storage, for making the received data available to respective destination identities; and a response former arranged for: receiving a message requesting a response indicating the availability of received data to each of a group of destination identities; and forming such a response; wherein the system is arranged to, in dependence on receiving the said message.

An information processing system, computer readable storage medium, and method for automatically generating human readable and meaningful documentation for one or more source code files. A processor of the information processing system receives one or more source code files containing source code artifacts (SCA) and infers semantics therefrom based on predefined rules. The processor, based on the inferred semantics, extracts documentation from another source code file. The extracted documentation and the inferred semantics are used to generate new human readable and meaningful documentation for the SCA, such new documentation being previously missing from the SCA. The generated new documentation is included with the SCA in one or more source code files.

The present invention relates to a method for compiling code for a multi-core processor, comprising: detecting and optimizing a loop, partitioning the loop into partitions executable and mappable on physical hardware with optimal instruction level parallelism, optimizing the loop iterations and/or loop counter for ideal mapping on hardware, chaining the loop partitions generating a list representing the execution sequence of the partitions.

In one embodiment, an optimization hint may be included in a business process flow. An executable process may be generated from the business process flow where the optimization hint is included in the executable process. While executing the executable process, the runtime engine encounters an optimization hint and determines an optimization to perform. The optimization hint may be related to an aspect of a business process being orchestrated by the business process flow. The optimization is then performed while executing the executable process. For example, the runtime engine may start pre-processing the branch while the condition is being evaluated. If the condition evaluates such that the pre-processed branch should be executed, then the runtime engine has already started processing of that branch. The processing is thus optimized in that the runtime engine is not sitting idle while waiting for the condition to be evaluated.

The present invention is directed to a novel compound, but-2-enoic acid 1-ethyl-2-methyl-propyl ester, and a method of improving, enhancing or modifying a fragrance formulation through the addition of an olfactory acceptable amount of but-2-enoic acid 1-ethyl-2-methyl-propyl ester.

The present invention is directed to a novel compound, but-2-enoic acid 1,2-dimethyl-butyl ester, and a method of improving, enhancing or modifying a fragrance formulation through the addition of an olfactory acceptable amount of but-2-enoic acid 1,2-dimethyl-butyl ester.

An optically active bicyclic compound is efficiently produced by optical resolution using an optically active amine.

A method of patterning a plurality of layers of a work piece in a series of writing cycles in one or a plurality of write machines, the workpiece being deviced to have a number of N layers and layers of the workpiece having one or a plurality of boundary condition(s) for pattern position, the method comprising the steps of: determining the boundary conditions of layers 1 to N, calculating deviations due to the boundary conditions and calculating a compensation for the deviation of the first transformation added with the assigned part of the deviation due to the boundary conditions.

Methods are provided to facilitate automated creation and management of design rule checking or DRC waiver descriptions. Embodiments include receiving a plurality of first checksums corresponding to respective first geometric element violations waived in association with a block of an integrated circuit design, the first checksums being based on a first version of at least one design verification rule and/or of the block, receiving a second checksum corresponding to a second geometric element violation associated with the block, the second checksum being based on a second version of the design verification rule and/or of the block, determining whether the second checksum corresponds to at least one of the first checksums, and, if the second checksum does not correspond to at least one first checksum, generating a waiver request for the second geometric element error.

A method of asymmetric asynchronous decoupling of capacitors in an integrated circuit design is provided for faster simulation by circuit simulators, e.g. FastSPICE circuit simulators. This method includes removing a coupling capacitor from a list, which includes coupling capacitors that capacitively couple two nets in the design. The two nets have capacitances C1 and C2, and at least one of capacitances C1 and C2 exceeds a threshold. The coupling capacitor has capacitance Cc. When coupling capacitance Cc is low and only one of capacitances C1 and C2 has a low capacitance, then a forward capacitance can be used at whichever of the two nets has the low capacitance and a lump capacitance can be used at the other net for simulation. When coupling capacitance Cc is low and both of capacitances C1 and C2 have high capacitances, then lump capacitances can be used at the two nets for the simulation.

A method for designing a transformer in an integrated circuit includes receiving one or more desired characteristics of the transformer from user input and iteratively determining a design solution for the transformer through one or more simulations and modifications using a rule-set. The method combines the one or more desired characteristics with other preset characteristics of the transformer or the integrated circuit. A first model of the transformer is defined with typical load impedances and simulated having the combined characteristics to determine performance. Results of the simulation are processed to calculate performance with the load impedances specified by the user. The results are further processed to obtain a mathematical model that includes tuning capacitors. The first and subsequent models are modified by drawing on a rule-set of expert knowledge relating to general dependency of at least one design criterion, such as a physical, geometrical or performance characteristic, with another design criterion.

Some example embodiments include a computer-implemented method for designing an integrated circuit. The computer-implemented method includes receiving a hierarchical network design for the integrated circuit, wherein the hierarchical design comprises a number of components that are coupled together. The computer-implemented method includes detecting that a component of the number of components has at least one of failed timing and incomplete timing based on a problem that comprises at least one of a missing assertion, one or more missing latches, a source driver having an input source slew that is greater than a source slew limit threshold, and a sink having an input sink slew that is greater than a sink slew limit threshold. The computer-implemented method includes replacing the component with a different component that is independent of the problem and testing others components of the number of components based on the different component.

A method, an apparatus, and a computer program product for wireless communication are provided. The apparatus generates a plurality of interconnect patterns for a set of longitudinal channels that are occupied by horizontal interconnects. Each interconnect pattern may be different from the other interconnect patterns. Each interconnect pattern may define relative locations for the set of horizontal interconnects and gap channels. Highest crosstalk is determined for each of the interconnect patterns and the interconnect pattern with the minimum highest crosstalk is selected as a preferred pattern. The highest crosstalk may comprise far-end crosstalk or near-end crosstalk and may be calculated for a range of frequencies or for a plurality of frequencies. The crosstalk may be calculated by modeling the interconnects as transmission lines.

An apparatus and an article of manufacture for controlling a voice site using a haptic input modality include validating a haptic input from an instrument capable of accessing a voice site, processing the haptic input on a server to determine a voice site command corresponding to the haptic input, and processing the voice site command at the server to control an interaction with the voice site.

The present invention is based on the finding that parameters including: a first set of parameters of a representation of a first portion of an original signal and a second set of parameters of a representation of a second portion of the original signal can be efficiently encoded when the parameters are arranged in a first sequence of tuples and a second sequence of tuples. The first sequence of tuples includes tuples of parameters having two parameters from a single portion of the original signal and the second sequence of tuples includes tuples of parameters having one parameter from the first portion and one parameter from the second portion of the original signal. A bit estimator estimates the number of necessary bits to encode the first and the second sequence of tuples. Only the sequence of tuples, which results in the lower number of bits, is encoded.

Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for adapting user interfaces for devices that include widescreen displays. In one aspect, a method includes determining a size characteristic of a display of a mobile device, determining a size characteristic of content that is to be displayed on the display, and comparing the size characteristic of the content to the size characteristic of the display. The method also includes selecting one or more controls to display in a portion of the display that is not to be used to display the content based on comparing the size characteristic of the content to the size characteristic of the display, displaying the content, and displaying the selected controls in a portion of the display that is not used to display the content.

A method of transferring data using a Trivial File Transport Protocol (TFTP) includes sending first request packet from client to server, first request packet requesting that first file be transferred; transferring first file according to first request packet if first acknowledgement packet is received at client from server indicating that server can accommodate request of first request packet; sending second request packet from client to the server if transfer of first file does not complete successfully, the second request packet including TFTP option indicating that transfer of first file be retried beginning at first block after final block that was successfully transferred in response to first request packet; and retrying transfer of first file according to second request packet if second acknowledgement packet is received at client from server indicating that server can accommodate request of second request packet.

Accessory for a laptop computer with LCD display which is connected to the laptop serial communications port and optically transmits data to a portable information device, such as a wristwatch designed to receive data as sequential pulses of light. The accessory includes a microcomputer with an RC timebase which is calibrated each time it is used by a special internal program, so that the input baud rate to the accessory matches the communications baud rate of the data received from the laptop. The internal program also permits selection of an output baud rate for the optically transmitted data.

A method, a system and a computer program product for enhancing a cache back invalidation policy by utilizing least recently used (LRU) bits and presence bits in selecting cache-lines for eviction. A cache back invalidation (CBI) utility evicts cache-lines by using presence bits to avoid replacing a cache-line in a lower level cache that is also present in a higher level cache. Furthermore, the CBI utility selects the cache-line for eviction from an LRU group. The CBI utility ensures that dormant cache-lines in the higher level caches do not retain corresponding presence bits set in the lower level caches by unsetting the presence bits in the lower level cache when a line is replaced in the higher level cache. Additionally, when a processor core becomes idle, the CBI utility invalidates the corresponding higher level cache by unsetting the corresponding presence bits in the lower level cache.

Techniques for handling version information using a copy engine. In one embodiment, an apparatus comprises a copy engine configured to perform one or more operations associated with a block memory operation in response to a command. Examples of block memory operations may include copy, clear, move, and/or compress operations. In one embodiment, the copy engine is configured to handle version information associated with the block memory operation based on the command. The one or more operations may include operating on data in a cache and/or modifying entries in a memory. In one embodiment, the copy engine is configured to compare version information in the command with stored version information. The copy engine may overwrite or preserve version information based on the command. The copy engine may be a coprocessing element. The copy engine may be configured to maintain coherency with other copy engines and/or processing elements.

An optical backup apparatus is provided and includes an optical storage device, an interface module to connect with at least one type of external storage medium, and a control unit to back up data from the external storage medium to the optical storage device in response to an external remote control operation.