A film-forming device and a film forming method are provided. The film-forming device is configured to form an organic material thin film at a target region of a substrate and includes a gas supplying mechanism and a gas injection mechanism. The gas supplying mechanism is configured to import a mixture gas of organic material steam and an inert gas into the gas injection mechanism. The gas injection mechanism is configured to inject the mixture gas from the gas supplying mechanism onto the target region of the substrate.

A method for producing a porous polyimide film comprises: forming a first un-burned composite film wherein the first film is formed on a substrate using a first varnish that contains (A1) a polyamide acid or a polyimide and (B1) fine particles at a volume ratio (A1):(B1) of from 19:81 to 45:65; forming a second un-burned composite film wherein the second film is formed on the first film using a second varnish that contains (A2) a polyamide acid or a polyimide and (B2) fine particles at a volume ratio (A2):(B2) of from 20:80 to 50:50 and has a lower fine particle content ratio than the first varnish; burning wherein an un-burned composite film composed of the first film and the second film is burned, thereby obtaining a polyimide-fine particle composite film; and a fine particle removal step wherein the fine particles are removed from the polyimide-fine particle composite film.

The invention provides a luminaire for illuminating a road, comprising a light source (10), a reflector arrangement (12) defining a light entrance window (18) at the top to which light is supplied by the light source (10) and a larger light exit window (20) at the bottom, and an optical plate (22) over the light exit window (20). The optical plate (22) comprises an array of elongate prisms which each extend in a side-to-side direction corresponding to the width direction of the road. The reflector (12) is primarily responsible for control of the light output in the road width direction and the optical plate (22) is primarily responsible for control of the light output in the road length direction.

A light emitting diode (LED) module for a light fixture includes a substrate with an upper surface and a lower surface. Various pressure multiplying pads are integrally connected to the lower surface, and each pressure multiplying pad extends away from the lower surface. LEDs are attached to the upper surface, along with a set of conductive lines so that each conductive line electrically connects a corresponding LED to a power inputs. Each of the pressure multiplying pads may be positioned opposite a corresponding LED. A flexible lens cover may cover the upper surface and the LEDs, while leaving the lower surface and pressure multiplying pads exposed so that the pads can contact a heat sink of the light fixture.

A light emitting module includes a circuit board, a light emitting device mounted on the circuit board, and a lens dispersing light emitted from the light emitting device. The lens includes a lower surface formed with a concave section defining a light incident surface through which light enters the lens, an upper surface through which light exits the lens, and legs coupled to the circuit board and disposed farther outside the lens than an area of the upper surface. The light emitting device is disposed within the concave section of the lens.

light emitting device includes: a light emitting element including a first electrode and a second electrode; a base equipped with a first conductive member and a second conductive member; a first bonding member electrically connecting the first electrode and the first conductive member, and a second bonding member electrically connecting the second electrode and the second conductive member; and one or more light reflecting members covering at least a part of the first conductive member and the second conductive member. The one or more light reflecting members are disposed in contact with the first bonding member and the second bonding member while being away from the light emitting element.

The present invention is related to a lighting device (100, 200, 300) and to a method for manufacturing such lighting device (100, 200, 300). A template (102) is provided having cavities (104) distributed across the template (102). The cavities (104) define mounting positions for a plurality of light source packages (110) each comprising a light source (112). The shape of the cavities matches the shape of the light source packages (110) such that the light source packages (110) have a limited number of possible mounting configurations in the cavities (104). Subsequently electrical conductors (122) are applied on a top surface of the template (102) for contacting electrodes of the light source packages (110). The light source packages (110, 208, 300) or the plurality of cavities comprise a reflective bottom layer (132, 220) and a light emitting surface of the light source (112, 210) faces the reflective bottom layer (132, 220).

Disclosed are an LED illumination apparatus and its manufacturing method. A metal sheet is stamped to form a conductive plate with 3D space, and the conductive plate includes an illumination circuit, and a support frame for supporting the conductive plate to form different types of illumination apparatuses. The support frame is provided for supporting and fixing the conductive plate to facilitate the conductive plate to form a 3D curved surface, and an LED chip soldering point protection mechanism is provided for protecting each LED chip soldering point, so that the illumination apparatus is applicable for mass production to improve the yield rate and meet the high heat dissipation efficiency, large-range illumination, material saving, lightweight and/or environmental protection requirements.

A light fixture includes a sealed path between a group of LED modules and a sensor cavity. The light fixture performs self-diagnosis and implements corrective measures upon detection of one or more environmental condition changes in the sealed path. In response to detecting an environmental condition change, the light fixture will automatically implement a corrective measure.

A method for providing assistance in aiming of one or more illumination devices in an area may include, by a processor, receiving photometric data for an area, and using the photometric data to determine an aiming vector for the illumination device. the area may include the illumination device. the method may further include receiving, from an orientation sensor module of the illumination device, orientation data for the illumination device, and using the orientation data and the aiming vector to determine if there is an error in the aiming of the illumination device.

A light fixture includes a housing comprising a body portion with an opening at a first end, a power supply at an opposing second end, and a heat sink comprising a plurality of fins between the opening and the power supply. A mating surface is positioned proximate to the opening. The mating surface includes a set of landing pad areas and a set of open areas. The fixture also includes a set of light emitting diode (LED) modules, each of which is positioned in the opening and secured to a landing pad area of the mating surface. The LED modules are arranged so that the plurality of open areas remain open to the atmosphere and provide an air path to and from the heat sink.

A light fixture includes one or more of light emitting diode (LED) modules. Each of the LED modules may include a substrate holding a plurality of LEDs, and a printed circuit board connected to the plurality of LEDs. Each of the LED modules may also include a flexible lens cover including a plurality of lenses, each positioned to be located over one of the LEDs. The flexible lens cover may include a side sealing structure configured to interface with the substrate and seal the lens cover to the substrate.

The present invention provides an atomizing fragrance lamp, comprising a shell, a circuit board, a light-emitting assembly, an atomizing assembly and a support base, wherein the shell comprises an upper chamber, a lower chamber and a top cover; two contact points connected with the circuit board extend from the bottom of the shell; the top cover is provided with a mist outlet; the atomizing assembly is mounted in the lower chamber together with the circuit board and electrically connected with the circuit board; and a color lamp of the light-emitting assembly is disposed in the upper chamber, extends out of the top cover through the mist outlet and is electrically connected with the circuit board. The atomizing fragrance lamp provided by the present invention is more compact in structure, attractive in appearance, small in size, convenient to carry, and meets the requirements of more people.

A planar illumination apparatus according to an embodiment includes a light source and a light guide plate. The light source includes a light emitting diode and a wavelength conversion material that is excited by light emitted from the light emitting diode so as to emit light, and emits white light. The light guide plate includes an incident end surface on which the light source is disposed, and an emission surface that emits light incident from the incident end surface. The light guide plate is provided with a light scattering unit on at least one of the emission surface and a rear surface opposed to the emission surface. The light scattering unit mainly scatters light emitted from the light emitting diode than light emitted from the wavelength conversion material.

An illumination device includes a light source configured to emit, during operation, light with a prevalent direction of propagation different from a direction of an optical axis of the illumination device; and an optical coupler including a transparent material, the optical coupler having an input aperture, an exit aperture and a first side surface and a second side surface arranged between the input aperture and the exit aperture, the exit aperture being centered on the optical axis of the illumination device. The optical coupler receives the emitted light through the input aperture from the light source. Further, the first side surface and the second side surface redirect the received light via total internal reflection (TIR) to the exit aperture. Additionally, the redirected light is issued through the exit aperture.

An apparatus for optimizing a skewed join is described herein. The apparatus includes logic, at least partially including hardware logic, to determine that a dataset for the skewed join comprises a skewed key that does not fit in memory. The apparatus also includes logic to model the skewed join as a queue. The apparatus also includes logic to estimate a cost of the skewed join based on the modeled queue. The apparatus evaluates different join techniques, and partitioning strategies for the skewed join, and chooses the plan with the lowest cost.

A system provides search results in response to a search query. The system includes a query understanding module configured to receive the search query and output a processed search query based on the search query. The search query includes one or more words and the processed search query selectively includes tags assigned to the one or more words. The system includes a fuzzy knowledge module configured to receive the processed search query, generate a set of candidate tags for selected ones of the words in the search query, and selectively validate the candidate tags. The system is configured to provide the search results to a user device based in part on the candidate tags generated and validated by the fuzzy knowledge module.

Techniques are described for automatic interval metadata determination for intermittent time series data. In one example, a method for determining intermittent time series interval metadata includes detecting one or more time variables in a time series data set. The method further includes determining whether the one or more time variables are intermittently regular. The method further includes determining one or more respective time intervals for the one or more time variables. The method further includes determining the parameters of intermittency for the one or more time variables. The method further includes generating an output comprising information about the one or more time variables based on the one or more respective time intervals and the parameters of intermittency for the time variable.

Embodiments of the present disclosure provide a method and an apparatus for determining a similar document set to a target document from a plurality of documents. Each of the multiple documents and the target document may include a plurality of words, and each of words corresponds to a different integer. The method comprises: for each document among the plurality of documents and the target document, obtaining a set of integers associated with a document based on a set of words associated with the document, converting the set of integers associated with the document into a vector with a same dimension based on a predefined conversion rule; and determining the similar document set based on differences between the corresponding vectors for the multiple documents and the vector for the target document.

Systems and methods for using pressure swing adsorption to separate and/or capture resulting emissions are provided. A stream of recycled exhaust gas is passed into a first swing adsorption reactor comprising a first adsorbent material which adsorbs CO2. An enriched N2 stream is recovered from a forward end of the first swing adsorption reactor. The pressure in the first swing adsorption reactor is reduced. The first swing adsorption reactor is purged with a portion of the first N2 stream recovered from the first swing adsorption reactor. The first purge output is passed to a second swing adsorption reactor comprising a second adsorbent material which adsorbs CO2. A second N2 stream is recovered from the second swing adsorption reactor. The pressure in the second swing adsorption reactor is reduced. The second swing adsorption reactor is purged with a steam purge.

A staged complementary pressure swing adsorption system and method for low energy fractionation of a mixed fluid. Two beds in a four-column PSA system are selective for component A, and another two columns are selective for component B. The cycle creates an intermittent A and B product, using the purge effluent from the complementary product fed at an intermediate pressure. This intermittent product is used as purge gas for low-pressure purged elsewhere in the cycle using appropriate storage tanks. The use of an intermediate pressure in this cycle enables continuous production of purified component A and B without the use of compressors. Columns may also be configured to enable pressure to equalize between complementary columns.

Example embodiments include systems for use in a wellhead platform. The system may comprise a separator subsystem, a scrubber subsystem, a first stage compressor subsystem, and a second stage compressor subsystem. The separator subsystem may comprise a separator inlet section for receiving multi-phase raw mixtures, a separator container body for housing the received multi-phase raw mixture, and a separator gas outlet section for separating gas. The scrubber subsystem may comprise a scrubber inlet section connected to the separator gas outlet section, a scrubber container body, and a scrubber gas outlet section for separating gas. The first stage compressor subsystem may be operable to receive gas separated from the scrubber subsystem, compress the received gas, and output the compressed gas. The second stage compressor subsystem may be operable to receive compressed gas from the first stage compressor subsystem, further compress the received compressed gas, and output the further compressed gas.

The present invention relates to a column (1) for thermal treatment of fluid mixtures, having a cylindrical, vertically aligned column body (2) which forms a column cavity (3), having a sequence of vertically spaced-apart dual-flow mass transfer trays (8) which are mounted in the column cavity (3) and which have orifices for passage of liquid and gas in countercurrent, and having at least one gas entry orifice (5) disposed below the lowermost of the sequence of dual-flow mass transfer trays (8). It is a characteristic feature of the column of the invention that a gas distribution tray (9) which is disposed between the lowermost of the sequence of dual-flow mass transfer trays (8) and the gas entry orifice (5) has orifices (32) for vertical passage of gas which can be introduced into the column cavity (3) via the gas entry orifice (5), the orifices (32) being formed so as to bring about equal gas distribution over the column cross section. The invention further relates to a process for thermal treatment of fluid mixtures in such a column (1).

The present invention is an air evacuation apparatus that prevents the accumulation of air inside a swimming pool or spa filter by allowing any air to be removed from inside the filter every time the swimming pool pump is turned on. By allowing air to be removed from the filter, the present invention prevents the build-up of dangerous levels of potential energy caused by compressed air inside the filter that can lead to the violent separation of the filter. More important, the air evacuation apparatus of the present invention allows air to be safely and automatically removed from inside of the filter without interfering with the functionality of the filter.

A sewer gas odor absorption apparatus for a manhole having a perforate manhole cover disposed in the manhole which includes an imperforate housing having a seal dimensioned and configured for sealing engagement with the manhole, the housing has a first extremity and a second extremity and a passageway in fluid communication with ambient air above the manhole cover at the first extremity and in fluid communication with sewer gases at the second extremity thereof. A sub-assembly including a porous absorption media and a variable volume device disposed in mutual fluid communication in a subassembly having first and second axial extremities, the first and second extremities of the subassembly being disposed in fluid communication respectively with the first and second extremities of the imperforate housing.

A pool cover for above ground swimming pools includes a cover with an elevated central area, a plurality of rods to support the cover, and a plurality of clip assemblies to couple the rods to the swimming pool. The cover is a waterproof textile having a plurality of sleeve members allowing for insertion of the support rods to secure and support the cover. Each clip assembly includes hook which removably attaches to an upper perimeter edge of the pool and a pocket to receive an end of the support rod. When assembled, the support rods form a dome-like structure circularly arranged about the edge of the pool.

A semiconductor device has a plurality of semiconductor die. A first prefabricated insulating film is disposed over the semiconductor die. A conductive layer is formed over the first prefabricated insulating film. An interconnect structure is formed over the semiconductor die and first prefabricated insulating film. The first prefabricated insulating film is laminated over the semiconductor die. The first prefabricated insulating film includes glass cloth, glass fiber, or glass fillers. The semiconductor die is embedded within the first prefabricated insulating film with the first prefabricated insulating film covering first and side surfaces of the semiconductor die. The interconnect structure is formed over a second surface of the semiconductor die opposite the first surface. A portion of the first prefabricated insulating film is removed after disposing the first prefabricated insulating film over the semiconductor die. A second prefabricated insulating film is disposed over the first prefabricated insulating film.

An example method includes providing a packaging device includes a substrate having an integrated circuit die mounting region. A plurality of microstructures, each including an outer insulating layer over a conductive material, are disposed proximate a side of the integrated circuit die mounting region. An underfill material is disposed between the substrate and the integrated circuit die, the microstructures preventing spread of the underfill. In another example method, a via can be formed in a substrate and the substrate etched to form a bump or pillar from the via. An insulating material can be formed over the bump or pillar. In another example method, a photoresist deposited over a seed layer and patterned to form openings. A conductive material is plated in the openings, forming a plurality of pillars or bumps. The photoresist and exposed seed layer are removed. The conductive material is oxidized to form an insulating material.

A method of making a semiconductor device can include providing a wafer comprising a plurality of semiconductor die, wherein each semiconductor die comprises an active surface and a backside opposite the active surface. A photosensitive layer can be formed over the wafer and on a backside of each of the plurality of semiconductor die within the wafer with a coating machine. An identifying mark can be formed within the photosensitive layer for each of the plurality of semiconductor die with a digital exposure machine and a developer, wherein a thickness of the identifying mark is less than or equal to 50 percent of a thickness of the photosensitive layer. The photosensitive layer can be cured. The wafer can be singulated into a plurality of semiconductor devices.

A semiconductor package is provided, including: an insulating base body having a first surface with an opening and a second surface opposite to the first surface; an insulating extending body extending outward from an edge of the first surface of the insulating base body, wherein the insulating extending body is less in thickness than the insulating base body; an electronic element having opposite active and inactive surfaces and disposed in the opening with its inactive surface facing the insulating base body; a dielectric layer formed in the opening of the insulating base body and on the first surface of the insulating base body, the insulating extending body and the active surface of the electronic element; and a circuit layer formed on the dielectric layer and electrically connected to the electronic element. The configuration of the insulating layer of the invention facilitates to enhance the overall structural rigidity of the package.

A semiconductor device includes a first moisture-resistant ring disposed in a peripheral region surrounding a circuit region on a semiconductor substrate in such a way as to surround the circuit region and a second moisture-resistant ring disposed in the peripheral region in such a way as to surround the first moisture-resistant ring.

A semiconductor mounting apparatus includes a storing unit that stores a liquid or a gas, a contact unit that comes into contact with a semiconductor chip when the storing unit is filled with the liquid or the gas, and a sucking unit that sucks up the semiconductor chip to bring the semiconductor chip into close contact with the contact unit.

A system for determining thickness variation values of a semiconductor substrate comprises a substrate vacuumed to a pedestal that defines a reference plane for measuring the substrate. A measurement probe assembly determines substrate CTV and BTV values, and defines a substrate slope angle. A thermal bonding assembly attaches a die to the substrate at a bonding angle congruent with the substrate slope angle. A plurality of substrates are measured using the same reference plane on the pedestal. Associated methods and processes are disclosed.

A method of ultrasonically bonding semiconductor elements includes the steps of: (a) aligning surfaces of a plurality of first conductive structures of a first semiconductor element to respective surfaces of a plurality of second conductive structures of a second semiconductor element; (b) ultrasonically forming tack bonds between ones of the first conductive structures and respective ones of the second conductive structures; and (c) forming completed bonds between the first conductive structures and the second conductive structures.

A semiconductor device includes a substrate comprising a trench; a gate dielectric layer formed over a surface of the trench; a gate electrode positioned at a level lower than a top surface of the substrate, and comprising a lower buried portion embedded in a lower portion of the trench over the gate dielectric layer and an upper buried portion positioned over the lower buried portion; and a dielectric work function adjusting liner positioned between the lower buried portion and the gate dielectric layer; and a dipole formed between the dielectric work function adjusting liner and the gate dielectric layer.

A method for forming a V-NAND device is disclosed. Specifically, the method involves deposition of at least one of semiconductive material, conductive material, or dielectric material to form a channel for the V-NAND device. In addition, the method may involve a pretreatment step where ALD, CVD, or other cyclical deposition processes may be used to improve adhesion of the material in the channel.

A method of forming a ferroelectric memory cell. The method comprises forming an electrode material exhibiting a desired dominant crystallographic orientation. A hafnium-based material is formed over the electrode material and the hafnium-based material is crystallized to induce formation of a ferroelectric material having a desired crystallographic orientation. Additional methods are also described, as are semiconductor device structures including the ferroelectric material.

Embodiments of the inventive concepts provide a method for manufacturing a semiconductor device. The method includes forming a stack structure including insulating layers and sacrificial layers which are alternately and repeatedly stacked on a substrate. A first photoresist pattern is formed on the stack structure. A first part of the stack structure is etched to form a stepwise structure using the first photoresist pattern as an etch mask. The first photoresist pattern includes a copolymer including a plurality of units represented by at least one of the following chemical formulas 1 to 3, wherein “R1”, “R2”, “R3”, “p”, “q” and “r” are the same as defined in the description.

A performance of a semiconductor device is improved. A film, which is made of silicon, is formed in a resistance element formation region on a semiconductor substrate, and an impurity, which is at least one type of elements selected from a group including a group 14 element and a group 18 element, is ion-implanted into the film, and a film portion which is formed of the film of a portion into which the impurity is ion-implanted is formed. Next, an insulating film with a charge storage portion therein is formed in a memory formation region on the semiconductor substrate, and a conductive film is formed on the insulating film.

A method of manufacturing a semiconductor device according to one embodiment includes forming a first film including a first metal above a processing target member. The method includes forming a second film including two or more types of element out of a second metal, carbon, and boron above the first film. The method includes forming a third film including the first metal above the second film. The method includes forming a mask film by providing an opening part to a stacked film including the first film, the second film and the third film. The method includes processing the processing target member by performing etching using the mask film as a mask.

Embodiments of the inventive concept provide a method for manufacturing a semiconductor device. The method includes forming a stack structure by alternately and repeatedly stacking insulating layers and sacrificial layers on a substrate, sequentially forming a first lower layer and a first photoresist pattern on the stack structure, etching the first lower layer using the first photoresist pattern as an etch mask to form a first lower pattern. A first part of the stack structure is etched to form a stepwise structure using the first lower pattern as an etch mask. The first lower layer includes a novolac-based organic polymer, and the first photoresist pattern includes a polymer including silicon.

A method of forming image sensor packages may include performing a molding process. Mold material may be formed either on a transparent substrate in between image sensor dies, or on a removable panel in between transparent substrates attached to image sensor dies. Redistribution layers may be formed before or after the molding process. Mold material may be formed after forming redistribution layers so that the mold material covers the redistribution layers. In these cases, holes may be formed in the mold material to expose solder pads on the redistribution layers. Alternatively, redistribution layers may be formed after the molding process and the redistribution layers may extend over the mold material. Image sensor dies may be attached to a glass or notched glass substrate with dam structures. The methods of forming image sensor packages may result in hermetic image sensor packages that prevent exterior materials from reaching the image sensor.

A method of forming a semiconductor device is provided such that a trench is formed in a semiconductor body at a first surface of the semiconductor body. Dopants are introduced into a first region at a bottom side of the trench by ion implantation. A filling material is formed in the trench. Dopants are introduced into a second region at a top side of the filling material. Thermal processing of the semiconductor body is carried out and is configured to intermix dopants from the first and the second regions by a diffusion process along a vertical direction perpendicular to the first surface.

A semiconductor device is provided that includes an n-type field effect transistor including a plurality of vertically stacked silicon-containing nanowires located in one region of a semiconductor substrate, and a p-type field effect transistor including a plurality of vertically stacked silicon germanium alloy nanowires located in another region of a semiconductor substrate. Each vertically stacked silicon-containing nanowire of the n-type field effect transistor has a different shape than the shape of each vertically stacked silicon germanium alloy nanowire of the p-type field effect transistor.

To provide a semiconductor device having improved reliability. After formation of an n+ type semiconductor region for source/drain, a first insulating film is formed on a semiconductor substrate so as to cover a gate electrode and a sidewall spacer. After heat treatment, a second insulating film is formed on the first insulating film and a resist pattern is formed on the second insulating film. Then, these insulating films are etched with the resist pattern as an etching mask. The resist pattern is removed, followed by wet washing treatment. A metal silicide layer is then formed by the salicide process.

A method of fabricating a semiconductor device includes forming a gate strip including a dummy electrode and a TiN layer. The method includes removing a first portion of the dummy electrode to form a first opening over a P-active region and an isolation region. The method includes performing an oxygen-containing plasma treatment on a first portion of the TiN layer; and filling the first opening with a first metal material. The method includes removing a second portion of the dummy electrode to form a second opening over an N-active region and the isolation region. The method includes performing a nitrogen-containing plasma treatment on a second portion of the TiN layer; and filling the second opening with a second metal material. The second portion of the TiN layer connects to the first portion of the TiN layer over the isolation region.

The on-state characteristics of a transistor are improved and thus, a semiconductor device capable of high-speed response and high-speed operation is provided. A highly reliable semiconductor device showing stable electric characteristics is made. The semiconductor device includes a transistor including a first oxide layer; an oxide semiconductor layer over the first oxide layer; a source electrode layer and a drain electrode layer in contact with the oxide semiconductor layer; a second oxide layer over the oxide semiconductor layer; a gate insulating layer over the second oxide layer; and a gate electrode layer over the gate insulating layer. An end portion of the second oxide layer and an end portion of the gate insulating layer overlap with the source electrode layer and the drain electrode layer.

A semiconductor structure is disclosed. The semiconductor structure includes a source trench in a drift region, the source trench having a source trench dielectric liner and a source trench conductive filler surrounded by the source trench dielectric liner, a source region in a body region over the drift region. The semiconductor structure also includes a patterned source trench dielectric cap forming an insulated portion and an exposed portion of the source trench conductive filler, and a source contact layer coupling the source region to the exposed portion of the source trench conductive filler, the insulated portion of the source trench conductive filler increasing resistance between the source contact layer and the source trench conductive filler under the patterned source trench dielectric cap. The source trench is a serpentine source trench having a plurality of parallel portions connected by a plurality of curved portions.

A semiconductor device includes a substrate comprising a channel region and a recess, wherein the recess is located at both side of the channel region; a gate structure formed over the channel region; a first SiP layer covering bottom corners of the gate structure and the recess; and a second SiP layer formed over the first SiP layer and in the recess, wherein the second SiP layer has a phosphorus concentration higher than that of the first SiP layer.

A method of production of a semiconductor device comprising a semiconductor layer forming step of forming a semiconductor layer including an inorganic oxide semiconductor on a board, a passivation film forming step of forming a passivation film comprising an organic material so as to cover the semiconductor layer, a baking step of baking the passivation film, and a cooling step of cooling the passivation film after baking, herein, in the cooling step, a cooling speed from a baking temperature at the time of baking in the baking step to a temperature 50° C. lower than the baking temperature is substantially controlled to 0.5 to 5° C./min in range is provided.