A ditch forming implement includes a frame supported for movement across the ground in a forward working direction when connected to a towing vehicle. A rotating member, for example a tire having a resilient main body and integral resilient paddles formed thereon, is rotatably supported on the frame within an upright plane oriented transversely to the forward working direction. The frame may also support a shovel on an implement shank spaced forwardly of the rotating member, an adjustable guide wheel supported rearwardly of the rotating member for controlling depth of the rotating member, and a grader blade supported forwardly and laterally offset to one side of the rotating member for widening a ditch to be formed by the implement.

A tobacco filter contains from 0.5 to 95% by mass of magnesium aluminometasilicate.

Delivery of additives in a smoking article is provided through thermally degradable, robust immobilized additive inserts. Additives can be immobilized in an elongated device or an insert, wherein the elongated device or the insert is sufficiently robust to allow the elongated device or the insert to be manually or machine inserted into a smoking article while maintaining the structure of the elongated device or the insert. By providing additives in the form of thermally degradable immobilized additive inserts, migration and/or loss of the additives in a smoking article prior to smoking can be reduced.

A protective device and method for preventing supply voltage of microcontroller from sag in electronic cigarette is provided, comprising a microcontroller, a power supply module, a field effect transistor, an energy storage circuit, wherein, the energy storage circuit is connected between the microcontroller and the power supply module, the energy storage circuit supplies electric power to the microcontroller when an over current or short circuit occurs, and maintains the supply voltage of the microcontroller not being less than its minimal operating voltage in a certain period of time; the microcontroller processes the over current or short circuit signal and turns off the MOSFET to cut off the current flow in a load circuit. The unstable or uncontrollable phenomena of the microcontroller in the existing technology are resolved. The circuit of the present invention is simple and low cost.

A system for producing porous masses may include a mold cavity disposed along the material path, at least one hopper before at least a portion of the mold cavity for feeding a matrix material to the material path, a heat source in thermal communication with at least a first portion of the material path, and a cutter disposed along the material path after the first portion of the material path.

Method of applying phase transition substance to impart reduced ignition propensity to a smoking article comprising a tobacco column and a wrapper surrounding the tobacco column and having a porous structure with a base permeability. The method comprising forming a pattern of phase transition material on the wrapper such that, when subjected to the heat of the tobacco column burning firecone, the phase transition material at least partially fills the wrapper porous structure in the vicinity of the burning firecone to form an area on the wrapper having reduced permeability lower than that of the wrapper base permeability. The reduced permeability of the wrapper in the vicinity of the burning firecone imparts reduced ignition propensity such that there is insufficient air flow to sustain combustion of the firecone or insufficient air flow to sustain an intensity of the burning firecone necessary to ignite the substrate.

A low power consumption semiconductor device is provided. The semiconductor device includes a decoder, a signal generation circuit, and a display device. The decoder includes an analysis circuit and an arithmetic circuit. The analysis circuit has a function of determining whether to decode the received first image data using the received data. The signal generation circuit has a function of generating a signal including an instruction on whether to decode the first image data in response to the determination of the analysis circuit. The arithmetic circuit has a function of decoding the first image data in response to the signal. The display device has a function of maintaining a second image displayed on the display device in the case where the first image data is not decoded in the arithmetic circuit.

A semiconductor device includes first to fourth terminals, a switch circuit, and an integrating circuit. The integrating circuit includes an amplifier circuit having a (−) terminal, a first (+) terminal, and a second (+) terminal. The integrating circuit is configured to integrate an input signal of the (−) terminal using an average voltage of a voltage of the first (+) terminal and a voltage of the second (+) terminal as a reference voltage. The switch circuit is configured to electrically connect the (−) terminal to the second terminal, the first (+) terminal to the first terminal, the second (+) terminal to the third terminal the (−) terminal to the third terminal, the first (+) terminal to the second terminal, and the second (+) terminal to the fourth terminal. The present semiconductor device is used as a semiconductor device sensing a current flowing through a pixel in a display panel.

A luminance controller according to example embodiments includes a gamma set selector to select a reference gamma set from among first through N-th gamma sets respectively corresponding to first through N-th reference luminances, based on a target luminance of a display panel; an initialization voltage selector to select an initialization voltage corresponding to the reference gamma set, from among first through N-th initialization voltage offsets respectively corresponding to the first through N-th gamma sets; a common voltage selector to select a common voltage corresponding to the reference gamma set from among first through N-th common voltage offsets respectively corresponding to the first through N-th gamma sets; and a determiner to determine a target initialization voltage based on the target luminance and the initialization voltage, and to determine a target common voltage based on the target luminance and the common voltage.

The present invention discloses an organic light-emitting diode display device and a driving method thereof. The device includes: a plurality of pixels, including a plurality of organic light-emitting diodes and a plurality of drive transistors for supplying drive currents to the organic light-emitting diodes; a data driver, configured to transmit corresponding data signals to the plurality of pixels via a plurality of data lines; and a pre-charge circuit, configured to pre-charge voltage signals reserved in a previous time sequence to an initial voltage, the initial voltage being less than or equal to a minimum voltage of the data signals, wherein before the data driver transmits the corresponding data signals to the plurality of pixels, the pre-charge circuit acts to pre-charge the voltage signals reserved in the previous time sequence by the plurality of pixels to be less than or equal to the minimum voltage of the data signals.

An image is displayed on an electronic display device at a reduced power level. Power used by the display device is maintained below a predetermined maximum power level by uniformly scaling the initial optical intensity of an image to a lower optical intensity whenever displaying the image at the initial optical intensity would result in power consumption of the display device exceeding the predetermined maximum power level.

An OLED touch display panel capable of detecting and reacting to touches on the display includes a signal sending element emitting ultrasonic signals, a driving layer configured to provide display driving signals, a light-emitting element configured to receive the display driving signals and emit light, and a signal receiving element configured for receiving reflected ultrasonic signals. The light-emitting element includes a plurality of light-emitting units and a plurality of black matrixes. Every two adjacent light-emitting units are separated from each other by one of the black matrixes. The signal receiving element includes a plurality of thin film transistor units arranged in a matrix. Each thin film transistor unit is formed on one of the black matrixes.

Systems, computer program products, and methods useful for handling or managing microplates are provided.

A belt tracking system for adjusting displacement of a movable belt in an axial direction of a plurality of rollers about which the movable belt is entrained includes a slope member and a roller shaft support. The slope member is disposed at least at one end of at least one of the plurality of rollers in the axial direction, to tilt the roller due to movement of the belt. The roller shaft support rotates about a predetermined shaft and includes a shaft recovery member to recover a tilt of the slope member. The shaft recovery member is disposed within a shortest circumference of a closed curve among closed curves within which the slope member and the roller shaft support are disposed in a state in which the roller shaft support is rotated.

A hand pump (16) includes a housing (22) having an inlet (18) and an outlet (26) and an actuating body (32) movably mounted in the housing axially and a membrane (46) with a flexible ring section (48) surrounding the stroke axis (34). During stroke movement, the actuating body (32) is pressed with the membrane (46) against the force of an elastic element (42) from a resting position (I) into the pump housing (22) and into an actuating position, and returned to the resting position (I) by the elastic element (72). Thus, the volume of a pump chamber (20) can be modified.

A valve timing control apparatus includes: a drive-side rotor rotating in synchronization with a crankshaft of an internal combustion engine; a driven-side rotor arranged to have the same shaft center as the drive-side rotor, rotating in synchronization with a camshaft for opening and closing valves; a fluid pressure chamber formed between the drive-side driven-side rotors; a partitioning portion provided in at least one of the drive-side and driven-side rotors; a timing advance chamber and a timing delay chamber formed by partitioning the fluid pressure chamber by the partitioning portion; a lock mechanism including a lock member and a concave portion a lock release flow path through which operating fluid supplied and discharged to and from the concave portion is circulated; a valve arranged in the middle of the lock release flow path; and a control unit controlling the operation of the valve.

A method of controlling a vehicle associated micro-hybrid system. The system includes a reversible rotary electrical machine that is connected to a thermal engine of a motor vehicle. The method includes: controlling a step of pre-fluxing of a rotor of the reversible rotary electrical machine when a control module receives an instruction to start the thermal engine via the reversible rotary electrical machine; measuring a speed of the rotor of the reversible rotary electrical machine; and, demanding stoppage of the pre-fluxing step when the speed of the rotor is greater than or equal to a predetermined speed threshold value. The method avoids the generation of overvoltages in an electrical distribution network formed by an onboard network of the vehicle and by an energy storage unit of the micro-hybrid system.

A venturi mixing valve assembly includes three open-ended tubular sections. A first section, coupled to a supply of a first gas and a supply of a second gas, has a sleeve defined therein wherein an annular channel open on one end thereof is defined between the sleeve and an inner surface of the first section. A second section defines an annular region with a plurality of holes and a venturi region coupled to the annular region. The annular region circumscribes at least a portion of the first section's sleeve. A third section is threadably coupled to outer surfaces of the first and second sections such that rotation of the third section in a first direction causes the first and second sections to move axially towards one another, while rotation of the third section in a second direction causes the first and second sections to move axially away from one another.

A vehicle is provided with an engine, an H2 and CO tank, a CO2 reclaimer, an electrolytic solution tank, an electrolyzer, a water tank and the like. During operation of the engine, an exhaust gas is introduced into an absorbing liquid in the CO2 reclaimer so as to recover CO2 in the exhaust gas and to store the same in the electrolytic solution tank. While supplying the absorbing liquid having absorbed CO2 and water to the electrolyzer from the electrolytic solution tank and the water tank, respectively, electric power is supplied to the electrolyzer. As a result, a mixed gas composed of CO and H2 from CO2 and water. The generated mixed gas is temporarily stored in the H2 and CO tank and is supplied to the engine.

A flow limiter for a fuel system is provided. The flow limiter includes a self-contained portion that enables testing of the flow limiter prior to assembly into a fuel system. A housing of the flow limiter is arranged to provide reduced or no pressure differential across a wall of the housing, permitting the housing to be reduced in size and thickness and providing improved consistency of operation.

Provided is a timing adjustment system having improved control for achieving a target rotational phase. The valve timing adjustment system includes a displacement mechanism unit that displaces a rotational phase of a camshaft relative to a crankshaft of an internal combustion engine; a locking mechanism unit that locks the rotational phase at an intermediate locked phase positioned within a displacement range of the rotational phase; a hydraulic pathway that hydraulically drives the displacement mechanism unit and the locking mechanism unit; and a control unit including a control system that controls operations of the hydraulic control valve. The control unit changes a temporal responsiveness of the control system based on a displacement force that displaces the rotational phase.

A valve timing adjusting device for and engine includes a sprocket configured to rotate by receiving drive power from a driving shaft, a vane rotor fixed to a driven shaft so as to be rotatable relative to the sprocket, a housing that includes an oil chamber housing the vane rotor and is fixed to one end in a thickness direction of the sprocket, a bolt fixing the sprocket to the housing, and a knock pin inserted into a sprocket hole formed in the sprocket at one end thereof and into a housing hole formed in the housing at the other end thereof to restrict relative relation between the sprocket and the housing. The knock pin abuts against an inner wall of the sprocket hole at one end thereof, and abuts against an inner wall of the housing hole at the other end thereof.

Apparatus and methods are disclosed, such as a method that includes precharging channel material of a string of memory cells in an unselected sub-block of a block of memory cells to a precharge voltage during a first portion of a programming operation. A programming voltage can then he applied to a selected memory cell in a selected sub-block of the block of memory cells during a second portion of the programming operation. The selected memory cell is coupled to a same access line as an unselected memory cell in the unselected sub-block. Additional methods and apparatus are disclosed.

A semiconductor memory device includes first and second memory cells, each of which includes a charge storage layer, a first bit line that is connected to the first memory cell, and a second bit line that is connected to the second memory cell. A writing operation includes multiple loops of a programming operation and a verification operation, and first data is written in the first memory cell, and second data different from the first data is written in the second memory cell through the writing operation. In a first loop of the writing operation, a first voltage is applied to the first bit line and the second bit line is maintained in an electrically floating state during the programming operation, and a verification operation relating to the second data is not performed and a verification operation relating to the first data is performed.

A nonvolatile memory device is provided as follows. A memory cell array includes a plurality of memory cells. An address decoder provides a first verify voltage to selected memory cells among the plurality of memory cells in a first program loop and provides a second verify voltage to the selected memory cells in a second program loop. A control logic determines the second program loop as a verify voltage offset point in which the first verify voltage is changed to the second verify voltage based on a result of a verify operation of the first program loop.

A programmable memory including a self-latching read data path. A sense amplifier senses the voltage level at a bit line, the bit line communicating the data state of a selected memory cell in its associated column. A data latch coupled to the output of the sense amplifier passes the sensed data state. Set-reset logic is provided that receives the output of the data latch in the read data path and, in response to a transition of the data state in a read cycle, latches the data latch and isolates it from the sense amplifier. The set-reset logic resets the data latch at the start of the next read cycle. In some embodiments, a timer is provided so that the latch is reset after a time-out period in a long read cycle in which no data transition occurs.

To provide a magnetic element capable of performing skyrmion transfer, a skyrmion memory to which this magnetic element is applied, and a shift register, for example, a magnetic element capable of performing skyrmion transfer is provided, the magnetic element providing a transverse transfer arrangement in which the skyrmion is transferred substantially perpendicular to a current between an upstream electrode and a downstream electrode, and including a plurality of stable positions in which the skyrmion exists more stably than in other regions of a magnet, and a skyrmion sensor that detects a position of the skyrmion.

To provide a magnetic element which can generate a skyrmion, and a skyrmion memory which applies the magnetic element or the like. To provide a magnetic element with a chiral magnet for generating a skyrmion, the chiral magnet is made of a magnetic material having a β-Mn type crystal structure. Also, to provide a magnetic element with a chiral magnet for generating a skyrmion, the chiral magnet is made of a magnetic material having an Au4Al type crystal structure.

A magnetic element capable of generating and erasing a skyrmion, including a magnet shaped as a thin layer and including a structure surrounded by a nonmagnetic material; a current path provided surrounding an end region including an end portion of the magnet, on one surface of the magnet; and a skyrmion sensor that detects the generation and erasing of the skyrmion. With Wm being width of the magnet and hm being height of the magnet, a size of the magnet, with the skyrmion of a diameter λ being generated, is such that 2λ>Wm>λ/2 and 2λ>hm>λ/2. With W being width of the end region in a direction parallel to the end portion of the magnet and h being height of the end region in a direction perpendicular to the end portion of the magnet, the end region is such that λ≧W>λ/4 and 2λ>h>λ/2.

The semiconductor device includes a bit line, a transistor, a retention node, and a capacitor. The transistor has a function of charging or discharging the retention node. The capacitor has a function of retaining a potential of the retention node. A voltage greater than the sum of a writing voltage and a threshold voltage is applied to a gate of the transistor. When the transistor is turned on, a first potential is supplied to the bit line with a reference potential in a floating state. A voltage less than the sum of the writing voltage and the threshold voltage is applied to the gate of the transistor. When the transistor is turned on, a second potential is supplied to the bit line with a reference potential in a floating state. With use of the first and second potentials, the threshold voltage of the transistor is calculated without being influenced by parasitic capacitance and variations in the storage capacitance of the capacitor.

Provided is a magnetic element capable of generating one skyrmion and erasing the one skyrmion. The magnetic element includes a magnet shaped like a substantially rectangular flat plate, an upstream electrode connected to the magnet in a width Wm direction of the magnet and made of a non-magnetic metal, a downstream electrode connected to the magnet in the width Wm direction to oppose the upstream electrode and made of a non-magnetic metal, and a skyrmion sensor configured to detect the skyrmion. Here, a width Wm of the substantially rectangular magnet is such that 3·λ>Wm≧λ, where λ denotes a diameter of the skyrmion, a length Hm of the substantially rectangular magnet is such that 2·λ>Hm≧λ, and the magnet has a notch structure at the edge between the upstream electrode and the downstream electrode.

A signal shifting circuit may include a bank selection signal generation unit suitable for generating a bank selection signal synchronized with a first clock in response to a bank address and an internal write signal; and a shifting device suitable for generating a shifted bank selection signal by shifting the bank selection signal by a number of times according to latency information and for advancing a phase of the shifted bank selection signal whenever shifting the bank selection signal once or more so that the shifted bank selection signal is synchronized with a second clock having a phase leading a phase of the first clock.

A semiconductor device capable of stably holding data for a long time is provided. A transistor including a back gate is used as a writing transistor of a memory element. In the case where the transistor is an n-channel transistor, a negative potential is supplied to a back gate in holding memory. The supply of the negative potential is stopped while the negative potential is held in the back gate. In the case where an increase in the potential of the back gate is detected, the negative potential is supplied to the back gate.

A semiconductor memory device may include: a plurality of memory mats; and a plurality of sense amplifier arrays arranged alternately with the memory mats, each sense amplifier array being suitable for sensing and amplifying data of memory mats adjacent thereto, wherein during a data sensing operation to a memory mat among the plurality of memory mats, in addition to a sense amplifier for the memory mat and sense amplifiers positioned immediately above and below the sense amplifier for the memory mat, at least one additional sense amplifier closest to the sense amplifier for the memory mat is also activated for providing additional amplification.

An apparatus includes a first terminal configured to communicate data with an outside of the apparatus, a second terminal configured to receive a first power source potential, a third terminal configured to receive a second power source potential lower than the first power source potential, a fourth terminal configured to be coupled to a calibration resistor, an output buffer including first to third nodes coupled to the first to third terminals respectively, and a replica circuit including fourth and fifth nodes coupled to the second and third terminals respectively, and sixth node coupled to the fourth terminal.

A semiconductor memory device may include: a memory bank comprising a plurality of word lines; a smart command generation unit suitable for generating a smart refresh command, which is enabled at a random cycle, in response to an active command; and a refresh operation control unit suitable for performing a refresh operation to at least one of adjacent word lines of a target word line among the plurality of word lines in response to the smart refresh command.

According to one embodiment, a semiconductor storage apparatus includes a memory cell array and a read circuit. The memory cell array includes a memory cell which is connected to a word line. A threshold voltage of the memory cell corresponds to a data value of multiple bits. The read circuit receives designation of one bit among the multiple bits, applies a first reading voltage and a second reading voltage corresponding to the designated bit to the word line, senses ON or OFF of the memory cell for each reading voltage, and outputs a first sensed value and a second sensed value after performing the sensing for each reading voltage. The first sensed value is a sensing result in a case where the first reading voltage is applied. The second sensed value is a sensing result in a case where the second reading voltage is applied.

A memory device includes a first string and a second string. The first string includes first and second transistors and first cell transistors coupled in series between a source line and a bit line. The second string includes third and fourth transistors and second cell transistors coupled in series between the source line and the bit line. During a read, a gate of the fourth transistor is applied with a voltage to turn off the transistor, and after start of application of voltages to the first cell transistors, the gate of the fourth transistor is applied with a voltage substantially the same as a voltage applied to the source line.

According to one embodiment, a first well of the first conductivity type which is formed in a substrate. a second well of a second conductivity type which is formed in the first well. The plurality of memory cells, the plurality of first bit line select transistors, and the plurality of second bit line select transistors are formed in the second well, and the plurality of first bit line select transistors and the plurality of second bit line select transistors are arranged on a side of the sense amplifier with respect to the plurality of memory cells of the plurality of bit lines.

According to one embodiment, a semiconductor storage device includes a memory cell array having memory cell capable of holding N-bit data; and a sense amplifier comprising a first latch holding information on a threshold distribution, a second latch holding write data, and a third latch holding lower information of the N-bit data, and supplying a first to a fourth voltages to the memory cell to write the data to the memory cell using the first to fourth voltages. The sense amplifier supplies the first to third voltages to the memory cell based on information in the second and the third latches, and based on a result of transfer of the information held by the first latch to the second latch, supplies the fourth voltage or the first voltage to the memory cell.

According to one embodiment, a semiconductor memory device includes: first to third pages; first to third word line; and row decoder. In data writing, data is written into the first page before data is written into the second page. The row decoder is configured to apply first to third verify voltages to the gates of the first to third memory cells in a program verify operation.

A memory system may include a memory device including 0th to N-1th memory blocks, wherein N is a positive integer; and a controller having a first list and a second list, wherein the first list includes 0th to N-1th erase count values respectively for the 0th to N-1th memory blocks, wherein the second list includes 0th to N-1th difference values respectively for the 0th to N-1th memory blocks, wherein each of the 0th to N-1th difference values is a difference between an average value of the 0th to N-1th erase count values and each of the 0th to N-1th erase count values, wherein the controller selects a source block and a target block among the 0th to N-1th memory blocks depending on the 0th to N-th erase count values included in the first list and the 0th to N-1th difference values included in the second list to perform a wear leveling between the source block and the target block.

Semiconductor memory devices are provided. The semiconductor memory device includes an input/output (I/O) drive controller, a data I/O unit and a data transmitter. The input/output (I/O) drive controller generates drive control signals and an input control signal for driving first and second global I/O lines in a first test mode or a second test mode. The data I/O unit drives the first global I/O line in response to an input data when a write operation is executed in the first test mode and to drive the first and second global I/O lines in response to the drive control signals when the write operation is executed in the second test mode. The data transmitter transfers the data on the first global I/O line onto first and second local I/O lines to store the data on the first global I/O line in a memory cell array portion when the write operation is executed in the first test mode. The data transmitter also transfers the data on the first and second global I/O lines onto the first and second local I/O lines to store the data on the first and second global I/O lines in the memory cell array portion when the write operation is executed in the second test mode. Related methods are also provided.

Provided is a semiconductor device capable of holding data for a long period. The semiconductor device includes first to third transistors, a capacitor, and a circuit. The third transistor includes a first gate and a second gate. A gate of the first transistor is electrically connected to a first terminal of the capacitor. A first terminal of the first transistor is electrically connected to the second gate. A second terminal of the first transistor is electrically connected to the circuit. A gate of second transistor is electrically connected to a first terminal of the second transistor. A first terminal of the second transistor is electrically connected to the second gate. A second terminal of the second transistor is electrically connected to a first terminal of the capacitor. The circuit is configured to generate a negative potential. A channel formation region of the first transistor preferably includes an oxide semiconductor.

A method for fabricating a semiconductor device and a method for operating the semiconductor device are provided. The method for fabricating a semiconductor device includes forming a first electrode layer; forming a material layer, including conductive path components, over the first electrode layer; forming a second electrode layer over the material layer; performing a forming operation, which includes initially creating, in the material layer, a conductive path that electrically connects the first electrode layer to the second electrode layer by applying one of a predetermined voltage and a predetermined current between the first and second electrode layers, the conductive path including the conductive path components; and performing a first heat-treatment process at a predetermined temperature that removes some of the conductive path components from the conductive path, wherein a resistance state of the material layer changes based on the creation or dissolution of the conductive paths.

A method for transmitting uplink (UL) data requiring low latency in a wireless communication system according to the present invention, the method performed by a user equipment comprises transmitting contention PUSCH resource block (CPRB) indication information used for identifying a particular UE and/or particular data to an eNB; transmitting UL data to the eNB through CPRB resources of a contention based PUSCH (CP) zone; and receiving a hybrid automatic retransmit request (HARQ) response with respect to the UL data from the eNB through a physical hybrid ARQ indicator channel (PHICH).

In a communications system which complies with LTE including a base station which transmits data by using an OFDM (Orthogonal Frequency Division Multiplexing) method as a downlink access method, and a mobile terminal, in a case in which an uplink scheduling request signal is transmitted by using an S-RACH when an Ack/Nack signal is being transmitted by using an Ack/Nack exclusive channel, the transmission of the Ack/Nack signal is stopped while the uplink scheduling request signal is transmitted.

A first communication device and method therein for transmitting data information at fixed time instants on a radio channel to a second communication device in a radio communications network. First, the first communication device determines that the radio channel is available for transmitting data information to the second communication device during a time period determined by the first communication device. Then, the first communication device transmits a preamble on the available radio channel after the time period. The first communication device thereafter transmits the data information on the available radio channel to the second communication device at a next fixed time instant following the transmission of the preamble.

A data transmission apparatus in a communication system includes a reception unit configured to receive terminal information from a plurality of terminals through a new frequency band for transmission and reception of data between the plurality of terminals and an AP (access point); a determination unit configured to determine access timing of the terminals to the AP by using the terminal information, and generate terminal access information including information on the access timing; and a transmission unit configured to transmit the terminal access information and beacon frames to the terminals, wherein the terminals access the AP and transmit data frames to the AP, at the access timing based on the beacon frames.

Disclosed are a method for transmitting and receiving a frame in a wireless local area network (WLAN) system and an apparatus for the same. A method for generating interference/non-interference station lists includes receiving a first frame from a second station, acquiring a receiver address of the first frame from the first frame, and setting, based on whether to receive a second frame that is a response to the first frame from a third station indicated by the receiver address within a preset time from a time when the first frame has been received, the third station as an interference station or a non-interference station. Therefore, the performance of a communication system may be improved.