1 Lebanese Pound = 0.008 Botswana Pula

1 Lebanese Pound = 0.0012 Bulgarian Lev

1 Bahraini Dinar = 32.1126 Botswana Pula

1 Bahraini Dinar = 4.7742 Bulgarian Lev

1 Chilean Peso = 0.0147 Botswana Pula

1 Chilean Peso = 0.0022 Bulgarian Lev

1 Maldivian Rufiyaa = 0.7833 Botswana Pula

1 Maldivian Rufiyaa = 0.1165 Bulgarian Lev

1 Malaysian Ringgit = 2.8021 Botswana Pula

1 Malaysian Ringgit = 0.4166 Bulgarian Lev

1 Nicaraguan Cordoba Oro = 0.353 Botswana Pula

1 Nicaraguan Cordoba Oro = 0.0525 Bulgarian Lev

The NFL didn’t wait long to shine a spotlight on the new Brady-Brees rivalry, but the Saints' fate could be decided by brutal late-season stretch.

1 Netherlands Antillean Guilder = 6.7649 Botswana Pula

1 Netherlands Antillean Guilder = 1.0057 Bulgarian Lev

1 Estonian Kroon = 0.8515 Botswana Pula

1 Estonian Kroon = 0.1266 Bulgarian Lev

1 Danish Krone = 1.7649 Botswana Pula

1 Danish Krone = 0.2624 Bulgarian Lev

1 Fiji Dollar = 5.3902 Botswana Pula

1 Fiji Dollar = 0.8014 Bulgarian Lev

1 New Zealand Dollar = 7.4541 Botswana Pula

1 New Zealand Dollar = 1.1082 Bulgarian Lev

1 Croatian Kuna = 1.7503 Botswana Pula

1 Croatian Kuna = 0.2602 Bulgarian Lev

1 Peruvian Nuevo Sol = 3.5729 Botswana Pula

1 Peruvian Nuevo Sol = 0.5312 Bulgarian Lev

The collegiate races for the Haskell Invitational have been rescheduled for October 11 at 4pm.

The 2019 Haskell cross country schedule has been released and the Indians will compete at seven regular season meets before postseason action begins. The Purple and Gold will also play host to the Association of Independent Institutions conference meet as the defending champions on the men's side.

1 Dominican Peso = 0.2206 Botswana Pula

1 Dominican Peso = 0.0328 Bulgarian Lev

Baldwin City, Kansas - The Haskell Indian Nations University men's track and field teams competed at the Baker Relays on Saturday.

1 Papua New Guinean Kina = 3.5402 Botswana Pula

1 Papua New Guinean Kina = 0.5263 Bulgarian Lev

1 Brunei Dollar = 8.5931 Botswana Pula

1 Brunei Dollar = 1.2775 Bulgarian Lev

Differentiating good IP from mediocre or bad IP is getting more difficult, in part because it depends upon how and where it is used and in part, because even the best IP may work better in one system than another—even in chips developed by the same vendor.  

So, how do you measure IP quality and why it is so complicated?

The answer depends on who is asking. Most of the time, the definition of IP quality depends on your vantage point.  If you are an R&D manager, IP quality means something. If you are a global supply manager, IP quality means something else. If you are an SoC start-up, your measure of quality is quite different from that of an established fabless company. If you are designing IP in-house, then your considerations are very different than being a commercial IP vendor. If you are designing an automotive SoC, then we are in a totally different category. How about as an IP vendor? How do you articulate IP quality metrics to your customers?

This varies greatly by the type of IP, as well. When it comes to interface (hard) IP and controllers, if you are an R&D manager, your goal is to design IP that meets the IP specifications and PPA (power, performance, and area) targets. You need to validate your design via silicon test chips. This applies to all hard PHYs, which must be mapped to a particular foundry process. For controllers that are in RTL form—we called these soft IP—you have to synthesize them into a particular target library in a particular foundry process in order to realize them in a physical form suitable for SoC integration. Of course, your design will need to go through a series of design validation steps via simulation, design verification and passing the necessary DRC checks, etc. In addition, you want to see the test silicon in various process corners to ensure the IP is robust and will perform well under normal process variations in the production wafers.

For someone in IP procurement, the measure of quality will be based on the maturity of the IP. This involves the number of designs that have been taped out using this IP and the history of bug reports and subsequent fixes. You will be looking for quality of the documentation and the technical deliverables. You will also benchmark the supplier’s standard operating procedures for bug reporting and technical support, as well as meeting delivery performance in prior programs. This is in addition to the technical teams doing their technical diligence.

An in-house team that is likely to design IP for a particular SoC project will be using an established design flow and will have legacy knowledge of last generation’s IP. They may be required to design the IP with some reusability in mind for future programs. However, such reusability requirements will not need to be as stringent and as broad as those of commercial IP vendors because there are likely to be established metrics and procedures in place to follow as part of the design team’s standard operating procedures. Many times, new development based on a prior design that has been proven in use will be started, given this stable starting point. All of these criteria help the team achieve a quality outcome more easily.

Then, if designing for an automotive SoC, additional heavy lifting is required.  Aside from ensuring that the IP meets the specifications of the protocol standards and passes the compliance testing, you also must pay attention to meeting functional safety requirements. This means adherence to ISO 26262 requirements and subsequently achieving ASIL certification. Oftentimes, even for IP, you must perform some AEC-Q100-related tests that are relevant to IP, such as ESD, LU, and HTOL.

To read more, please visit: https://semiengineering.com/why-ip-quality-is-so-difficult-to-determine/

In the book “The World of _____” by Bennett Alan Weinberg and Bonnie K Bealer, there is a photograph of a label from a jar of pharmaceutical-grade crystals. It reads:

“WARNING: MAY BE HARMFUL IF INHALED OR SWALLOWED. HAS CAUSED MUTAGENIC AND REPRODUCTIVE EFFECTS IN LABORATORY ANIMALS. INHALATION CAUSES RAPID HEART RATE, EXCITEMENT, DIZZINESS, PAIN, COLLAPSE, HYPOTENSION, FEVER, SHORTNESS OF BREATH. MAY CAUSE HEADACHE, INSOMNIA, VOMITING, STOMACH PAIN, COLLAPSE AND CONVULSIONS.”

Fill in the blank.

Workoutable © 2007 IndiaUncut.com. All rights reserved.
India Uncut * The IU Blog * Rave Out * Extrowords * Workoutable * Linkastic

This is the 21st installment of The Rationalist, my column for the Times of India.

When all political parties agree on something, you know you might have a problem. Giriraj Singh, a minister in Narendra Modi’s new cabinet, tweeted this week that our population control law should become a “movement.” This is something that would find bipartisan support – we are taught from school onwards that India’s population is a big problem, and we need to control it.

This is wrong. Contrary to popular belief, our population is not a problem. It is our greatest strength.

The notion that we should worry about a growing population is an intuitive one. The world has limited resources. People keep increasing. Something’s gotta give.

Robert Malthus made just this point in his 1798 book, An Essay on the Principle of Population. He was worried that our population would grow exponentially while resources would grow arithmetically. As more people entered the workforce, wages would fall and goods would become scarce. Calamity was inevitable.

Malthus’s rationale was so influential that this mode of thinking was soon called ‘Malthusian.’ (It is a pejorative today.) A 20th-century follower of his, Harrison Brown, came up with one of my favourite images on this subject, arguing that a growing population would lead to the earth being “covered completely and to a considerable depth with a writhing mass of human beings, much as a dead cow is covered with a pulsating mass of maggots.”

Another Malthusian, Paul Ehrlich, published a book called The Population Bomb in 1968, which began with the stirring lines, “The battle to feed all of humanity is over. In the 1970s hundreds of millions of people will starve to death in spite of any crash programs embarked upon now.” Ehrlich was, as you’d guess, a big supporter of India’s coercive family planning programs. ““I don’t see,” he wrote, “how India could possibly feed two hundred million more people by 1980.”

None of these fears have come true. A 2007 study by Nicholas Eberstadt called ‘Too Many People?’ found no correlation between population density and poverty. The greater the density of people, the more you’d expect them to fight for resources – and yet, Monaco, which has 40 times the population density of Bangladesh, is doing well for itself. So is Bahrain, which has three times the population density of India.

Not only does population not cause poverty, it makes us more prosperous. The economist Julian Simon pointed out in a 1981 book that through history, whenever there has been a spurt in population, it has coincided with a spurt in productivity. Such as, for example, between Malthus’s time and now. There were around a billion people on earth in 1798, and there are around 7.7 billion today. As you read these words, consider that you are better off than the richest person on the planet then.

Why is this? The answer lies in the title of Simon’s book: The Ultimate Resource. When we speak of resources, we forget that human beings are the finest resource of all. There is no limit to our ingenuity. And we interact with each other in positive-sum ways – every voluntary interactions leaves both people better off, and the amount of value in the world goes up. This is why we want to be part of economic networks that are as large, and as dense, as possible. This is why most people migrate to cities rather than away from them – and why cities are so much richer than towns or villages.

If Malthusians were right, essential commodities like wheat, maize and rice would become relatively scarcer over time, and thus more expensive – but they have actually become much cheaper in real terms. This is thanks to the productivity and creativity of humans, who, in Eberstadt’s words, are “in practice always renewable and in theory entirely inexhaustible.”

The error made by Malthus, Brown and Ehrlich is the same error that our politicians make today, and not just in the context of population: zero-sum thinking. If our population grows and resources stays the same, of course there will be scarcity. But this is never the case. All we need to do to learn this lesson is look at our cities!

This mistaken thinking has had savage humanitarian consequences in India. Think of the unborn millions over the decades because of our brutal family planning policies. How many Tendulkars, Rahmans and Satyajit Rays have we lost? Think of the immoral coercion still carried out on poor people across the country. And finally, think of the condescension of our politicians, asserting that people are India’s problem – but always other people, never themselves.

This arrogance is India’s greatest problem, not our people.

© 2007 IndiaUncut.com. All rights reserved.
India Uncut * The IU Blog * Rave Out * Extrowords * Workoutable * Linkastic

Hello, i have a logic output from a D-flipflop which generates a reset signal with variable pulse width. I want to stretch this LOW pulse width with an extra 100ns added to the original pulse width digitally, is there any way to do that?

When I enable clock gating in my synthesis flow (using Genus 18.15), my simulation (using Xcelium) on the post-synthesis netlist fails. The simulation succeeds pre-synthesis and also if I remove clock-gating in the design. I use set_db  lp_insert_clock_gating true to enable clock gating during synthesis. I printed out some of the signals from the netlist and can see where it fails (it incorrectly writes a register). However, I am not sure how to solve this issue or what I should be looking for. Any help would be appreciated. Thanks.

Dear all,

I am using Conformal Constraint Designer (Version 17.1) to analyse a SystemVerilog based design.

While performing default HDL checks it finds  some violations (issues) in RTL and complains (warnings, etc) about RTL checks and others.

My questions:

Is there any directive which I can add to RTL (system Verilog) so that particular line of code or signal is ignored or not checked for HDL or RTL checks.

I can set ignore rules in rule manager (gui) but it does not seems effective if code line number changes or new signals are introduced.

What is the best way to customize default_hdl_rules ?

I will be grateful for your guidance.

Thanks for your time.

Hi Folks, A question that I've often received from designers, "Is there a method to determine the amount of memory required before I submit a job? I use distributed processing and need to provide an estimate before submitting jobs." The answer...(read more)

Hi All, Here's another great new feature that I've found very helpful... Broadband SPICE is a new tool for S-parameter simulation in Spectre RF. In the MMSIM13.1.1 ( MMSIM13.1 USR1) release (now available on http://downloads.cadence.com), a...(read more)

Did you check out the new Pnoise and Hbnoise Choosing Analyses forms in the MMSIM 15.1 and IC6.1.7 /ICADV12.2 releases? These forms have been significantly improved and simplified. The Direct Plot Form has also been enhanced and is much easy to use....(read more)

Hello Spectre Users, Simulating S-parameters in a time domain (transient, periodic steady state) simulator has been and continues to be a challenge for many analog and RF designers. I'm often asked: What is required in order to achieve accurate...(read more)

Hi All, If you were unable to attend IMS 2017 in June 2017, the IMS MicroApp “7 Habits of Highly Successful S-Parameters” is on our Cadence website. On Cadence Online Support , the in-depth AppNote is here: 20466646 . Best regards, Tawna...(read more)

Hi,

I am trying to use "sed -e 's " from SKILL code to edit unix file "FileA", to replace 3 words in the 2nd line.

How to run below multiple commands using  ipcBeginProcess, Should I use ipcWait or ipcCloseProcess ?

Using && to combine , will that work as I have to work serially on each command. ?

With below code only the first command gets executed. Please advise.

FileA="/user/tmp/text1.txt"

sprintf(Command1 "sed -e '2s/%s/%s/g' %s > %s" comment1 get(form concat("dComment" RDWn))->value FileA FileA)
cid = ipcBeginProcess(Command1)


sprintf(Command2 "sed -e '2s/%s/%s/g' %s > %s"  Time getCurrentTime() FileA FileA)
cid1 = ipcBeginProcess(Command2)


sprintf(Command3 "sed -e '2s/%s/%s/g' %s > %s"  comment2 get(form concat("Duser" RDWn))->value FileA FileA)
cid2 = ipcBeginProcess(Command3)

Thanks,

Ajay

Hi,

I am running simulation in ADEXL and need a custom function for VIVA to apply same procedure to all signals saved in output. For instance, I have clock nets and I want to get all of them and look at the duty-cycle, edge rate etc.

It is a little more involved than about part since I have some regex and setof to filter before processing but if I can get all signals for current history, I can postprocess them later.

In ocean, I am just doing outputs() and getting all saved signals but I was able to do this in VIVA calculator due to the difficulties in getting current history, test name and opening result directory

thanks

yayla

Version Info:

ICADV12.3 64b 500.21

spectre -W =>

Tool 'cadenceMMSIM' Current project version '16.10.479'
sub-version  16.1.0.479.isr9

When I place a pcell and do not change the W parameter (default is used) the value is not saved in the OA cell property.

When I change the default value of the super master now, the old pcell will get the new default value automatically because there is nothing saved inside the OA cell for this parameter.

Do you have any Idea, that how we can save the default values in the OA cell properties so that this value doesn't get updated if the default values are updated in the new PDKs