Mock test paper for CA exams 2020: In the view of Coronavirus pandemic, the Board of Studies of ICAI will be commencing the Mock Test Papers (Series-1) online this month.

International Women's Day Special: This Braveheart girl averts a rape attempt - Youtube Video

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[Daily Maverick] The Eastern Cape Department of Health has confirmed that 80 of a group of 188 seasonal farmworkers who returned to the province from the Western Cape over the past two weeks have tested positive for coronavirus. The taxis were 'intercepted' on the province's back roads near Elliotdale. Some drivers were allegedly in possession of fake permits. The positive test results come as nearly 10,000 people returned home during the window period allowed for interprovincial travel.

[News24Wire] Police confiscated drugs worth close to R4 million as they were allegedly being smuggled into Cape Town.

Hello Spectre RF Users, Next week is my all time favorite technical conference - the International Microwave Symposium IMS2016 , May 22-27 in San Francisco, CA at the Moscone Center. If you're at the conference, please stop by the Cadence booth and...(read more)

I could not find info about the highlight shapes/layers in the cadence doc directory, forum, support library.

I have a script that creates highlight shapes on the y* drawing layer.

My understand is the highlight is a virtual shape. The shapes go away when the cadence session is closed or when you close data of that cellview if it is not global.

If they are vitual shapes it would be okay to use valid or process layers when I create the highlight set with geCreateHilightSet.

Ex: ( The command I use to create the hiighlight set       geCreateHilightSet(cv list(lay purp) nil) )

Current y0-9 drawing 

To N-P_implant drawing

Paul

Is there any way I can find duplicated shapes?

I would like to find two or more shapes are identical and they are placed in the same location.

Hi all,

I have a question regarding the manufacture : how to check a cluster of same net vias spacing, with have no shape or cline covered

Those who work in the IC Packaging design space have some unique challenges. We bridge between the IC design world (90/45-degree traces with rectangular and octagonal pins) and the PCB domain...

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Hi experts,

I have a problem with my design as below

ERROR: in SHAPE (-2.3622 2.3622)

  class = ETCH

  subclass = TOP 

  Part of Symbol Def SHAPE_4725X4725.

      Which is part of a padstack as a SHAPE symbol.

  ERROR(SPMHDB-187): SHAPE boundary may not cross itself.

   Error cannot be fixed.

       Object has first point location at (-2.3622 2.3622).

Can you tell me how to solve my problem?

Thanks a lot.

Currently I tried this:

axlDBCreateShape(recPolyPlanes t "BOUNDARY/L02" netName sym1)

I get a atom error on car(sym1)

I can do this "static" using ETCH/L02 with out an issue, but I am trying to avoid doing an axlShapeChangeDynamicType().

Thanks,

Jerry

Hi all,

I am creating shapes on plane layers for a coupon and want to void them using axlShapeAutoVoid()

The shapes are attached to a symbol.

I've tried using axlShapeAutoVoid, but this only voids the pins, not the route keepouts created by nc_backdrill.

I also tried selecting the shape, individually, then running axlShapeAutoVoid. That was unsuccessful, also.

planeShapes is a list of shapes I created. The code for voiding:

;run backdrill to get route keepouts
axlShell("setwindow pcb;backdrill setup ;setwindow form.nc_backdrill;FORM nc_backdrill apply ;FORM nc_backdrill close")

foreach(sHape planeShapes
axlShapeAutoVoid(car(sHape))
)

Those who work in the IC Packaging design space have some unique challenges. We bridge between the IC design world (90/45-degree traces with rectangular and octagonal pins) and the PCB domain (any-angle routing, filled planes, and a multitude of pad ...(read more)

Here are two screen capture of Before and After Autorouting my board. Padstacks have all been revised and corrected. The Capture Schematic is correct. All Footprints have been verified after Padstack revision. a new NETLIST generation have been done after some corrections made in Capture. I have imported the new Logic. I revised my Layout Cross Section as such: TOP, GND, VCC, BOTTOM. Both VCC and GND shapes have been assigned to their respective logical GND and VCC Nets (verified). Yet, I still have the Autorouter to systematically use extra vias to make GND and VCC connections to the VCC and GND planes. Where a simple utilisation of the part padstack inner layer would have been indicated. What Im I missing ?

Hi everybody,

I've created a symbol with custom pad shapes. Everything looks correct in the symbol editor.

And the 3d view looks correct (upside down to show placement)

But when I try to place it on the pcb the 2 "T" shaped pads aren't in the correct location.

I have the pad shape centered on the pad...

with no offset on the padstack editor.

Does anybody know how to fix this?

Thank you!

If you have one of those Die layouts, which doesn’t have bumps, but rather uses pad shapes and labels to identify I/O locations, then you might be feeling a bit left out of all of this jazz and tango. Hence, today, I am writing to tell you that, fear not, we have a solution for your Die as well.(read more)

The Call For Papers has been announced for REVULN 19Q4, an international cyber-security conference taking place December 11th and 12th, 2019 in Hong Kong at the Best Western Plus Hotel Hong Kong.

The No cON Name 2019 call for papers has been announced. It will be held in Barcelona, Spain, from November 14th and 15th, 2019.

BSidesLisbon 2019 has announced its call for papers. It will be held November 28th and 29th at Auditorio FMD-UL.

The ZeroNights 2019 Call For Papers has been announced. It will be held in Saint-Petersburg, Russia November 12th through the 13th, 2019.

RootedCON is a technology congress that will be held in Madrid (Spain) March 5th through the 7th, 2020. With an estimated seating from 2,000 and 2,500 people, is the most relevant specialized congress that is held in the country, and one of the most relevant in Europe, with attendee profiles ranging from students, Law Enforcement Agencies to professionals in the technology and information security market and, even, just passionate people.

The c0c0n 2020 Middle East call for papers has been announced. It will take place June 15th through the 18th, 2020 at the St. Regis in Abu Dhabi.

B-Sides Ljubljana will be held April 4th, 2020 in Ljubljana, Slovenia.

The 16th CarolinaCon will be hosted in Charlotte at the Embassy Suites April 10th through the 11th, 2020.

Call For Papers for Positive Hack Days 10 which will take place in Moscow, Russia May 13th through the 14th, 2020.

LeHACK 2020 is a yearly rendezvous where hackers and aficionados are meeting with both technical and non-technical talks and workshops about hacking. It is a great place to discover, to learn, to teach and be taught in the magical city of Paris. LeHACK 2020 will be held in La Cite des Sciences et de l'Industire in Paris, France from June 26th through the 27th, 2020.

REVULN 20x1 is an international conference taking place the April 28th through the 30th, 2020 in Metro Manila (Philippines) at the RED Hotel Cubao.

REVULN 20x2 is an international conference taking place the June 25th through the 26th, 2020 in St. Paul's Bay (Malta) at the Hotel Santana.

BSides Brussels is a security conference in Brussels, Belgium, with talks, workshops and villages. The goal is to strengthen the exchange of knowledge, cooperation, communication, and integration between the different actors active in the IT security industry. We are pleased to announce that the first edition of BSides Brussels will be held on May 28th, 2020.

REVULN 20x3 is an international conference taking place on September 9th through the 10th, 2020 in Bangkok (Thailand) at Ibis Styles Bangkok Sukhumvit Phra Khanong.

The call for papers for H2HC 17th edition is now open. H2HC is a hacker conference taking place in Sao Paulo, Brazil, from October 24th through the 25th of 2020.

Atlantis in South Africa has a new SEZ focused on green manufacturing, which is hoping to turn around the area's fortunes. Annie Hessler reports.

Today, solar power has become cheaper than the production cost of any other existing conventional power generation technology. The arrival of grid parity heralds a milestone in the history of energy production. It means solar energy being commercially viable without any subsidies or state support; producing energy with the lowest possible environmental impact.

Today, solar power has become cheaper than the production cost of any other existing conventional power generation technology. The arrival of grid parity heralds a milestone in the history of energy production. It means solar energy being commercially viable without any subsidies or state support; producing energy with the lowest possible environmental impact.

A new roadmap for the future of Ohio’s electric grid can benefit all types of interest groups, but the next few years will be critical for the plan to achieve its goals.

Australian urban planning and design and economics consultancy Cistri is using its evidence-based insights to help Asian developers design and plan urban communities that enhance quality of life.

随着嵌入式技术越来越受欢迎，目前，制造商正为是否将这种技术应用到电路板中而举棋不定。

与三位预约的 APEX 演讲者的访谈将带您抢先了解会议内容。

The Report Bosnia and Herzegovina Power Market Outlook to 2030 - Market Trends, Regulation and Competitive Landscape provides information on pricing, market analysis, shares, forecast, and company profiles for key industry participants. - MarketResearchReports.biz

Australian table grape exports to Korea have continuously increased year on year, with a three-fold increase each year from 162 tonnes in 2017; 776 tons in 2018 and 3,224 tons in 2019.

As many Australian clients know, India announced a 21-day lockdown across the entire country, commencing on March 24. At this point, this is the largest lockdown in the world affecting more than a billion people. On April 14, this lockdown was extended until May 3.