Hi all,

I have a question regarding the manufacture : how to check a cluster of same net vias spacing, with have no shape or cline covered

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Hello All,

After selecting a cline (using axlSingleSelectBox), may I know how to obtain the dbid of the 'pin' connected to the end of the cline?

Thanks All

Hi , 

I am sharing with you some simple skill script that draw line in user layer :

axlCmdRegister("DrawLine" 'DrawLine)
procedure(DrawLine()
   layer_name = "substrate geometry/userlayer"
   mypopup = axlUIPopupDefine(nil '(
      ("Done" "axlDBTransactionCommit(mark), axlFinishEnterFun()")
      ("Oops" "axlDBTransactionOops(mark), when(zerop(--oopsNum)")
      ("Cancel" "axlDBTransactionRollback(mark), axlCancelEnterFun()")
      ("MENU_SEPARATOR", nil)))
   axlUIPopupSet( mypopup)
   ; Clear the dynamic buffer
   axlClearDynamics()

   if(axlLayerGet(layer_name) != nil then
      if(axlIsVisibleLayer(layer_name) == nil then
         axlVisibleLayer(layer_name,t)
         axlVisibleUpdate(t)
      );End if
   else
      if(axlLayerGet("substrate geometry") == nil then
         layer_name = "board geometry/userlayer"
         axlLayerCreateNonConductor(layer_name)
         axlVisibleLayer(layer_name,t)
         axlVisibleUpdate(t)
      else
         axlLayerCreateNonConductor(layer_name)
         axlVisibleLayer(layer_name,t)
         axlVisibleUpdate(t)
      );End if
   );End if

   ; Clear mypath to nil, then loop gathering user picks:
   mypath = nil
   mark = axlDBTransactionStart()
   flag = t
   allP = list(nil)
   seg1 = nil
   seg2 = nil
   while( (mypath = axlEnterPath(?lastPath mypath))
      if(flag == t then
         p = axlDBCreatePath(mypath, layer_name)
         seg1 = car(car(car(p))->segments)
         seg2 = car(cdr(car(car(p))->segments))
         path = axlPathStart( list(car(seg1->startEnd)) , 0)
         axlPathLine( path , 0 , car(cdr(seg1->startEnd)))
         if(seg2 then
            axlPathLine( path , 0 , car(cdr(seg2->startEnd)))
         );end if
         flag = nil
      else
         p = axlDBCreatePath(mypath, layer_name)
         seg1 = car(car(car(p))->segments)
         seg2 = car(cdr(car(car(p))->segments))
         axlPathLine( path , 0 , car(cdr(seg1->startEnd)))
         if(seg2 then
            axlPathLine( path , 0 , car(cdr(seg2->startEnd)))
         );end if
      );end if
      allP = cons(car(car(p)) allP)
   );Loop
   axlDBCreatePath(path, layer_name)
   forall( x allP axlDeleteObject(x))
);End procedure

Is anyone can help to understand why this script can work with 16.5/16.6/17.2 and doesn't work with 17.4 ?

To be more informative in 17.4 this script behaves differently , when i am trying to draw line i can't zoom in/out ,i can't use my shortcuts to snap it on segment/middle/edge , it's like it's waiting only for next X/Y user click , all other functions just disabled .

Thanks .

Hi 

I'm trying to find the location of the assembly line in the design automatically without using "Show Element". And also I want to find the end points of that line. The line exists in "Package Geometry/Assembly_Top" Layer. So is there any code snippet to find the location of assembly line?

Hello All,

May I know if there is a way to breakup a selected clinesegment into a few clinesegments by just using SKILL code

Thanks All

This is the 16th installment of The Rationalist, my column for the Times of India.

Steven Pinker, in his book Enlightenment Now, relates an old Russian joke about two peasants named Boris and Igor. They are both poor. Boris has a goat. Igor does not. One day, Igor is granted a wish by a visiting fairy. What will he wish for?

“I wish,” he says, “that Boris’s goat should die.”

The joke ends there, revealing as much about human nature as about economics. Consider the three things that happen if the fairy grants the wish. One, Boris becomes poorer. Two, Igor stays poor. Three, inequality reduces. Is any of them a good outcome?

I feel exasperated when I hear intellectuals and columnists talking about economic inequality. It is my contention that India’s problem is poverty – and that poverty and inequality are two very different things that often do not coincide.

To illustrate this, I sometimes ask this question: In which of the following countries would you rather be poor: USA or Bangladesh? The obvious answer is USA, where the poor are much better off than the poor of Bangladesh. And yet, while Bangladesh has greater poverty, the USA has higher inequality.

Indeed, take a look at the countries of the world measured by the Gini Index, which is that standard metric used to measure inequality, and you will find that USA, Hong Kong, Singapore and the United Kingdom all have greater inequality than Bangladesh, Liberia, Pakistan and Sierra Leone, which are much poorer. And yet, while the poor of Bangladesh would love to migrate to unequal USA, I don’t hear of too many people wishing to go in the opposite direction.

Indeed, people vote with their feet when it comes to choosing between poverty and inequality. All of human history is a story of migration from rural areas to cities – which have greater inequality.

If poverty and inequality are so different, why do people conflate the two? A key reason is that we tend to think of the world in zero-sum ways. For someone to win, someone else must lose. If the rich get richer, the poor must be getting poorer, and the presence of poverty must be proof of inequality.

But that’s not how the world works. The pie is not fixed. Economic growth is a positive-sum game and leads to an expansion of the pie, and everybody benefits. In absolute terms, the rich get richer, and so do the poor, often enough to come out of poverty. And so, in any growing economy, as poverty reduces, inequality tends to increase. (This is counter-intuitive, I know, so used are we to zero-sum thinking.) This is exactly what has happened in India since we liberalised parts of our economy in 1991.

Most people who complain about inequality in India are using the wrong word, and are really worried about poverty. Put a millionaire in a room with a billionaire, and no one will complain about the inequality in that room. But put a starving beggar in there, and the situation is morally objectionable. It is the poverty that makes it a problem, not the inequality.

You might think that this is just semantics, but words matter. Poverty and inequality are different phenomena with opposite solutions. You can solve for inequality by making everyone equally poor. Or you could solve for it by redistributing from the rich to the poor, as if the pie was fixed. The problem with this, as any economist will tell you, is that there is a trade-off between redistribution and growth. All redistribution comes at the cost of growing the pie – and only growth can solve the problem of poverty in a country like ours.

It has been estimated that in India, for every one percent rise in GDP, two million people come out of poverty. That is a stunning statistic. When millions of Indians don’t have enough money to eat properly or sleep with a roof over their heads, it is our moral imperative to help them rise out of poverty. The policies that will make this possible – allowing free markets, incentivising investment and job creation, removing state oppression – are likely to lead to greater inequality. So what? It is more urgent to make sure that every Indian has enough to fulfil his basic needs – what the philosopher Harry Frankfurt, in his fine book On Inequality, called the Doctrine of Sufficiency.

The elite in their airconditioned drawing rooms, and those who live in rich countries, can follow the fashions of the West and talk compassionately about inequality. India does not have that luxury.

The India Uncut Blog © 2010 Amit Varma. All rights reserved.
Follow me on Twitter.

Hi supporters,

I got the following error while I run simulation with gate netlist using Cadence Incisive (v15.20):

----

ncsim(64): 15.20-s076: (c) Copyright 1995-2019 Cadence Design Systems, Inc.
ncsim: *E,DLOALB: Design library 'tcbnxxx' not defined while reading module tcbnxxx.MAOxxx:bv (VST).
ncsim: *F,NOSIMU: Errors initializing simulation 'alu_tb' 

----

xxx: standard library name.

My netlist design uses a cell "MAOxxx". I already included the library behavior model to compile using ncverilog, there is no error while compiling. But when I run with ncsim to execute the test, I got above error.

I tried to run with other vendors such as VCS or MTI, they worked.

Please help to understand the error.

Thanks.

Hello,

I have a question I want to create a cover that consists a sparse values, pre-computed (a list or define) for example l = {1; 4; 7; 9; 2048; 700} I'd like to cover that data a (uint(bits:16)) had those values, Any suggestion on how to achieve this, I'd prefer to stay away from macros, and avoid to write a lot of code

struct inst {

  data :uint(bits:16);
  opcode :uint(bits:16);
  !valid_data : list of uint(bits:16) = {0; 12; 10; 700; 890; 293;};
  event data_e;
  event opcode_e;

  cover data_e is {
     item data using radix = HEX, ranges = {
     //I dont want to write all of this
     range([0], "My range1");
     range([10], "My range2");
     //... many values in between
    range([700], "My rangen");
    };

    item opcode;

   cross data, opcode;
};

post_generate() is also {
    emit data_e;
};
};

Hello,

I am trying to import multiple verilog modules defined in a single file with "`define" directive in the top using Verilog In. The code below is an example of what my file contains.

When I use the settings below to import the modules into a library, it imports it correctly but completely ignores all `define directive; hence when I simulate using any of the modules below the simulator errors out requesting these variables.

My question: Is there a way to make Verilog In consider `define directives in every module cell created? 

Code to be imported by Cadence Verilog In:

--------------------------------------------------------

`timescale 1ns/1ps
`define PROP_DELAY 1.1
`define INVALID_DELAY 1.3

`define PERIOD 1.1
`define WIDTH 1.6
`define SETUP_TIME 2.0
`define HOLD_TIME 0.5
`define RECOVERY_TIME 3.0
`define REMOVAL_TIME 0.5
`define WIDTH_THD 0.0

`celldefine
module MY_FF (QN, VDD, VSS, A, B, CK);

inout VDD, VSS;
output QN;
input A, B, CK;
reg NOTIFIER;
supply1 xSN,xRN;
buf IC (clk, CK);
and IA (n1, A, B);
udp_dff_PWR I0 (n0, n1, clk, xRN, xSN, VDD, VSS, NOTIFIER);
not I2 (QN, n0);

wire ENABLE_B ;
wire ENABLE_A ;
assign ENABLE_B = (B) ? 1'b1:1'b0;
assign ENABLE_A = (A) ? 1'b1:1'b0;

specify
$setuphold(posedge CK &&& (ENABLE_B == 1'b1), posedge A,  `SETUP_TIME, `HOLD_TIME, NOTIFIER);
$setuphold(posedge CK &&& (ENABLE_B == 1'b1), negedge A, `SETUP_TIME, `HOLD_TIME, NOTIFIER);
$setuphold(posedge CK &&& (ENABLE_A == 1'b1), posedge B, `SETUP_TIME, `HOLD_TIME, NOTIFIER);
$setuphold(posedge CK &&& (ENABLE_A == 1'b1), negedge B, `SETUP_TIME, `HOLD_TIME, NOTIFIER);
$width(posedge CK,1.0,0.0,NOTIFIER);
$width(negedge CK,1.0,0.0,NOTIFIER);
if (A==1'b0 && B==1'b0)
(posedge CK => (QN:1'bx)) = (1.0, 1.0);
if (A==1'b1 && B==1'b0)
(posedge CK => (QN:1'bx)) = (1.0, 1.0);
if (B==1'b1)
(posedge CK => (QN:1'bx)) = (1.0,1.0);

endspecify

endmodule // MY_FF
`endcelldefine

`timescale 1ns/1ps
`celldefine
module MY_FF2 (QN, VDD, VSS, A, B, CK);

inout VDD, VSS;
output QN;
input A, B, CK;
reg NOTIFIER;
supply1 xSN,xRN;
buf IC (clk, CK);
and IA (n1, A, B);
udp_dff_PWR I0 (n0, n1, clk, xRN, xSN, VDD, VSS, NOTIFIER);
not I2 (QN, n0);

wire ENABLE_B ;
wire ENABLE_A ;
assign ENABLE_B = (B) ? 1'b1:1'b0;
assign ENABLE_A = (A) ? 1'b1:1'b0;

specify
$setuphold(posedge CK &&& (ENABLE_B == 1'b1), posedge A,  `SETUP_TIME, `HOLD_TIME, NOTIFIER);
$setuphold(posedge CK &&& (ENABLE_B == 1'b1), negedge A,  `SETUP_TIME, `HOLD_TIME, NOTIFIER);
$setuphold(posedge CK &&& (ENABLE_A == 1'b1), posedge B,  `SETUP_TIME, `HOLD_TIME, NOTIFIER);
$setuphold(posedge CK &&& (ENABLE_A == 1'b1), negedge B,  `SETUP_TIME, `HOLD_TIME, NOTIFIER);
$width(posedge CK,1.0,0.0,NOTIFIER);
$width(negedge CK,1.0,0.0,NOTIFIER);
if (A==1'b0 && B==1'b0)
(posedge CK => (QN:1'bx)) = (1.0, 1.0);
if (A==1'b1 && B==1'b0)
(posedge CK => (QN:1'bx)) = (1.0, 1.0);
if (B==1'b1)
(posedge CK => (QN:1'bx)) = (1.0,1.0);

endspecify

endmodule // MY_FF2
`endcelldefine

--------------------------------------------------------

I am using the following Cadence versions:

MMSIM Version: 13.1.1.660.isr18

Virtuoso Version: IC6.1.8-64b.500.1

irun Version: 14.10-s039

Spectre Version: 18.1.0.421.isr9

Hello,

I am using Virtuoso 6.1.7.

I am performing the parasitic extraction of a MOM cap array of 32 caps. I use Quantus QRC and I enable field solver. I select “QRCFS” for field solver type and “High” for field solver accuracy. The unit MOM cap is horizontally and vertically symmetric. The array looks like the sketch below and there are no other structures except the unit caps:

Rationally speaking, the capacitance values of the unit caps should be symmetric with respect to a vertical symmetry axis that is between cap16 and cap17 (shown with dashed red line). For example,

the capacitance of cap1 should be equal to the capacitance of cap32

the capacitance of cap2 should be equal to the capacitance of cap31

etc. as there are no other structures around the caps that might create some asymmetry.

Nevertheless, what I observe is the following after the parasitic extraction:

As it can be seen, the result is not symmetric contrary to what is expected. I should also add that I do not observe this when I perform parasitic extraction with no filed solver.

Why do I get this result? Is it an artifact resulting from the field solver tool (my conclusion was yes but still it must be verified)? If not, how can something like this happen?

Many thanks in advance.

Best regards,

Can

Introduction to AMSD Flex mode and its benefits.(read more)

This blog talks about how to enable the AMS Designer flex mode.(read more)

તો આજે આપણે જોઇએ કે કઇ રાશિનાં જાતકો માટે આ વૅલેન્ટાઇન કેવો રહેશે. તમને પ્રેમનો રંગ મળશે કે પ્રેમ પર પાણી ફરશે.

14 ફેબ્રુઆરીને વેલેન્ટાઈન ડે તરીકે ઉજવવામાં આવે છે. યુવાન હૈયાઓ આ દિવસની આતુરતાથી રાહ જોતા હોય છે. આ દિવસે યુવક યુવતીઓ પોતાના પ્રીય પાત્રને ગીફ્ટ આપીને પ્રેમનો એકરાર કરતા હોય છે. પરંતુ ગિફ્ટ આપવી અથવા લેવી અલગ અલગ ગ્રહો ઉપર અલગ અલગ અસર કરે છે.

આજના રાશીફળ પ્રમાણે જાણો તમારા ભાગ્ય, સ્વાસ્થ્ય, ધન, પ્રેમ-વિવાહ, નોકરી વગેરેની ભવિષ્યવાણી

પંડિતજીએ કહ્યું, Video Call દ્વારા હું આપના સંપર્કમાં રહીશ, અહીંથી મંત્ર બોલીશ અને ત્યાં પૂજા વિધિ કરતાં રહેજો

Inout PPC Engine suffers from a cross site request forgery vulnerability.

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