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Japanese Yen(JPY)/Kuwaiti Dinar(KWD)

1 Japanese Yen = 0.0029 Kuwaiti Dinar




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Japanese Yen(JPY)/Bahraini Dinar(BHD)

1 Japanese Yen = 0.0035 Bahraini Dinar





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Glory and Sadness, Beauty and Pain

X is a song written by Y and famously covered by Z. Time Magazine’s Josh Tyrangiel described it thus:

Y murmured the original like a dirge, but except for a single overwrought breath before the music kicks in, Z treated the 7-min. song like a tiny capsule of humanity, using his voice to careen between glory and sadness, beauty and pain, mostly just by repeating the word X. It’s not only Z’s best song — it’s one of the great songs, and because it covers so much emotional ground and is not (yet) a painfully obvious choice, it has become the go-to track whenever a TV show wants to create instant mood. ‘X can be joyous or bittersweet, depending on what part of it you use,’ says Sony ATV’s Kathy Coleman. ‘It’s one of those rare songs that the more it gets used, the more people want to use it.’

Name X, Y and Z.


Workoutable © 2007 IndiaUncut.com. All rights reserved.
India Uncut * The IU Blog * Rave Out * Extrowords * Workoutable * Linkastic




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The LSSP spectre simulation (Cadence 5) fails with the following error

What is the meaning of this error?

I used already two ports (PORT1 and PORT2 for input and output, respectively.

-------------------------------------------------------------------------------------------------------------------------

Also when I apply the PSP analysis for S-parameter the value of maximum S21 value (4.75 dB) is much lower than the maximum power gain (17.6 dB).

while the same circuit is designed using  ADS program the two values are approximately the same around (17.1 dB).




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ncsim: *E,FLTIGF: [FLT] Failed to inject fault at NET

Hi,

I'm doing the "The Targeted Fault Campaign" with ncsim and got stuck at the following message: "ncsim: *E,FLTIGF: [FLT] Failed to inject fault at circuit_tb.U0.n2174." I already tried with other NETs, with SET, SA0, SA1, always the same error occurs.


$nchelp ncsim FLTIGF
$ncsim/FLTIGF =
    Injection time is not within the expected finish
    time for the specified fault node. Failed to inject fault.

As can be seen below, the injection time is at 2ns and the -fault_good_run -fault_tw 1ns:100ns, so in theory 2ns is inside the window 1ns:100ns.


My scripts so far, considering I already compiled the Verilog testbench and also the gates from the technology library (gate-level simulation):

#this runs ok

ncelab -work worklib -cdslib circuit/trunk/backend/synthesis/work/cds.lib -logfile ncelab.log -errormax 15 -access +wc -status -timescale 1ps/1ps worklib.circuit_tb -fault_file circuit/trunk/backend/synthesis/scripts/fi.list

#this runs ok
ncsim -fault_good_run -fault_tw 1ns:100ns -fault_work fault_db -fault_overwrite worklib.circuit_tb:module -input ../scripts/fs_strobe.tcl -exit

#this runs NOT OK
ncsim -fault_sim_run -fault_work fault_db worklib.circuit_tb:module -input ../scripts/injection.tcl -exit

After the above command, I get: "ncsim: *E,FLTIGF: [FLT] Failed to inject fault at circuit_tb.U0.n2174."


Here are the files called from the commands above.

fi.list:

fault_target circuit_tb.U0.n2174 -type SET+SA1+SA0


fs_strobe.tcl:

fs_strobe circuit_tb.WRITE_OUT circuit_tb.PC_OUT[0]


injection.tcl:

fault -stop_severity 3 -inject -time 2ns -type sa1 circuit_tb.U0.n2174


I already checked the NETs with simvision, so their paths are correct.

I'm using as reference the following document: "Functional Safety Simulation - Product Version 15.2 - April 2016"


Any ideas are welcome.

Thank you in advance.




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ncsim: *E,FLTIGF: [FLT] Failed to inject fault at NET

Hi,

I'm doing the "The Targeted Fault Campaign" with ncsim and got stuck at the following message: "ncsim: *E,FLTIGF: [FLT] Failed to inject fault at circuit_tb.U0.n2174." I already tried with other NETs, with SET, SA0, SA1, always the same error occurs.


$nchelp ncsim FLTIGF
$ncsim/FLTIGF =
    Injection time is not within the expected finish
    time for the specified fault node. Failed to inject fault.

As can be seen below, the injection time is at 2ns and the -fault_good_run -fault_tw 1ns:100ns, so in theory 2ns is inside the window 1ns:100ns.


My scripts so far, considering I already compiled the Verilog testbench and also the gates from the technology library (gate-level simulation):

#this runs ok

ncelab -work worklib -cdslib circuit/trunk/backend/synthesis/work/cds.lib -logfile ncelab.log -errormax 15 -access +wc -status -timescale 1ps/1ps worklib.circuit_tb -fault_file circuit/trunk/backend/synthesis/scripts/fi.list

#this runs ok
ncsim -fault_good_run -fault_tw 1ns:100ns -fault_work fault_db -fault_overwrite worklib.circuit_tb:module -input ../scripts/fs_strobe.tcl -exit

#this runs NOT OK
ncsim -fault_sim_run -fault_work fault_db worklib.circuit_tb:module -input ../scripts/injection.tcl -exit

After the above command, I get: "ncsim: *E,FLTIGF: [FLT] Failed to inject fault at circuit_tb.U0.n2174."


Here are the files called from the commands above.

fi.list:

fault_target circuit_tb.U0.n2174 -type SET+SA1+SA0


fs_strobe.tcl:

fs_strobe circuit_tb.WRITE_OUT circuit_tb.PC_OUT[0]


injection.tcl:

fault -stop_severity 3 -inject -time 2ns -type sa1 circuit_tb.U0.n2174


I already checked the NETs with simvision, so their paths are correct.

I'm using as reference the following document: "Functional Safety Simulation - Product Version 15.2 - April 2016"


Any ideas are welcome.

Thank you in advance.




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Stability analysis Phase margin and loop gain

Hi,

I am designing a resistive feedback TIA which needs a capacitor in its feedback loop for stability.

I would like to know the effect of a feedback capacitor on the phase margin to determine the optimal capacitance value.

My plan is to add it to the results after the stb analysis by using the direct plot>main form > phase margin (add to outputs).However it not getting added to my results list.

What could be a problem? Is there a way to add phase margin to the results using the calculator? 

I also find that the gain from the stability analysis(the closed loop gain) is different from that of the gain obtained for the closed loop simulation in AC analysis. Why is the difference, how is it computed in stability analysis?

Thanks,

-Rakesh.




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One Chai and a Wills Navy Cut

Pablo Bartholomew’s beautiful photo-show “Outside In” opened in Manhattan a few evenings ago. The exhibition is being held at Bodhi Art in Chelsea. Black-and-white photographs from the seventies and the eighties—reflecting Bartholomew’s engagement with people and places in Delhi, Bombay, and Calcutta.

These are not the pictures that made Bartholomew famous. The undying image of the father brushing the dust from the face of the child he is burying—that was the iconic photograph from the Bhopal tragedy in 1984. It also won for Bartholomew, still in his twenties, the World Press Photo’s Picture of the Year Award.

The images in “Outside In” do not commemorate grim tragedies or celebrate well-publicised public events. Instead, they are documents that offer intimate recall of a period and a milieu. Please click here to look at these photographs.

People who share a context with the photographer will have their own private reading of the scenes. For me, they evoke days when happiness seemed only one chai and a Wills Navy Cut away. There is charm and candor in these scenes. And because the young believe they will live forever, there is nothing defensive or stuck-up or overly self-conscious about their faces and postures.

Even the language of the captions is true to this spirit: “Self-portrait after a trippy night…”; “Nona writing and Alok zonked out…”; “Hanging out with the Maharani Bagh gang….” The exhibition catalogue has a fine essay by Aveek Sen that has also been published in the latest issue of Biblio.

Rave Out © 2007 IndiaUncut.com. All rights reserved.
India Uncut * The IU Blog * Rave Out * Extrowords * Workoutable * Linkastic




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RTL Compiler Beginner’s Guides Available on Cadence Online Support

With shrinking design nodes, a significant portion of the delays are contributed by the wires rather than the cells. Traditional synthesis tools use fan-out-based wire-load models to provide wire delay information, which has led to significant differences...(read more)




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Traidnt Upload 3 Add Administrator

Traidnt Upload 3 add administrator exploit that leverages cookie manipulation.












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Brits Happy To Hand Over Password Details For 5 Pound Gift Voucher







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Security Failings At Siemens Could Lead To An Attack Worse Than Stuxnet






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Metamorphic Worms: Can They Remain Hidden?

Whitepaper that discusses types of computer worms and how metamorphic worms differ from the rest.




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Morris Worm sendmail Debug Mode Shell Escape

This Metasploit module exploits sendmail's well-known historical debug mode to escape to a shell and execute commands in the SMTP RCPT TO command. This vulnerability was exploited by the Morris worm in 1988-11-02. Cliff Stoll reports on the worm in the epilogue of The Cuckoo's Egg. Currently only cmd/unix/reverse and cmd/unix/generic are supported.




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Opera Update Draws The Curtain On Seven Security Vulns





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Researcher Raids Browser History For Webmail Login Tokens






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DMCA Strikes Again - First Amendment Does Not Apply




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Court Confirms DMCA Good Faith Web Site Shut Down




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DMCA Fails to Stop Garage Door Opener




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Coupons, Inc. Drops DMCA Lawsuit Against Coupon Hacker




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Apple Files Opposition To DMCA Exemption For Jailbreaking





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Air Raids Force Gadhafi Retreat, Rebels Seize East




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Rebel Hackers Seize Libyan Domain Name Registry






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US Marine Unearths Nukes, Cocaine, And $25 Million






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Variety Jones, Alleged Silk Road Mentor, Arrested In Thailand