I decided it was time to update my spectre install (currently a version of Spectre211).  Since 241 was a larger number than 211 I thought it would be a good idea (LOL)

Anyway, the simulator failed to run, and since I didn't have the time to debug why, I reverted to 211.

What's the difference in the two?

I have tried replicating the setup described in a previous post (here), with the proposed solution.

The MDL measurements return a value of 0 for all exported result but the first.

Using Viva I can actually see the correct value for each contribution.

I am using :
- Spectre 23.1.0.538.isr10
- Viva IC23.1-64b.ISR8.40

What should I do differently?

Thanks!

**** test.measure ****

Measurement Name   :  noi_test
Analysis Type      :  noise
noi_total             =  6.9282e-06
r1_flicker            =  0
r1_thermal            =  0
r1_total              =  0
r2_flicker            =  0
r2_thermal            =  0
r2_total              =  0

I want to use PSpice model (download from TI) in Virtuoso , but it can not work. Please help me to check the error message, Thanks

ADE-> Setup-> simulation files->Pspice  Files  /TPS628502-Q1_TRANS.LIB

Parse error before token ']' in expression '[[STEADY_STATE]*0.6]'. If '[[STEADY_STATE]*0.6]'  is a spice expression, quotes are required for the expression.

ERROR(SFE-46): An instance of 'TPS628502-Q1_TRANS'  can have at most 8 terminals (but has 9).

*****************************************************************************
.SUBCKT TPS628502-Q1_TRANS COMP_FSET EN FB GND PG SW SYNC_MODE VIN
+ PARAMS: STEADY_STATE=0
V_U9_V45 U9_N16725824 0 5
E_U9_ABM22 U9_N16725392 0 VALUE { V(FREQ)*1e-12 }
X_U9_U161 U9_N16849713 U9_N16846056 one_shot PARAMS: T=20

I want to use jaspergold to formally verify functionality of my custom multiplier. I am computing the expected result using A*B to check against output of my multiplier. Here, A and B are two logic signed operands. However, jaspergold is performing the operation A*B incorrectly.

I have reproduced this issue using the attached example. JasperGold compiles and elaborates the module and subsequently runs a formal proof. The tool raises a counterexample to assertion whose screenshot is attached below:

I simulated the same example using xrun and it was giving the correct product output in simvision waveform. Please help me resolve this issue. I am using 2023.03 version of Jasper Apps.

Thanks and regards

Anubhav Agarwal

I'm trying to use Jasper for checking parameter propagation in a large design. I have a list of top-level parameters, each with a HDL path of a module parameter somewhere lower in the hierarchy that's supposed to receive its value from the top-level module. The FPV app seems like an excellent tool for this, but elaborating the entire design in it is extremely time-consuming and memory-intensive. So, I'm trying to black-box everything but the interesting HDL paths. I thought using `elaborate -top dut_module_name -bbox_i * -no_bbox_i inst_foo -no_bbox_i inst_bar (...)` would work, but it doesn't. Jasper just starts flooding the log with warnings from modules that are definitely not on the whitebox list, and eventually dies due to insufficient memory. When I use -bbox_m * it correctly elaborates the top-level module with all of its sub-modules black-boxed. But then the -no_bbox_i switches have no effect. Could anyone suggest a working solution for this use case?

Hello,

I have been running this `uvm_reg_hw_reset_seq` sequence for the AHB protocol. My UVM Adapter looks like:

Issue: When I use basic reg.write, my write access are working well, as that is managed by the driver i.e. once adapter gives the packet to the driver, the driver supplies the address and the control signals to the DUT on the first clock cycle and then the write data on the next clock cycle. But when I am performing the read operation, somehow the UVM adapter is reading the data at the same clock cycle where read address + Controls are supplied and this is triggering read failure messages from the `uvm_reg_hw_reset_seq` sequence. What should I modify in the driver/sequencer/adapter so that the UVM adapter can read the data on the next cycle instead of the same clock cycle.

Just FYI: The waveforms of the read operation are correct, it is just the Adapter and the `uvm_reg_hw_reset_seq`. The AHB Driver + AHB Monitor is fully proven and verified to be working correctly.

I have been using the rank feature to identify tests that are redundant in our environment, but then I realized I'd also like to be able to see exactly what coverage goes into increasing the delta_cov value for a given test. If I had a test in my rank report that contributed 0.5% of the delta_cov, how could I got about seeing exactly where that 0.5% was coming from? It seems like that might be part of the correlate function, but I couldn't mange to find a way to see what specific coverage was being contributed for a given test.

Hi,

 I need to call a  c function form specman . I had followed the below steps.


File vb_pattern.e
---------------------------------

 
struct vb_pattern_s
{
  %data_in_ch0 : uint (bits : 4);   // data on channel 0
  %data_in_ch1 : uint (bits : 4);   // data on channed 1
  %data_in_ch2 : uint (bits : 4);   // data on channel 2
  %mode : uint (bits : 1);          // mode 
  %enable : uint (bits : 1);        // enable

};

C export vb_pattern_s;

------

file  x_output_bfm.e
--------------------------------------------

check_patterns()@clk_e is
{

  ...
 exp_viterbi_op();

}

routine exp_viterbi_op() is C routine viterbi_c_func;

---- EOF------

X.c
#include "vb_pattern.h"

void viterbi_c_func ()
{
 SN_TYPE(vb_pattern_s) vb_packet;
 SN_TYPE(mode)   mode;
 vb_packet = SN_SYS->ops
 mode = vb_packet->mode;
 printf(" Printing from C environment MODE = %h ", mode);

}


------------------- EOF----

x_top.e
------------
import  tb/vb_pattern.e;
import  tb/x_input_bfm.e;
import  tb/x_output_bfm.e;
import  tb/x_cover_dut.e;
import  tb/x_env.e;




I  did the following comand


>> sn_compile.sh -h_only x_top.e -o vb_pattern.h
>> gcc -c viterbi.c -o viterbi.o

I am getting the following error


viterbi.c: In function `viterbi_c_func':
viterbi.c:6: error: `t__mode' undeclared (first use in this function)
viterbi.c:6: error: (Each undeclared identifier is reported only once
viterbi.c:6: error: for each function it appears in.)
viterbi.c:6: error: syntax error before "mode"
viterbi.c:7: error: `mode' undeclared (first use in this function)


Please help me resolve this.

Kesav



  

Hello All,

starting with version 8.1 the contents of the ce_tools directory will no longer
be shipped with Specman. The directory contains some unsupported AE/R&D
ware and has not been updated for several releases (i.e. most of those old
packages don't work with the latest release).
 
Attached is the contents of this directory. Please read the README before
using any of the packages.


Regards,
-hannes

I've heard lots of people asking for a way to generate Makefiles for Specman code, and it seems there are some who don't use "irun" which takes care of this automatically. So I wrote this little utility to build a basic Makefile based on the compiled and loaded e code.

It's really easy to use: at any time load the snmakedeps.e into Specman, and use "write makefile <name> [-ignore_test]".
This will dump a Makefile with a set of variables corresponding to the loaded packages, and targets to build any compiled modules.
Using -ignore_test will avoid having the test file in the Makefile, in case you switch tests often (who doesn't?).

It also writes a stub target so you can do "make stub_ncvlog" or "make stub vhdl" etc.

The targets are pretty basic, I thought it was more useful to #include this into the main Makefile and define your own more complex targets / dependencies as required.

The package uses the "reflection" facility of the e language, which is now documented since Specman 8.1, so you can extend this utility if you want (please share any enhancements you make).

 Enjoy! :-)

Steve.

Hi everybody,

The attached package is a tiny code example with a demo for an upcoming Team Specman blog post about writing macros.

Hilmar

Attached is the latest revision of the venerable Specman-Matlab package (Lead Application Engineer Jangook Lee is the latest to have refreshed it for a customer in Asia to support 64 bit mode.  Look for a guest blog post from him on this package shortly.)

There is a README file inside the package that gives a detailed overview, shows how to run a demo and/or validate it’s installed correctly, and explains the general test flow.  The test file included in the package called "test_get_cmp_mdim.e" shows all the capabilities of the package, including:

* Using Specman to initialize and tear down the Matlab engine in batch mode

* Issuing Matlab commands from e-code, using the Specman command prompt to load .m files, initializing variables, and other operational tasks.

* Transfering data to and from the Matlab engine to Specman / an e language test bench

* Comparing data of previously retrieved Matlab arrays

* Accessing Matlab arrays from e-code without converting them to e list data structure

* Convert Matlab arrays into e-lists

Happy coding!

Team Specman

Attached is the latest emacs mode for e/Specman - version 1.23

Please follow the install instructions in the top section of the actual file
(after unzipping it) to install/load this package with your emacs.

Hello,

I have a question I want to create a cover that consists a sparse values, pre-computed (a list or define) for example l = {1; 4; 7; 9; 2048; 700} I'd like to cover that data a (uint(bits:16)) had those values, Any suggestion on how to achieve this, I'd prefer to stay away from macros, and avoid to write a lot of code

struct inst {

  data :uint(bits:16);
  opcode :uint(bits:16);
  !valid_data : list of uint(bits:16) = {0; 12; 10; 700; 890; 293;};
  event data_e;
  event opcode_e;

  cover data_e is {
     item data using radix = HEX, ranges = {
     //I dont want to write all of this
     range([0], "My range1");
     range([10], "My range2");
     //... many values in between
    range([700], "My rangen");
    };

    item opcode;

   cross data, opcode;
};

post_generate() is also {
    emit data_e;
};
};

Hi,
My Virtuoso and Spectre Version: ICADVM20.1-64b.NYISR30.2
I plot an eye diagram using a built in function. I want to see the data-dependent jitter. I want to measure the eye diagram edges at zero crossing (width of that diamond part) shown in the pic by vertical and horizontal markers. I can put a marker and read the numbers there and get what I want. But now I want to run Monte Carlo and I can't do this for all samples. I wish I could write an expression for this. Unfortunately, I see that the function "cross" is not working on the eye diagram. Basically, when I send the eye diagram data to a table, I see that it actually is just the prbs data and not the eye diagram data. Is there a hack that can help me achieve my goal which is: having an expression to measure the edges of the eye diagram at zero crossing?
There is a script that Andrew wrote (https://support.cadence.com/wps/mypoc/cos?uri=deeplinkmin%3AViewSolution%3BsolutionNumber%3D11395772). This is a good script but it puts all edges on top of each other. I want to distinguish the two edges. In the attached pic (two-period eye diagram) you can see what I mean by the two edges (diamond shapes). I want to measure each of the two and take the maximum. Having all the edges on top of each other won't give me what I want. All edges together will lso include DCD. I purely want to measure DDJ. DCD is measured separately. I have very little experience with writing scripts and could not modify Andrew's script.
Your help is much appreciated. Thank you.

In this post, we will learn about the most important parameters for the analog simulators that affect the accuracy of the simulation results. We will also understand how each parameter limits the accuracy of the measurements for the DC and transient analyses.(read more)

This blog describes the new capabilities in Spectre 21.1 ISR2 through which it provides support to the Voltus-XFi Custom Power Integrity Solution.(read more)

This blog introduces the new Voltus-XFi Custom Power Integrity Solution, a transistor-level EM-IR tool that enables designers to complete comprehensive analysis and debugging easily and quickly.(read more)

hello

is there a way to update one dynamic shape instead of updating all dynamic shapes?

i have over 6000 dynamic shapes on my design and it takes over 10 mins to update them all.

i just would like to update only one dynamic shape sometimes to find out if placing vias and lines in a shape has enough space or not.

regards

masa

I have a small shape for connecting three SMD pads, but it won't connect to one of the pads (0.2x0.6 mm). Thermal relief connects are set to Full contact for SMD pin in Shape parameters, but that doesn't help.

However, if I decrease the Minimum aperture for gap width in Void controls in Shape parameters to something below 0.2 mm the shape connects to the pad. But it is a little contracted at the pad entrance. Just 0.002 mm. What is going on here? 

Tried to attach some pictures, but I get: "An error occurred. Please try again or contact your administrator.". Will try later again.

/F

Any tips or SKIL files to help create a thermal shaped openings for paste masks for a donut shaped pin for mics or stand-offs like below?

Dear Community,

I have created a PCB layout with multiple high-speed nets, I want to check the SI like how signals are reflected and taken to each other.

I have the OrCAD X Professional, how to check the reflection and crosstalk using the OrCAD X Professional software version 24.1.

I want to create a topology flow to the PCB layout and perform the reflection and crosstalk.

Regards,

Rohit Rohan

Hai Community,

I have a PCB board which has multiple high speed nets and I want to perform the EMI and EMC checking.

Which Cadence tool should I use for checking the EMI and EMC coupling?

Regards,

Rohit Rohan

Dear Community,

I have created a PCB board and let's say I have found some parts of the PCB board where there are impedance issues, then how to resolve that impedance issue using the OrCAD X Professional.

Regards,

Rohit Rohan

Optimizing PCB thermal performance is essential in today’s high-density designs, as it ensures stability, prolongs component life, and prevents potential thermal issues. One of the first steps to achieving this is with strategic component placement. Positioning high-power components—such as regulators, power transistors, or processors—away from heat-sensitive parts can prevent thermal interference, and placing them near the edges of the PCB often helps dissipate heat more effectively. It’s also beneficial to group components by their heat generation, creating dedicated thermal zones that can manage localized heating and reduce impact on other areas of the board.

Using thermal vias is another effective technique. By placing thermal vias under components like BGAs or power ICs, heat can be transferred from the surface to internal layers or ground planes. Increasing the size and number of these vias, or using thicker plating, enhances heat conductivity and helps manage heat more evenly across layers in multilayer boards. Increasing copper thickness on the PCB also has a major impact. Opting for thicker copper layers (e.g., 2 oz or even 3 oz copper) significantly boosts the heat dissipation capabilities of power planes and traces, especially in high-current areas. Large copper planes, such as dedicated ground or power planes, are equally effective in spreading heat efficiently. Adding thermal pads directly beneath heat-generating components improves this heat distribution.

Thermal relief pads help regulate heat flow for through-hole components by controlling heat transfer, which reduces thermal stress during soldering and prevents excessive heat spread to nearby sensitive areas. Performing thermal analysis with software tools like Celsius can be invaluable, as it allows you to simulate and model heat distribution, spot potential thermal issues, and refine your design before finalizing it.

Using heat sinks and thermal pads provides a direct way to draw heat from high-power components. Heat sinks can be attached with thermal adhesives, screws, or clamps, while thermal interface materials (TIMs), such as thermal pads or conductive adhesives, further reduce thermal resistance, enhancing heat-transfer efficiency. Optimizing the PCB layer stackup is also a key factor. Dedicated ground and power layers improve heat conduction across the PCB, enabling heat transfer between layers, particularly in high-density and multilayer PCBs.

In designs with high power requirements, active cooling options like fans, blowers, or heat pipes can be essential, helping to direct airflow across the PCB and further improving heat dissipation. Adding ventilation slots around hot zones and considering passive cooling paths enhance natural airflow, making the design more thermally efficient. By combining several of these techniques, you can create a PCB that handles heat effectively, resulting in a robust, long-lasting, and reliable product.

Let us know if you’ve had any challenges with thermal management in your designs—I’d be glad to discuss further!

Has anyone experienced the same situation?

Research by fDi Intelligence reveals which countries receive more than their ‘expected share’ of FDI. 

A look at the results of fDi’s rankings throughout 2019 finds that Singapore and New York dominated the year’s league tables, followed by Shanghai, Tokyo and London

Sub-Saharan Africa is the world’s fastest growing mobile phone market, but how can telecoms companies make the most of the huge opportunities the region provides?

Atlantis in South Africa has a new SEZ focused on green manufacturing, which is hoping to turn around the area's fortunes. Annie Hessler reports.

The UK is the Europe's leading destination for foreign investment in green energy, followed by Spain, finds fDi’s Top European Locations for Renewable Energy Investment.

In spite of the uncertainty caused by Brexit, London retains its position as fDi's European City of the Future for 2020/21, while Paris keeps the regional crown.

London has retained its position as fDi’s European City of the Future, while Paris has climbed to second place, knocking Dublin into the third spot. 

London is crowned best major city in Europe in fDi's FDI Strategy category, with Glasgow, Vilnius, Reykjavik and Galway also winning out.

Paris Region has kept its fDi European Region of the Future title, while Dublin Region holds on to second place and North Rhine-Westphalia is in third. 

North Rhine-Westphalia is fDi's top large region for FDI Strategy, with the Basque Country topping the table for mid-sized regions and Ireland South East first among small regions. 

London LEP and Thames Valley Berkshire LEP hold on to their respective first and second places in the Local Enterprise Partnership rankings, while Oxfordshire LEP jumps up eight places to third. 

Despite nurturing its R&D capacity, the city of Braunschweig lags its German peers in attracting FDI. Now it hopes a focus on the mobility sector will mean its technical skills are matched with investment.

Togo won a record number of greenfield investment projects last year.

Lower fertility rates will boost economic growth, according to a demographic model developed by Renaissance Capital. 

Sino-European foreign direct investment is converging, according to data from fDi Markets.

The eastern Chinese city of Zibo is recognised as the official birthplace of football. However, its local government is hoping it will soon be known for its excellence in the chemical, medical and manufacturing industries.

President Obrador aims to mobilise billions in public and private investment to create an alternative to the Panama Canal along the Tehuantepec corridor. 

The Eastern Caribbean Central Bank is to launch a digital currency for the benefit of its dispersed island economies – essential to a region that has been disproportionately affected by climate change-induced disasters, governor Timothy Antoine tells fDi.

Long-dominant global supply chains look less tenable in the light of pressures ranging from pandemics to disasters, trade tensions and protectionism.

The UK is the top country, but Dublin is leading city, for foreign companies setting up headquarters in Europe, according to fDi’s ranking.

The coronavirus pandemic could change human behaviour more permanently in future.

Pedro Calado, vice-president of Madeira’s regional government, tells Sebastian Shehadi about the island's capacity for more upmarket tourism and its ongoing struggle to gain financial independence from Portugal. 

FDI project numbers from China into the EU are on a downward trend, but Europe is still a popular destination for Chinese investment.

Europe’s most well-known digital disruptor banks have been expanding across the globe, but not without some controversy. Alex Irwin-Hunt reports.