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This are the Errors i am getting can you please provide the solution.

Checking out license: Genus_Synthesis (12 seconds elapsed).
License 'Genus_Synthesis' (main version: 17.2, alternate version: 17.2) checkout failed.
Checking out license: Virtuoso_Digital_Implem (12 seconds elapsed).
License 'Virtuoso_Digital_Implem' (main version: 17.1, alternate version: 17.1) checkout failed.
Checking out license: Virtuoso_Digital_Implem_XL (12 seconds elapsed).
License 'Virtuoso_Digital_Implem_XL' (main version: 17.1, alternate version: 17.1) checkout failed.
Cannot obtain 'Genus_Synthesis' license.
Abnormal exit.

I have a technology library (given by foundry) with leLsw layer section defined.
I do not want to touch it

I added few layers with an ITDB approach. Now I'm unable to see the added layers, as it is not present in the leLsw layer section of the main techlib.

I want the user of the new techlib to see all the layers by default.(I don't want the users to go to the properties of palette and switch the display option to techfile layers instead of leLsw)

Hi,

i'm using spectre HB simulation on PA (Power Amplifier) test_bench to perform large signal analysis (i want to plot Output power vs intput power, PAE and Gain)

Although the simulation returns no error, i still can't plot anything. seem like there is an issue with the ports i'm using. (analoglib ports)

i attach an image of my configuration so maybe you can find something helpful in it. 

thank you all for your help

best regards

Hi All,

I want to capture the transition values of certain nodes in a design (i.e. a digital multiplier built with standard cells) and I use probe -screen command to dump the nodal values in text format. Since I only need to capture these values in the ideal situation, I use -nospecify switch with the xrun command :

xrun -clean R16FA_2009.v R4BE_Test.v tb_stop16.v -v stdlib_verilog_models-sdf30.v -access +rwc -mess -timescale 1ns/1ps -nospecify -gui &

and the probe command goes like this : 

probe -screen tb_stop16.mul16.test.L1 -redirect probe1.txt -format "%T L1 Value: %b"  //Here L1 is an array of wires

Although I expect a single transition at a given time instance, I see multiple transitions occurring in the dumped probe1.txt file. i.e. 

Time: 300 PS : 48'bxx0xx0xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0xx0xx11x
Time: 300 PS : 48'b000000000000000000000000000000000000000000000110
Time: 4 NS : 48'b001000000000000000000000000000000000000000000100
Time: 4 NS : 48'b011000000010111111111001000000110011011001010101
Time: 8 NS : 48'b010000000010111111111001000000110011011001010101
Time: 8 NS : 48'b110100101100000110000111100001010010111001011100
Time: 12 NS : 48'b010000110011100010001110011100010101010001010101
Time: 16 NS : 48'b000010000010000000000000000010000000010010010100
Time: 20 NS : 48'b000011000010000000000000000010000000010010010100
Time: 20 NS : 48'b000001001001001001011011000010001010011010010100

From the waveform, it appears that only the second value (bold)  of the time instance is correct. Since the simulation is without annotated delays, there are no intermediate transitions in the waveform. How could this be possible ?

Thanks in advance

Hello,

I find a strange issue when using design variable -> right-click -> copy from cellview in assembler. Cadence version is IC618-64b. 500.9

In fact, I set the value of variable (e.g., AAA = 100), then after I right-click -> copy from cellview, AAA's is updated to other value. In my opinion "copy from cellview" should only update the missing variable to the list, but not change any variable value. 

Is there any mechanism could change variable value when using "copy from cellview"?

Thanks

Optimizing power can be a very convoluted and crucial process. To make design chips meet throughput goals along with optimal power consumption, you need to plan right from the beginning! (read more)

Key Findings:  There are a host of issues that arise in mixed-signal verification.  As discussed in earlier blogs, the industry trends indicate that teams need to prepare themselves for a more mixed world.  The good news is that these top five pitfalls are all avoidable.

It’s always interesting to study the human condition.  Watching the world through the lens of mixed-signal verification brings an interesting microcosm into focus.  The top 5 items that I regularly see vexing teams are:

1. When there’s a bug, whose problem is it?
2. Verification team is the lightning rod
3. Three (conflicting) points of view
4. Wait, there’s more… software
5. There’s a whole new language

Reason 1: When there’s a bug, whose problem is it?

It actually turns out to be a good thing when a bug is found during the design process.  Much, much better than when the silicon arrives back from the foundry of course. Whether by sheer luck, or a structured approach to verification, sometimes a bug gets discovered. The trouble in mixed-signal design occurs when that bug is near the boundary of an analog and a digital domain.

Figure 1.   Whose bug is it?

Typically designers are a diligent sort and make sure that their block works as desired. However, when things go wrong during integration, it is usually also project crunch time. So, it has to be the other guy’s bug, right?

A step in the right direction is to have a third party, a mixed-signal verification expert, apply rigorous methods to the mixed-signal verification task.  But, that leads to number 2 on my list.

Reason 2: Verification team is the lightning rod

Having a dedicated verification team with mixed-signal expertise is a great start, but what can typically happen is that team is hampered by the lack of availability of a fast executing model of the analog behavior (best practice today being a SystemVerilog real number model – SV_RNM). That model is critical because it enables orders of magnitude more tests to be run against the design in the same timeframe. 

Without that model, there will be a testing deficit. So, when the bugs come in, it is easy for everyone to point their finger at the verification team.

Figure 2.  It’s the verification team’s fault

Yes, the model creates a new validation task – it’s validation – but the speed-up enabled by the model more than compensates in terms of functional coverage and schedule.

The postscript on this finger-pointing is the institutionalization of SV-RNM. And, of course, the verification team gets its turn.

Figure 3.  Verification team’s revenge

Reason 3: Three (conflicting) points of view

The third common issue arises when the finger-pointing settles down. There is still a delineation of responsibility that is often not easy to achieve when designs of a truly mixed-signal nature are being undertaken.  

Figure 4.  Points of view and roles

Figure 4 outlines some of the delegated responsibility, but notice that everyone is still potentially on the hook to create a model. It is questions of purpose, expertise, bandwidth, and convention that go into the decision about who will “own” each model. It is not uncommon for the modeling task to be a collaborative effort where the expertise on analog behavior comes from the analog team, while the verification team ensures that the model is constructed in such a manner that it will fit seamlessly into the overall chip verification. Less commonly, the digital design team does the modeling simply to enable the verification of their own work.

Reason 4: Wait, there’s more… software

As if verifying the function of a chip was not hard enough, there is a clear trend towards product offerings that include software along with the chip. In the mixed-signal design realm, many times this software has among its functions things like calibration and compensation that provide a flexible way of delivering guards against parameter drift. When the combination of the chip and the software are the product, they need to be verified together. This puts an enormous premium on fast executing SV-RNM.

Figure 5.   There’s software analog and digital

While the added dimension of software to the verification task creates new heights of complexity, it also serves as a very strong driver to get everyone aligned and motivated to adopt best known practices for mixed-signal verification.  This is an opportunity to show superior ability!

Figure 6.  Change in perspective, with the right methodology

Reason 5: There’s a whole new language

Communication is of vital importance in a multi-faceted, multi-team program.  Time zones, cultures, and personalities aside, mixed-signal verification needs to be a collaborative effort.  Terminology can be a big stumbling block in getting to a common understanding. If we take a look at the key areas where significant improvement can usually be made, we can start to see the breadth of knowledge that is required to “get” the entirety of the picture:

• Structure – Verification planning and management
• Methodology – UVM (Unified Verification Methodology – Accellera Standard)
• Measure – MDV (Metrics-driven verification)
• Multi-engine – Software, emulation, FPGA proto, formal, static, VIP
• Modeling – SystemVerilog (discrete time) down to SPICE (continuous time)
• Languages – SystemVerilog, Verilog, Verilog-AMS, VHDL, SPICE, PSL, CPF, UPF

Each of these areas has its own jumble of terminology and acronyms. It never hurts to create a team glossary to start with. Heck, I often get my LDO, IFV, and UDT all mixed up myself.

Summary

Yes, there are a lot of things that make it hard for the humans involved in the process of mixed-signal design and verification, but there is a lot that can be improved once the pain is felt (no pain, no gain is akin to no bugs, no verification methodology change). If we take a look at the key areas from the previous section, we can put a different lens on them and describe the value that they bring:

• Structure – Uniformly organized, auditable, predictable, transparency
• Methodology – Reusable, productive, portable, industry standard
• Measure – Quantified progress, risk/quality management, precise goals
• Multi-engine – Faster execution, improved schedule, enables new quality level
• Modeling – Enabler, flexible, adaptable for diverse applications/design styles
• Languages – Flexible, complete, robust, standard, scalability to best practices

With all of this value firmly in hand, we can turn our thoughts to happier words:

…  stay tuned for more!

 Steve Carlson

A deficiency in handling authentication and authorization has been found with Kguard 104/108/v2 models. While password-based authentication is used by the ActiveX component to protect the login page, all the communication to the application server at port 9000 allows data to be communicated directly with insufficient or improper authorization. Proof of concept exploit included.

scrrun.dll on Microsoft Windows 10 suffers from file creation, folder creation, and folder deletion vulnerabilities.

macOS and iOS have a vulnerability with ImageIO where memory safety issues occur when processing OpenEXR images.