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Coronavirus patient present in stadium during ICC Women’s T20 World Cup Final, says MCG, issues checklist

The MCG in its statement shared the Australian DHHS's recommendation for those who were seated in section N42 of the ground during Sunday’s ICC Women’s T20 World Cup Final.




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Coronavirus in India update: Indigo issues fresh cancellation, rescheduling rules, policy

Check latest flight ticket cancellation policy, fee, and rules of Indigo: For bookings made between March 9, 2020 till March 31, 2020, for any travel date, one can reschedule your journey multiple times, without paying any change fee.




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Coronavirus impact: Air India issues new flight cancellation, rescheduling advisory; check new rules

Air India has stated that if the flight is cancelled, flyers need not call Air India or Travel Agent through whom the tickets have been booked.




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Coronavirus lockdown: Airlines to not issue refunds for cancelled tickets, to offer free rescheduling instead; check terms

The airlines have said that they will not refund the money back for cancelled tickets and customers can get their tickets scheduled for the next available date.




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Vistara airlines issues inflight modifications to tackle Coronavirus infection; Read full list

The airline may make further changes in compliance with regulatory guidelines once they are finalized and notified, Vistara said in a statement.




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No Domestic flights till May 17! DGCA issues fresh circular as govt extends lockdown

Suspension of flight operations has been extended till May 17, the Director General of Civil Aviation (DGCA) said in a circular issued today.




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Defence, water issues and agriculture to top Narendra Modi’s agenda during Israel visit

Defence, water issues and agriculture will top the agenda of talks when Prime Minister Narendra Modi visits Israel next month.




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Mehbooba Mufti doesn’t meet PDP panel: Kashmir bigger than party issues

Underscoring that the situation in Kashmir is bigger than party issues, People’s Democratic Party (PDP) chief Mehbooba Mufti refused to meet a delegation of her party members.




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Webinar on Environment Law Practice, Issues and the role played by NGT

Conservation - Conversation 

with Mrs. Neelam Rathore, senior advocate, best known for speaking for the trees. She has a robust practice in NGT and can be credited for a huge load of carbon offset making the lives easier for thousands. 
 
A webinar on - 
ENVIRONMENT LAWS, ISSUES and the ROLE OF NGT!
 
Date - 24th April
Time- 11 AM -12:30 PM
 




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MP HC issues circular to expand matters to be heard in interim bail period

Subordinate Courts to conduct hearing of less urgent matter as well, says MP HC; interim bail period also extended by 45 days.A circular has been issued by the Madhya Pradesh High Court, to expand the Scope of matters to be heard by the lower courts




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Delhi Issues Orders For Functioning Of Permitted Economic Activities

The Delhi government on Friday issued orders directing all the district magistrates and deputy commissioners of police to ensure smooth running of all economic activities permitted during the...




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COVID-19 recovery: Govt issues new guidelines for discharging patients; check details

The Ministry of Health and Family Welfare has come up with some revised guidelines for discharging patients from healthcare facilities.




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Canada Holds the 131st Express Entry Draw and Issues 3,600 Invitations

IRCC conducted its 131st Express Entry draw, and has issued Invitations to Apply for 3,600 candidates on November 27th.  Features of the DrawHere the minimum score in the Comprehensive Ranking System stood at 471, which is lesser by one point…




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Ontario Issues 667 Invitations in Skilled Trades to Express Entry Candidates

The immigration authorities in Ontario held their largest draw on December 11th4wsqor 2019, and issued 667 Notifications of Interest to such candidates who had a profile in Express Entry Pool. This was the first draw in the Skilled Trades stream after…




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133rd Express Entry Draw of Canada Issues 3,200 Invitations

The immigration authorities in Canada conducted their 133rd Express Entry draw, within eight days of the earlier draw, and issued 3,200 Invitations to Apply, to the promising candidates, on December 19. The DetailsThere was a decline of three points…




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Saskatchewan Holds EOI Draw Targeting 96 Jobs and Issues 595 Invitations

The immigration authorities in Saskatchewan targeted 96 NOC codes and issued 595 invitations in their recent provincial draw for Expression of Interest draw on December 20. Saskatchewan Immigrant Nominee Program featured invitations in the provincial…




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134th Express Entry Draw Held in Canada - Issues 3,400 PR Invitations

On January 8th Canada held its First Draw in 2020 and Invited 3,400 Express Entry Candidates to get the PR. In this draw the minimum score of the Comprehensive Ranking System increased by four points to 473 in comparison to the earlier…




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Saskatchewan Holds A Draw and Issues Invitations to 308 Promising Candidates

The immigration officials of Saskatchewan issued 308 invitations that target 82 NOC codes in the first skilled worker draw for Expression of Interest draw in the present year on January 9th. This draw was held in Saskatchewan Immigrant Nominee Program…




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Ontario has Issued 7,391 Immigration Nominations in 2019

In 2019, Ontario has issued 7,391 nominations in its Ontario Immigrant Nominee Program as per an announcement. OINP had an initial allocation target standing 6,650, and in December 700 places were offered to it by IRCC. It included 41 nominations in…




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Alberta Provincial Draw Issues 150 Invitations to Express Entry Candidates

150 invitations were issued to Express Entry candidates to apply and seek the Alberta provincial nomination on January 9. The Candidates having a 350 CRS score received these NOIs.Through the Alberta Express Entry Stream the Alberta Immigrant Nominee…





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Foreign currency bond issues in India reaches record high

Foreign currency bond issues in India will reach record high in 2014: Moody's Report




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RBI issues norms for Gold Monetisation Scheme

RBI issues norms for Gold Monetisation Scheme (GMS), 2015




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RBI to issue Rs 1,000 banknotes with new design

RBI to issue banknotes of Rs 1,000 Denomination with new design




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Govt Issues Strict Warning Against Zoom App; Says It’s ‘Not Safe’, Issues Guidelines Of Usage

Govt of India has issued a strict warning against Zoom app, which has become India’s most downloaded app for March, even beating the likes of Whatsapp and Facebook, TikTok. Govt has issued guidelines on how to use this app, but more importantly, suggested not to use it. Govt of India: Zoom Is Unsafe After National […]

The post Govt Issues Strict Warning Against Zoom App; Says It’s ‘Not Safe’, Issues Guidelines Of Usage first appeared on Trak.in . Trak.in Mobile Apps: Android | iOS.




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License Issue

This are the Errors i am getting can you please provide the solution.

Checking out license: Genus_Synthesis (12 seconds elapsed).
License 'Genus_Synthesis' (main version: 17.2, alternate version: 17.2) checkout failed.
Checking out license: Virtuoso_Digital_Implem (12 seconds elapsed).
License 'Virtuoso_Digital_Implem' (main version: 17.1, alternate version: 17.1) checkout failed.
Checking out license: Virtuoso_Digital_Implem_XL (12 seconds elapsed).
License 'Virtuoso_Digital_Implem_XL' (main version: 17.1, alternate version: 17.1) checkout failed.
Cannot obtain 'Genus_Synthesis' license.
Abnormal exit.




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leLSW layer issue

I have a technology library (given by foundry) with leLsw layer section defined.
I do not want to touch it

I added few layers with an ITDB approach. Now I'm unable to see the added layers, as it is not present in the leLsw layer section of the main techlib.

I want the user of the new techlib to see all the layers by default.(I don't want the users to go to the properties of palette and switch the display option to techfile layers instead of leLsw)




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Spectre HB simulation issue

Hi,

i'm using spectre HB simulation on PA (Power Amplifier) test_bench to perform large signal analysis (i want to plot Output power vs intput power, PAE and Gain)

Although the simulation returns no error, i still can't plot anything. seem like there is an issue with the ports i'm using. (analoglib ports)

i attach an image of my configuration so maybe you can find something helpful in it. 

thank you all for your help

best regards




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Xcelium Probe -Screen Issue

Hi All,

I want to capture the transition values of certain nodes in a design (i.e. a digital multiplier built with standard cells) and I use probe -screen command to dump the nodal values in text format. Since I only need to capture these values in the ideal situation, I use -nospecify switch with the xrun command :

xrun -clean R16FA_2009.v R4BE_Test.v tb_stop16.v -v stdlib_verilog_models-sdf30.v -access +rwc -mess -timescale 1ns/1ps -nospecify -gui &

and the probe command goes like this : 

probe -screen tb_stop16.mul16.test.L1 -redirect probe1.txt -format "%T L1 Value: %b"  //Here L1 is an array of wires

Although I expect a single transition at a given time instance, I see multiple transitions occurring in the dumped probe1.txt file. i.e. 

Time: 300 PS : 48'bxx0xx0xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0xx0xx11x
Time: 300 PS : 48'b000000000000000000000000000000000000000000000110
Time: 4 NS : 48'b001000000000000000000000000000000000000000000100
Time: 4 NS : 48'b011000000010111111111001000000110011011001010101
Time: 8 NS : 48'b010000000010111111111001000000110011011001010101
Time: 8 NS : 48'b110100101100000110000111100001010010111001011100
Time: 12 NS : 48'b010000110011100010001110011100010101010001010101
Time: 16 NS : 48'b000010000010000000000000000010000000010010010100
Time: 20 NS : 48'b000011000010000000000000000010000000010010010100
Time: 20 NS : 48'b000001001001001001011011000010001010011010010100

From the waveform, it appears that only the second value (bold)  of the time instance is correct. Since the simulation is without annotated delays, there are no intermediate transitions in the waveform. How could this be possible ?

Thanks in advance




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FEV ISSUE

I see unmapped points (not-mapped) on both golden and revised side. These are all ddr scan latches.
 
Eg-
 
*/latch_lo_gt_ctech_customlib_ddr_scan_latch[156]/o_reg in golden
*/latch_lo_gt_ctech_customlib_ddr_scan_latch[156]_clock_scan_latch_dt/sttb_$U4/udp1/U$1 in revised
 
There are many not-mapped similar to above one.
 
Below renaming rule doesn’t seem to work
ren rule r1 "_clock_scan_latch_dt" "/o_reg" -rev
 
Could someone please help here?




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Design variable in assember -> copy from cell view issue

Hello,

I find a strange issue when using design variable -> right-click -> copy from cellview in assembler. Cadence version is IC618-64b. 500.9

In fact, I set the value of variable (e.g., AAA = 100), then after I right-click -> copy from cellview, AAA's is updated to other value. In my opinion "copy from cellview" should only update the missing variable to the list, but not change any variable value. 

Is there any mechanism could change variable value when using "copy from cellview"?

Thanks




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Are You Stuck While Synthesizing Your Design Due to Low-Power Issues? We Have the Solution!

Optimizing power can be a very convoluted and crucial process. To make design chips meet throughput goals along with optimal power consumption, you need to plan right from the beginning! (read more)




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Top 5 Issues that Make Things Go Wrong in Mixed-Signal Verification

Key Findings:  There are a host of issues that arise in mixed-signal verification.  As discussed in earlier blogs, the industry trends indicate that teams need to prepare themselves for a more mixed world.  The good news is that these top five pitfalls are all avoidable.

It’s always interesting to study the human condition.  Watching the world through the lens of mixed-signal verification brings an interesting microcosm into focus.  The top 5 items that I regularly see vexing teams are:

  1. When there’s a bug, whose problem is it?
  2. Verification team is the lightning rod
  3. Three (conflicting) points of view
  4. Wait, there’s more… software
  5. There’s a whole new language

Reason 1: When there’s a bug, whose problem is it?

It actually turns out to be a good thing when a bug is found during the design process.  Much, much better than when the silicon arrives back from the foundry of course. Whether by sheer luck, or a structured approach to verification, sometimes a bug gets discovered. The trouble in mixed-signal design occurs when that bug is near the boundary of an analog and a digital domain.


Figure 1.   Whose bug is it?

Typically designers are a diligent sort and make sure that their block works as desired. However, when things go wrong during integration, it is usually also project crunch time. So, it has to be the other guy’s bug, right?

A step in the right direction is to have a third party, a mixed-signal verification expert, apply rigorous methods to the mixed-signal verification task.  But, that leads to number 2 on my list.

 

Reason 2: Verification team is the lightning rod

Having a dedicated verification team with mixed-signal expertise is a great start, but what can typically happen is that team is hampered by the lack of availability of a fast executing model of the analog behavior (best practice today being a SystemVerilog real number model – SV_RNM). That model is critical because it enables orders of magnitude more tests to be run against the design in the same timeframe. 

Without that model, there will be a testing deficit. So, when the bugs come in, it is easy for everyone to point their finger at the verification team.


Figure 2.  It’s the verification team’s fault

Yes, the model creates a new validation task – it’s validation – but the speed-up enabled by the model more than compensates in terms of functional coverage and schedule.

The postscript on this finger-pointing is the institutionalization of SV-RNM. And, of course, the verification team gets its turn.


Figure 3.  Verification team’s revenge

 

Reason 3: Three (conflicting) points of view

The third common issue arises when the finger-pointing settles down. There is still a delineation of responsibility that is often not easy to achieve when designs of a truly mixed-signal nature are being undertaken.  


Figure 4.  Points of view and roles

Figure 4 outlines some of the delegated responsibility, but notice that everyone is still potentially on the hook to create a model. It is questions of purpose, expertise, bandwidth, and convention that go into the decision about who will “own” each model. It is not uncommon for the modeling task to be a collaborative effort where the expertise on analog behavior comes from the analog team, while the verification team ensures that the model is constructed in such a manner that it will fit seamlessly into the overall chip verification. Less commonly, the digital design team does the modeling simply to enable the verification of their own work.

Reason 4: Wait, there’s more… software

As if verifying the function of a chip was not hard enough, there is a clear trend towards product offerings that include software along with the chip. In the mixed-signal design realm, many times this software has among its functions things like calibration and compensation that provide a flexible way of delivering guards against parameter drift. When the combination of the chip and the software are the product, they need to be verified together. This puts an enormous premium on fast executing SV-RNM.

 


Figure 5.   There’s software analog and digital

While the added dimension of software to the verification task creates new heights of complexity, it also serves as a very strong driver to get everyone aligned and motivated to adopt best known practices for mixed-signal verification.  This is an opportunity to show superior ability!


Figure 6.  Change in perspective, with the right methodology

 

Reason 5: There’s a whole new language

Communication is of vital importance in a multi-faceted, multi-team program.  Time zones, cultures, and personalities aside, mixed-signal verification needs to be a collaborative effort.  Terminology can be a big stumbling block in getting to a common understanding. If we take a look at the key areas where significant improvement can usually be made, we can start to see the breadth of knowledge that is required to “get” the entirety of the picture:

  • Structure – Verification planning and management
  • Methodology – UVM (Unified Verification Methodology – Accellera Standard)
  • Measure – MDV (Metrics-driven verification)
  • Multi-engine – Software, emulation, FPGA proto, formal, static, VIP
  • Modeling – SystemVerilog (discrete time) down to SPICE (continuous time)
  • Languages – SystemVerilog, Verilog, Verilog-AMS, VHDL, SPICE, PSL, CPF, UPF

Each of these areas has its own jumble of terminology and acronyms. It never hurts to create a team glossary to start with. Heck, I often get my LDO, IFV, and UDT all mixed up myself.

Summary

Yes, there are a lot of things that make it hard for the humans involved in the process of mixed-signal design and verification, but there is a lot that can be improved once the pain is felt (no pain, no gain is akin to no bugs, no verification methodology change). If we take a look at the key areas from the previous section, we can put a different lens on them and describe the value that they bring:

  • Structure – Uniformly organized, auditable, predictable, transparency
  • Methodology – Reusable, productive, portable, industry standard
  • Measure – Quantified progress, risk/quality management, precise goals
  • Multi-engine – Faster execution, improved schedule, enables new quality level
  • Modeling – Enabler, flexible, adaptable for diverse applications/design styles
  • Languages – Flexible, complete, robust, standard, scalability to best practices

With all of this value firmly in hand, we can turn our thoughts to happier words:

…  stay tuned for more!

 

 Steve Carlson




issue

রিলায়েন্সের শেয়ারহোল্ডারদের জন্য সুখবর, Rights Issue-এর প্রস্তাব নিতে চলেছে সংস্থা




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Ubuntu Issues Security Patch For Kernel Flaw




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Microsoft Windows 10 scrrun.dll Active-X Creation / Deletion Issues

scrrun.dll on Microsoft Windows 10 suffers from file creation, folder creation, and folder deletion vulnerabilities.





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macOS / iOS ImageIO OpenEXR Image Processing Memory Issues

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Quantum Processor's Prime Feat Raises Security Issues




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Cisco Re-Issues Patch For High Severity WebEx Flaw




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Home Office Issued 10,000 Fake UK Passports Last Year





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Interpol Issues Arrest Warrant For Fake Passport Hit Team






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SoundCloud Tackles DoS, Account Takeover Issues