CSR Short Film Festival is corporate social responsibility intiative

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Best Indian Short Films - Six Sigma Films

As per the reports, the companies with a presence in China are back in business with easing of restrictions, while India extended its lockdown further till 3rd May.  How Are Things In China? The trade association Nasscom has said member companies across the sector are operating with almost 80% attendance. Basically, the lockdown in China […]

The post Indian IT Firms Doing Chinese Operations Is Working With 80% Capacity! Chinese Economy Back On Track? first appeared on Trak.in . Trak.in Mobile Apps: Android | iOS.

After the Government extended the lockdown to curb the spread of COVID-19 outbreak, the Ministry of Home Affairs (MHA) released a set of revised guidelines for services that are allowed during the lockdown. Several ecommerce companies including Flipkart, Snapdeal and Paytm Mall are all set to resume full operations from April 20. Read to find […]

The post Flipkart, Amazon, Paytm Mall, Snapdeal All Set To Sell Non-Essential Items From April 20th first appeared on Trak.in . Trak.in Mobile Apps: Android | iOS.

Williams will put safety first even though the team is one of several whose survival depends on Formula One starting racing again, deputy principal Claire Williams said.

Six organizations that aid survivors of domestic violence are among groups that will receive $50,000 each from Major League Baseball and the players' association as part of a Healthy Relationships Community Grant initiative.

Here's why Clemson, Ohio State, Oklahoma and 22 more teams will have the top offenses through the next three seasons.

Clemson softball players were upset their inaugural season ended due to the coronavirus pandemic, but they will remember it for starting traditions.

The 2020 UCLA Bruins might have been on pace for NCAA softball history, but they're not the only powerhouse team not to win a WCWS title.

Which NHL team has the deepest farm system? How about the weakest? Which are trending up or down? We reset the pipelines with prospect system superlatives.

We identify the top trios for each club, including best overall, cult classic and top current group. Let the debates begin!

Todd Gurley said "forget the Rams" and that he's not speaking with his former teammates until he gets the money he says the team still owes him.

Once while eating dinner in Montreal, our friendly, intoxicated waitress plopped herself in my lap and proceeded to tell us about how obsessed she was with the CD that was playing - singing out the lyrics at an ungodly volume and flinging her arms about. Wow, I thought to myself, people who listen to Morcheeba sure seem to have a lot of fun, and promised to check them out.

Several CDs later, they are firmly one of my favorites. And their trip hop meditation, 2003’s Charango remains one of my most played CDs.

Morcheeba (Mor = more, Cheeba = pot) are brothers Ross and Paul Godfrey with singer Skye Edwards (who has since been replaced). Part trance, part ambience, Charango is full of smooth, snogworthy jams. And just as you surrender to its seductive groove, Slick Rick shows up with a rap called “Women Lose Weight”.

Lamenting his wife putting on weight after having kids and stalled by his mistress who wants a clean break before she shacks up with him, he decides the easiest way out of it all is to kill the spouse. Considering different ways to do the deed, he finally rams his car into her Chevy over a long lunch break one fine day. It is an unexpected, stunning, tongue-in-cheek social commentary that makes it a CD you won’t forget easily.

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Hi Folks, Check out this great new video on YouTube: CDNLive SV 2014: PMC Improves Visibility and Performance with Spectre APS In this video from CDNLive Silicon Valley 2014, Jurgen Hissen, principal engineer, MSCAD, at PMC, discusses an aggressive...(read more)

Hello Spectre RF Users, Next week is my all time favorite technical conference - the International Microwave Symposium IMS2016 , May 22-27 in San Francisco, CA at the Moscone Center. If you're at the conference, please stop by the Cadence booth and...(read more)

Cadence ® Spectre ® AMS Designer is a high-performance mixed-signal simulation system. The ability to use multiple engines, and drive from a variety of platforms enables you to "rev...

[[ Click on the title to access the full blog on the Cadence Community site. ]]

Imagine you are on a vacation with your family, and suddenly, your phone starts buzzing. You pick it up and what are you looking at is a bunch of pending, unanswered e-mails. You start recollecting the checklist you had made before taking off only to realize that you haven’t put on the automatic replies! (read more)

xmsim is not exiting the simulation for this error. It is unusual for the simulator to not exit for an error. I have just started using uvm and this is occurring during the randomization step for a sequencer item.

xmsim: *E,RNDCNSTE

I am using -EXIT on the command line.

I am using Xcelium 19.03-s013.

Any insights are appreciated. Thanks.

-Jim

Hello,

I have a question I want to create a cover that consists a sparse values, pre-computed (a list or define) for example l = {1; 4; 7; 9; 2048; 700} I'd like to cover that data a (uint(bits:16)) had those values, Any suggestion on how to achieve this, I'd prefer to stay away from macros, and avoid to write a lot of code

struct inst {

  data :uint(bits:16);
  opcode :uint(bits:16);
  !valid_data : list of uint(bits:16) = {0; 12; 10; 700; 890; 293;};
  event data_e;
  event opcode_e;

  cover data_e is {
     item data using radix = HEX, ranges = {
     //I dont want to write all of this
     range([0], "My range1");
     range([10], "My range2");
     //... many values in between
    range([700], "My rangen");
    };

    item opcode;

   cross data, opcode;
};

post_generate() is also {
    emit data_e;
};
};

I'm trying to set up a VHDL-AMS simulation, so I made a new cell, selected the vhdlamstext type, and copied some example from the web. But when I hit the save and compile button, I first got the following NOLSTD error:

https://www.edaboard.com/showthread.php?27832-Simulating-a-VHDL-design-in-ldv5-1

So I added said file to my cds.lib and tried again. But now I'm getting this:

ncvhdl_p: *F,DLUNNE: Can't find STANDARD at /cadappl/ictools/cadence_ic/6.1.7.721/tools/inca/files/STD.

If I go over to the Library Browser, it indeed shows that the library is completely empty. Properties show it has the following files attached.

In the file system I've also found a STD.src folder. Is there a way to recompile the library properly? Supposedly this folder includes precompiled versions, but looks like not really.

The complexity and size of mixed-signal designs in wireless, power management, automotive, and other fast growing applications requires continued advancements in a mixed-signal verification methodology. An SoC, in these fast growing applications, incorporates a large number of analog and mixed-signal (AMS) blocks/IPs, some acquired from IP providers, some designed, often concurrently. AMS IP must be verified independently, but this is not sufficient to ensure an SoC will function properly and all scenarios of interaction among many different AMS IP blocks at full chip / SoC level must be verified thoroughly. To reduce an overall verification cycle, AMS IP and SoC verification teams must work in parallel from early stages of the design. Easier said than done! We will outline a methodology than can help.

AMS designers verify their IP meets required specifications by running a testbench they develop for standalone / out of-context verification. Typically, an AMS IP as analog-centric, hierarchal design in schematic, composed of blocks represented by transistor, HDL and behavioral description verified in Virtuoso® Analog Design Environment (ADE) using Spectre AMS Designer simulation. An SoC verification team typically uses UVM SystemVerilog testbech at full chip level where the AMS IP is represented with a simple digital or real number model running Xcelium /DMS simulation from the command line.

Ideally, AMS designers should also verify AMS IP function properly in the context of full-chip integration, but reproducing an often complex UVM SystemVerilog testbench and bringing over top-level design description to an analog-centric environment is not a simple task.

Last year, Cadence partnered with Infineon on a project with a goal to automate the reuse of a top-level testbench in AMS verification. The automation enabled AMS verification engineers to automatically configure setup for verification runs by assembling all necessary options and files from the AMS IP Virtuoso GUI and digital SoC top-level command line configurations. The benefits of this method were:

• AMS verification engineers did not need to re-create complex stimuli representing interaction of their IP at the top level
• Top-level verification stays external to the AMS IP verification environment and continues to be managed by the SoC verification team, but can be reused by the AMS IP team without manual overhead
• AMS IP is verified in-context and any inconsistencies are detected earlier in the verification process
• Improved productivity and overall verification time

For more details, please see Infineon’s CDNLlive presentation.

Typically, analog designers verify their AMS IP in schematic driven, interactive environment, while SoC designers use a UVM SystemVerilog testbench ran from a command line. In our last MS blog, we talked about automation for reusing SystemVerilog testbench by analog designers in order to verify AMS IP in exactly same context as in its SoC integration, hence reducing surprises and unnecessary iterations.

But, what about other direction: selecting proper AMS IP views for SoC Verification? Manually export netlist from Virtuoso and then manually assemble together all of the files for use with in command line driven flow? Often, there are multiple views for the same instance (RNM, analog behavioral model, transistor netlist). Which one to pick? Who is supposed to update configuration files? We often work concurrently and update the AMS IP views frequently. Obviously, manually selecting correct and most up-to-date AMS IP views for SoC Verification is tedious and error prone. Thanks to Cadence Innovation, there is a better way!

Cadence has developed a Command-Line IP Selector (CLIPS) product as part of the Virtuoso^® environment, which:

• Bridges the gap between MS SoC command-line setup and the Virtuoso-based analog mixed-signal configuration
• Allows seamless importing of AMS IP from the Virtuoso environment into an existing digital verification setup
• Provides a GUI-based and command-line use model, flexible to fit into an existing design flow methodologyCLIPS reads MS SoC command (irun) files, identifies required AMS IP modules, uses Virtuoso ADE setup files to properly netlist required modules, and pulls the AMS IP out of the Virtuoso environment. All necessary files are properly extracted/prepared and package as required for the MS SoC command line verification run. CLIPS setup can be saved and rerun as a batch process to ensure the latest IP from the hierarchy is being simulated.

For more details, please see CLIPS Rapid Adoption Kit at Cadence Online Support page

Introduction to AMSD Flex mode and its benefits.(read more)

This blog talks about how to enable the AMS Designer flex mode.(read more)

દિલ્હીની જવાહરલાલ નેહરૂ યુનિવર્સિટી પરિસરમાં દેશવિરોઘી સુત્રોચ્ચારના ઘેરા પ્રાત્યાઘાતો દેશભરમાં પડ્યા છે, ત્યારે અચાનક જ એમ.એસ યુનિવર્સિટીની ફાઇન આર્ટ્સ ફેકલ્ટીના કેન્ટીન પાસે જેએનયુ સબંધિત પોસ્ટર લગાડવામાં આવ્યા હતા.

વડોદરાની MS યૂનિવર્સિટી ફરી એક વખત વિવાદમાં આવી છે. ટેકનોલોજી ફેકલ્ટીમાં આવેલી એપ્લાઈડ મિકેનિકસના હેડ તરીકે જુનિયર પ્રોફેસરની વરણી સિન્ડિકેટની બેઠકમાં કરાતા વિવાદ ઉભો થયો છે.

વડોદરાની વિશ્વવિખ્યાત એમ એસ યુનિવર્સિટી ફરી એક વખત વિવાદમાં આવી છે. હોસ્ટેલના વિધાર્થીઓ એ ઉગ્ર રજૂઆત કરતા પોલીસ અને વિદ્યાર્થીઓ વચ્ચે સામાન્ય ઘર્ષણ થયું. વિદ્યાર્થીઓ વિજિલન્સના સભ્યો દ્વારા માર મારવાનો આરોપ લગાવી વીસીને રજૂઆત કરવા ગયા હતા.

છેલ્લા કેટલાક સમયથી વડોદરાની મહારાજા સયાજીરાવ યુનિવર્સિટી વિવાદોમાં રહ્યાં કરે છે. વિદ્યાર્થીઓ વચ્ચે યુનિવર્સિટી પરિસરમાં હિંસક ઘટનાઓ, હોસ્ટેલમાં દારૂની મેહફિલ માણતા વિદ્યાર્થીઓ, પ્રોફેસરોની નિમણુંકનો વિવાદ, બાદ હવે આજે ફેકલ્ટી ઓફ ટેકનોલોજીનાં પરિસરમાં ડસ્ટબિન માંથી વિદ્યાર્થીઓની ઉત્તરવહીનો જથ્થો મળી આવતા ફરી એક લાપરવાહીની મામલો સામે આવ્યો છે.

વડોદરાની વિશ્વવિખ્યાત મહારાજા સયાજીરાવ યુનિવર્સિટીમાં એક પછી એક નવા વિવાદો સામે આવી રહ્યાં છે. ટેકનોલોજી ફેકલ્ટીના એપ્લાઈડ મિકેનિકસ વિભાગના હેડની વરણીનો વિવાદ હજી સમ્યો નથી કે. એમ એસ યુનિવર્સિટીના સિન્ડીકેટ સભ્યો દ્વારા 11મી માર્ચથી ઉજવનારા સયાજી લિટરેચર ફેસ્ટીવલ સામે પૂર્વ વિદ્યાર્થી અગ્રણીઓએ વિરોધ નોંધાવતા નવો વિવાદ ઉભો થયો છે.

દિલ્હીની જેએનયુમાં વિદ્યાર્થીઓના આઝાદી આંદોલનની આગ સમગ્ર દેશમાં પ્રસરી છે, ત્યારે વડોદરાની એમ એસ યુનિવર્સિટીમાં પણ આઝાદી આંદોલનના એંધાણ વર્તાઈ રહ્યાં છે. યુનિવર્સિટીના અધ્યાપકોએ યુનિવર્સિટીમાં કોઈ પણ વ્યકિતની આઝાદી ન હોવાનો તેમજ યુનિવર્સિટીમાં થતી નિમણૂંકોમાં આરએસએસની દખલગીરી હોવાનો ગંભીર આરોપ લગાવ્યો છે.

અંબાલાની સ્કૂલનો પટાવાળો કમલ એમએસસી છે પરંતુ સરકારી નિયમ પ્રમાણે તે વિદ્યાર્થીઓને ભણાવી શકે નહીં.

લૉકડાઉન પુરૂં થતાની સાથે જ ટેલિવિઝન અને અન્ય ડિજિટલ એપ્લાયન્સ પર આજે અનેક લોભામણા ઓફરની જાહેરાત કરી છે.

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