While Devika Bhise had earlier delighted fans by sharing a few snaps from the wedding day and pre-wedding functions on Instagram, designer Anita Dongre took to Instagram this morning to give them...

The Google Play store is full of awesome apps that can help you with tasks or simply help you take a break and relax with an engaging game. This article consolidates the Apps and Games we highlighted for the month of April. Scroll through to find a couple of new options we think you will ...

When it comes to flagship chipsets for Android phones, Qualcomm is typically regarded as being the top contender with its 800-series processors. That being said, MediaTek has been playing an incredible catchup game as of late with the Dimensity 1000 in late 2019 which put it within a striking range of the new Snapdragon 865 ...

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Dr. Scott A. Brown, Vice President of External Innovation, Veterinary Medicine Research & Development at Zoetis, shares Zoetis approach to research alliances with organizations and companies across the pharmaceutical, biotechnology, agribusiness and animal health industries and describes the company’s research areas of interest.

Winds are from the West at 20.7 gusting to 34.5 MPH (18 gusting to 30 KT). The pressure is 1009.0 mb and the humidity is 41%. The wind chill is 33. Last Updated on May 9 2020, 11:53 am EDT.

Smart Lock Company LockState raised $5.8M Series A in new investment to fund its aggressive sales and marketing and partner development plan. The company previously raised $740K seed round and $1M in a round led by angel investors. The lead investor in latest round was Iron Gate Capital. Other investors include Kozo Keikaku Engineering Inc, Nelnet and Service Provider Capital.

The company’s Wi-Fi-enabled RemoteLock is used by 1000s of Airbnb and other vacation rental hosts. It helps hosts remotely provide access to guests. Locking/unlocking codes can be generated via a host’s computer or smartphone.

RemoteLock’s prices start at $299 which is its algorithmic ResortLock. The most pricey lock by LockState is its ‘RemoteLock 7i Black WiFi Commercial Smart Lock’ which costs $479.

Another core product of LockState is its cloud-based remote access platform for internet-enabled locks. It implies users can remotely manage their (internet-enabled) locks via LockState’s cloud platform.

Unlike smartphones and watches, customers don’t look forward to upgrading their smart locks or buying one when new models are launched. Thus, smart lock companies offset this disadvantage by partnering with property management and short-term rental companies to get new customers.

LockState has partnered with vacation rental brands like Airbnb, HomeAway, and other listing partners to automate guest access.

Igloohome a Singapore-based smart lock company also raised an investment of $4M in April this year.

[RFI] South Africa's government will assist the authorities in Madagascar to test and analyse an unproven herbal treatment for Covid-19, according to health minister Zweli Mkhize. Madagascar's President Andry Rajoelina is promoting a tea infusion based on the artemisia plant, praising its benefits in treating the coronavirus.

[News24Wire] Police have launched a manhunt for the perpetrators of the murder of an 89-year-old woman in an old age home in Queenstown in the Eastern Cape.

Top international basketball prospect Rati Andronikashvili has committed to Creighton, he told ESPN on Thursday.

The latest on stock market and business news during the coronavirus outbreak.

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Officials in India’s capital have imposed a special tax of 70% on retail alcohol purchases to deter large gatherings at stores as authorities ease a six-week lockdown imposed to slow the spread of coronavirus.

Taxes on alcohol are a key contributor to the revenue of many of India’s 36 states and federal territories, most of which are running short of funds because of the lengthy disruption in economic activity caused by the virus.

It was a beautiful Saturday afternoon as the Indians prepared to take on the Robert Morris Eagles for Haskell Football's Home Opener. This would be the second time the Indians would take on the Illinois team. The Indians lost in their first match-up against the Eagles in 2011, which would play a recognizable tune in 2012.

Bettendorf, Iowa – The Haskell men's cross country team finished in 4th place with 102 points at the Association of Independent Institutions Cross Country Championships on Saturday.

Capitals forward Brendan Leipsic and Panthers prospect Jack Rodewald were both condemned by the NHL over "misogynistic and reprehensible" comments made on social media.

The Washington Capitals placed forward Brendan Leipsic on waivers for the purpose of terminating his contract.

Haskell women's volleyball will travel to Lincoln College today to participate in pool play Friday 11/15/19!

Brett Favre on Friday disputed a Mississippi state auditor's report that said the Hall of Fame quarterback received $1.1 million in welfare money for multiple speaking engagements that he didn't actually attend.

Haskell will play host to the 2014 Midlands Collegiate Athletic Conference Outdoor Track and Field Championships on April 25th and 26th. 

Test chips are becoming more widespread and more complex at advanced process nodes as design teams utilize early silicon to diagnose problems prior to production. But this approach also is spurring questions about whether this approach is viable at 7nm and 5nm, due to the rising cost of prototyping advanced technology, such as mask tooling and wafer costs.

Semiconductor designers have long been making test chips to validate test structures, memory bit cells, larger memory blocks, and precision analog circuits like current mirrors, PLLs, temperature sensors, and high-speed I/Os. This has been done at 90nm, 65nm, 40nm, 32nm, 28nm, etc., so having test chips at 16nm, 7nm, or finer geometries should not be a surprise. Still, as costs rise, there is debate about whether those chips are over-used given advancements in tooling, or whether they should be utilized even more, with more advanced diagnostics built into them.

Modern EDA tools are very good. You can simulate and validate almost anything with certain degree of accuracy and correctness. The key to having good and accurate tools and accurate results (for simulation) is the quality of the foundry data provided. The key to having good designs (layouts) is that the DRC deck must be of high quality and accurate and must catch all the things you are not supposed to do in the layout. Most of the challenges in advanced node is in the FEOL where semiconductor physics and lithography play outsize roles. Issues that were not an issue at more mature nodes can manifest themselves as big problems at 7nm or 5nm. Process variation across the wafer and variation across a large die also present problems that were of no consequence in more mature nodes.

The real questions to be asked are as follows:

What is the role of test chips in SoC designs?

1. Do all hard IP require test chips for validation?
2. Are test chips more important at advanced nodes compared to more mature nodes?
3. Is the importance of test chip validation relative to the type of IP protocols?
4. What are the risks if I do not validate in silicon?

In complex SoC designs, there are many high-performance protocols such as LPDDR4/4x PHY, PCIe4 PHY, USB3.0 PHY, 56G/112G SerDes, etc. Each one of these IP are very complex in and by itself. If there is any chance of failure that is not detected prior to SoC (tapeout) integration, the cost of retrofit is huge. This is why the common practice is to validate each one of these complex IP in silicon before committing to use such IP in chip integration. The test chips are used to validate that the IP are properly designed and meet the functional specifications of the protocols. They are also used to validate if sufficient margins are designed into the IP to mitigate variances due to process tolerances. All high-performance hard IP go through this test chip/silicon validation process. Oftentimes, marginality is detected at this stage. In advanced nodes, it is also important to have the test chips built under different process corners. This is intended to simulate process variations in production wafers so as to maximize yields. Advanced protocols such as 112G, GDDR6, HBM2, and PCIe4 are incredibly complex and sensitive to process variations. It is almost impossible to design these circuits and try to guarantee their performance without going through the test chip route.

Besides validating performance of the IP protocols, test silicon is also used to validate robustness of ESD structures, sensitivity to latch up, and performance degradation over wide temperature ranges. All these items are more critical in advanced nodes than more mature modes. Test chips are vehicles to guarantee design integrity in bite-size chunks. It is better to deal with any potential issues in smaller blocks than to try to fix them in the final integrated SoC.

Test chips will continue to play a vital role in helping IP and SoC teams lower the risk of their designs, and assuring optimal quality and performance in the foreseeable future. They are not going away!

To read more, please visit https://semiengineering.com/test-chips-play-larger-role-at-advanced-nodes/

PCIe has been widely adopted in the electronics industry since its first debut in 2003 (PCIe 1.0 standard release) for wide breach of applications, from Data Center Server, Networking, to Mobile, AI/ML, Automotive, IoT, and many others…. It’s a versatile, high-performance, robust, mature interconnect standard with full “backward compatibility” (e.g., a PCIe 3.0 device can still function well in a PCIe 4.0 system) which enables a solid and strong PCIe eco-system in the industry.  While the market, so as the users,  are enjoying the systems, e.g., desktop/laptop, powered (or to be more specific: “bridged”) by PCIe 3.0 since 2010, the industry is pushing hard for the PCIe 4.0 eco-system enablement. Earlier this year, AMD announced it X570 chipset would support the PCIe 4.0 interface and Phison also introduced the world’s first PCIe 4.0 SSD.

On the standard evolution front, the official PCIe 5.0 came out in May 2019, doubling the data rate to 32GT/s from 16GT/s in PCIe 4.0. The PCIe 6.0 standard will be released in 2021 based on the announcement made by PCI-SIG in June’19 with the goal to further double the data rate to 64GT/s with incorporating the PAM4 coding.

PCIe Protocol Evolution

Having said that, is the latest generation of PCIe always desired?  

My answer would be positive. Just like car maker/enthusiast has kept pursuing faster car in the history, there is no doubt that these speed enhancements/upgrades in the electronic world certainly provide a tremendous benefit for especially those applications craving the most throughput, such as Data center, HPC, Networking, Cloud and AI applications.   

But, does every application have to opt for the fastest speed (bandwidth)? My view would be leaning toward “Not really”. Just like we don’t need a 3-second sport car (meaning 0-60mph acceleration < 3s) for daily commute though it would certainly spice some driving fun on the road, but it may not be "the best fit" for most of commuters.

There are applications still well satisfied with PCIe 3.0 (or even older PCIe 2.0) for its best performance and cost balance.  Those applications include, but not limit to, IoT/consumer, Edge AI, SSD (non-enterprise),…etc. They typically need to make trade-off in between the cost, power consumption (especially battery powered), flexibility on changing product features, and time-to-market (TTM). To address such type of market needs, Cadence also offers an PPA (Performance, Power, Area) optimized PCIe 3.0 solution in addition to its high-performance PCIe 4.0 product line.

Cadence PCIe 3.0 PHY Solution (with Multi-Protocol Multi-Link feature)

With leveraging the multi-protocol SerDes implementation, the same Cadence PHY IP support multi-protocol and multi-link operation. Such a multi-protocol enabled PHY gives the SoC developers the optimum flexibility to integrate multiple commonly used interface protocols (e.g., PCIe 3.0 + USB 3.0) with using only a single PHY design.  This would largely save the product development time (faster TTM), reduce the risk of using multiple different PHY instances (for different protocol needs), and with the configurability to enable different product features/protocols.

Some people might say PCIe 3.0 era has gone. I was not quite yet being convinced as I still see its potential to shine a lot of market use cases. What do you think?

More Information

For more information on Cadence's PCIe IP offerings, see our PCI Express page.

For more information on PCIe in general, and on the various PCI standards, see the PCI-SIG website.

Related Posts

• Blog: PCIe Gen4: It’s Official, We’re Compliant
• Blog: The PCIe 4.0 Era Continues at PCI-SIG Developers Conference 2016
• Blog: Cadence PCIe Solutions: Configurable, Compliant, and Low Power

Hi Folks, A question that I've often received from designers, "Is there a method to determine the amount of memory required before I submit a job? I use distributed processing and need to provide an estimate before submitting jobs." The answer...(read more)

It’s always good to hear what real users think of products. Here is a very detailed review (~4000 words) by an Anonymous user, nick named Ant-Man (from the movie). Overall it’s a very strong endorsement of Perspec, and summarize...(read more)

There’s nothing like the heat of a DAC demo to stress new technology and the engineers behind it! Such was the case at DAC 2018 at the new locale of Moscone Center West, San Francisco. Cadence and AMIQ were two of several vendors who announced ...(read more)

Cadence continues to be a leader in SoC verification and has expanded our industry investment in Accellera portable stimulus language standardization. Some customers have expressed reservations that portable stimulus requires the effort of learn...(read more)

A little bit of everything in the blog today: PSS is All Over As someone that was involved with UVM and PSS, both becoming Accellera standards, it is exciting to see both growing independently and together. With PSS we had a massive amount of papers ...(read more)

You can't read anything about technology these days without reading about 5G. But before there was 5G, there was 4G. And before that 3G, 2G, and 1G. A 0G even. For the next few Thursdays,...

[[ Click on the title to access the full blog on the Cadence Community site. ]]

Longfellow's metaphorical footprints on the sands of time is more profound and eternal no doubt but a footprint for silicon (a form of sand isn't it?) is as important for PCB designers. So, here we will list the steps to create a fo...(read more)

In my previous blog, I talked about creating a footprint using an existing template in Allegro ECAD-MCAD Library Creator and explained how easily you can access an existing template and create a package from it by just clicking a button. In this blog...(read more)

Hello,

Would anyone know how to setup a PSS or QPSS simulation with 25% dutycycle clock sources or if such a thing is possible with QPSS.

Fig1 (below) is a snapshot of the circuit I am trying to characterize. This has 4 clock ports each with 25%duty cycle in the ON state. Fig2 below shows two of these clocks.

Each path in the circuit consists of two switches with a low pass RC sandwiched in between. The Input is a 50Ohm port sine wave and the output is a 1K resistor. The output nets of all paths are connected together.

I am trying to determine the swept frequency response from input to output (voltage) when the input is from 500Mhz to  510MHz. The Period (T=1/Fp) of each of the pulses is such that Fp=500MHz. The first pulse source has a delay=0, second has delay=T/4, third delay=2T/4, etc...

I am currently getting it working and seeing the correct result (bandpass response) with Transient but the problem is doing a dft at 500MHz with 10KHz spacings needs at least 100us and takes up a lot of time and disk space.

Many Thanks,
Chris.

Fig1

Fig2

They say Moore's law is slowing. It may be slowing but it is still running - it has not stopped! And, it has been running at full throttle for quite a few decades now.  The net result of this run? Well, you can't design ICs in isolation from the...(read more)

I would like to add these components to the component bank in ORCAD simulation. Even an accessible or free course that explained how to create these components.

Hello All,

I'm currently using OrCAD PCB Designer Professional w/ PSpice (version 16.6-2015).  In the 'Design Object Find Filter' side bar, all options are grayed out and unselectable.  I did attempt to 'Reset UI to Cadence Default' without any luck.  A colleague has no issues with the identical file on his computer.  Any guidance would be much appreciated.  Thanks!

George

Hi,

I have a new customer that uses Allegro Design entry HDL for the schematic and have a few questions.

1. How do you get pin/gate swaps into the symbols in the schematic ?

2. How do you transfer them to the pcb editor ?

3. How do you back annotate the swaps from the pcb editor to the schematic ?

4. How do you stop the export/Import physical from updating the constraints in the pcb file ? 

Hello,

I would like to simulate the PSSR+/PSSR- and the CMMR using xf for the attached test bench.

Normally, I do the AC analysis and using the post-processing capability of cadence spectre I do 20log(vdd/vout) for PSSR+

and 20*log(vss/vout) for PSSR-. 

looked online from an old post that I do:

PSRR-
db20(1/DATA("/Vn/PLUS" "xf-xf"))

PSRR+
db20(1/DATA("/Vp/MINUS" "xf-xf"))

How about the for the CMRR?

Thanks a lot in advance.  

Cadence_SPB_17.4-2019 + Matlab R2019a

请参考本文档中的步骤进行操作

1，打开BJT_AMP.opj

2，设置Matlab路径

3，打开BJT_AMP_SLPS.slx

4，打开后，设置PSpiceBlock，出现或CEFSimpleUI.exe停止工作

5，添加模块

6，相同

7，打开pspsim.slx

8，相同

9，打开C： Cadence Cadence_SPB_17.4-2019 tools bin

orCEFSimpleUI.exe和orCEFSimple.exe

10，相同

我想问一下如何解决，非常感谢！

Bumps are central to the Virtuoso MultiTech Framework solution. Bumps provide a connection between stacked ICs, interposers, packages, and boards. Bump locations, connectivity, and other attributes are the basis for creating TILPs, which we combine to create system-level layouts.(read more)

If you have one of those Die layouts, which doesn’t have bumps, but rather uses pad shapes and labels to identify I/O locations, then you might be feeling a bit left out of all of this jazz and tango. Hence, today, I am writing to tell you that, fear not, we have a solution for your Die as well.(read more)

પાલનપુરઃ ગુજરાત ભરમાં ક્ષત્રિય ઠાકોર સેના દ્વારા વ્યસનમુક્તિ અભિયાન ચલાવવામાં આવી રહ્યુ છે.થોડાક દિવસ અગાઉ બનાસકાંઠાના ક્ષત્રીય ઠાકોર સેના દ્વારા વડગામ તાલુકાના સમશેરપુરા ગામમાં જનતા રેડ કરવામાં આવી હતી. જે દરમિયાન પોલીસે ક્ષત્રીય ઠાકોર સેનાના 12 જેટલા કાર્યકરોની અટકાયત કરી હતી.જેને લઈને આજે અલ્પેશ ઠાકોરે પાલનપુર સર્કિટ હાઉસ પહોંચ્યા હતા અને પત્રકારોને સંબોધ્યા હતા.

ભગવાનઅને સંત આપણને સંસારમાંથી છોડાવવા માટે જે પ્રયત્ન કરે તે આપણને દુઃખ જેવું લાગે, તોપણ તે તેઓનું આપણા પરનું હેત છે.

ગરમીમાં પંખો કે A.C. બંધ થઈ જાય તો પણ આપણે અકળાઈ ઊઠીએ છીએ. આ આપણી વાસ્તવિકતા છે.