A Bengaluru couple found themselves in legal trouble after they posted videos of their balcony garden on Facebook. The posts included images of plants later identified as ganja.

Rajya Sabha MP Raghav Chadha marked his 36th birthday in Varanasi.

Police on Monday arrested Manisha, wife of jailed gangster Kaushal Chaudhary, for allegedly trying to extort Rs 2 crores from a hotel owner, officials said.

On February 4, 2019, gloom settled over the iconic Brigade Parade grounds in the heart of Kolkata. Kanhaiya Kumar, then a firebrand Left leader known for his rousing speeches, had cancelled his visit to a rally just before the Lok Sabha election

Your sweet tooth could depend on your ability to digest sugar  BBC Science FocusView Full coverage on Google News

1. Ricky Ponting hits back at Gautam Gambhir, calls him 'prickly character'  The Times of India
2. Ricky Ponting Fires Back At Gautam Gambhir After India Coach's Press Conference Remarks  NDTV Sports
3. A fired-up Virat Kohli is Australia's worry after Ricky Ponting's 'bad move'  The Times of India
4. Gambhir a prickly character, never took dig at Kohli: Ponting  The Hindu
5. Border-Gavaskar Trophy: Why Gautam Gambhir comes across as abrasive at times  The Indian Express

1. Garena Free Fire MAX redeem codes for November 13, 2024: Win bundles, new outfits, and more rewards...  Moneycontrol
2. Garena Free Fire MAX redeem codes for November 12, 2024: Win free gifts, rewards, and know how to redeem...  Moneycontrol
3. Garena Free Fire MAX redeem codes for November 13: Win free in-game rewards daily  The Times of India
4. Garena Free Fire MAX Redeem Codes Today, November 13: Win Free Gifts, Skins And Much More  Jagran English
5. Garena Free Fire MAX November 13 redeem codes: All about Booyah Top-Up event  HT Tech

1. Battered Reliance Shares To Make A Comeback? This Analyst Sees 29% Upside Ahead  Benzinga India
2. Reliance Industries shares may see 30% upside according to CLSA, who cites this key trigger  CNBCTV18
3. RIL shares are down 20% from record high, oversold on charts; here's what analysts say  Business Today
4. Six of India’s top 10 most valuable firms shed Rs 1.55 lakh crore in market value  Moneycontrol
5. Reliance Industries Share Price Today on 13-11-2024: Reliance Industries share price are down by -0.63%, Nifty down by -0.8%  Mint

1. Inflation in nearly half of major states outgrows India's Oct CPI; price pressure steepest in Chhattisgarh  Moneycontrol
2. Retail inflation surges to a 14-month high of 6.2% in October  The Times of India
3. If we exclude vegetable prices, CPI inflation remains in RBI's range: UBI research  The Economic Times
4. Rising food prices are likely to push back beginning of rate cutting cycle  The Indian Express
5. India confident of reaching USD 100 billion trade volume with Russia ahead of 2030 timeline: S Jaishankar  Telegraph India

1. Telangana train accident: Goods train derails near Peddapalli. Check full list of cancelled, diverted trains today | Today News  Mint
2. Goods train derails in Telangana's Peddapalli; 20 trains cancelled, 10 diverted  The Economic Times
3. 11 coaches of goods train derail in Telangana  The Times of India
4. Goods train derailment in Telangana affects rail traffic between Delhi and Chennai  Telangana Today
5. Goods train derails in Telangana's Peddapalli; 30 trains cancelled, several diverted  The Hindu

1. BREAKING| 'Bulldozer Reminds Of Lawlessness' : Supreme Court Says Properties Can't Be Demolished Merely...  Live Law - Indian Legal News
2. "Officials To Pay From Salary": Top Court Guidelines On 'Bulldozer Justice'  NDTV
3. ‘Heavens won’t fall on authorities if they hold their hands for some period’: SC sets pan India guidelines against bulldozer action  The Financial Express
4. Executive Can't Become Judge, Pronounce Guilt Of Persons & Punish Them By Demolishing Their Properties :...  Live Law - Indian Legal News
5. ‘Officials will pay for demolitions from their salary’: 5 Key SC observations on ‘chilling’ side of ‘bulldozer justice’  Mint

According to the latest rumors, the Samsung Galaxy Z Flip FE could be powered by the Exynos 2400 chipset which is surprising.

The post Samsung Galaxy Z Flip FE chipset of choice could surprise you appeared first on Phandroid.

Samsung is running some Black Friday deals for its foldables like the Galaxy Z Fold 6 and Flip 6, so what are you waiting for?

The post Grab the Samsung Galaxy Z Fold 6 and Flip 6 at incredible Black Friday prices! appeared first on Phandroid.

If you’re in the market for a new Android tablet, check out these early Black Friday deals for the Samsung Galaxy Tab S10 series.

The post Check out these Samsung Galaxy Tab S10 early Black Friday deals and SAVE BIG! appeared first on Phandroid.

Shared by Gator Boys star Paul Bedard, the viral video shows the alligator emerging from his den to the tune of the iconic song.

A Bengaluru-based entrepreneur recently took to social media to jokingly explain how his daily commute on bike taxes in the city doubles as an unexpected fitness routine.

A man recently took to Reddit, seeking help identifying an unknown Devanagari text he found at a flea market in Germany.

The post has sparked a heated debate about Bengaluru's rising rental prices and the need for a cap on deposits.

[SAPS] - Five suspects are appearing in the Kariega Magistrate's Court today, after they were arrested and found in possession of cycads with an estimated value of R1 Million on Friday 08 November 2024.

[Premium Times] In September, Tyla made headlines at the MTV Video Music Awards (VMAs) for winning the "Best Afrobeats," but she stirred debate by clarifying that she identified with the Amapiano genre rather than Afrobeats

[State Department] U.S. Ambassador-at-Large to Monitor and Combat Trafficking in Persons Cindy Dyer will travel to Madagascar November 13-16 and South Africa November 17-21.

[Daily Maverick] Water and Sanitation Minister Pemmy Majodina held an urgent meeting on Sunday with Gauteng Premier Panyaza Lesufi and Johannesburg Mayor Dada Morero to address severe water shortages affecting Johannesburg communities.

[allAfrica]

In the rapidly evolving landscape of automotive electronics, traditional monolithic design approaches are giving way to something more flexible and powerful—chiplets. These modular microchips, which are themselves parts of a whole silicon system, offer unparalleled potential for improving system performance, reducing manufacturing costs, and accelerating time-to-market in the automotive sector. However, the transition to working with chiplets in automotive electronics is not without its challenges.

Designers must now grapple with a new set of considerations, such as die-to-die interconnect standards, complex processes, and the integration of diverse IPs. Advanced toolsets and standardized design approaches are required to meet these challenges head-on and elevate the potential of chiplets in automotive innovation. In the following discourse, we will explore in detail the significance of chiplets in the context of automotive electronics, the obstacles designers face when working with this paradigm, and how Cadence comprehensive suite of IPs, tools, and flows is pioneering solutions to streamline the chiplet design process.

Unveiling Chiplets in Automotive Electronics

For automotive electronics, chiplets offer a methodology to modularize complex functionalities, integrate different chiplets into a package, and significantly enhance scalability and manufacturability. By breaking down semiconductor designs into a collection of chiplets, each fulfilling specific functions, automotive manufacturers can mix and match chiplets to rapidly prototype new designs, update existing ones, and specialize for the myriad of use cases found in vehicles today.

The increasing significance of chiplets in automotive electronics comes as a response to several industry-impacting phenomena. The most obvious among these is the physical restriction of Moore's Law, as large die sizes lead to poor yields and escalating production costs. Chiplets with localized process specialization can offer superior functionality at a more digestible cost, maintaining a growth trajectory where monolithic designs cannot. Furthermore, chiplets support the assembly of disparate technologies onto a single subsystem, providing a comprehensive yet adaptive solution to the diverse demands present in modern vehicles, such as central computing units, advanced driver-assistance systems (ADAS), infotainment units, and in-vehicle networks. This chiplet-based approach to functional integration in automotive electronics necessitates intricate design, optimization, and validation strategies across multiple domains.

The Complexity Within Chiplets

Yet, with the promise of chiplets comes a series of intricate design challenges. Chiplets necessitate working across multiple substrates and technologies, rendering the once-familiar 2-dimensional design space into the complex reality of multi-layered, sometimes even three-dimensional domains. The intricacies embedded within this design modality mandate devoting considerable attention to partitioning trade-offs, signal integrity across multiple substrates, thermal behavior of stacked dies, and the emergence of new assembly design kits to complement process design kits (PDKs).

To effectively address these complexities, designers must wield sophisticated tools that facilitate co-design, co-analysis, and the creation of a robust virtual platform for architectural exploration. Standardizations like the Universal Chip Interconnect Express (UCIe) have been influential, providing a die-to-die interconnect foundation for chiplets that is both standardized and automotive-ready. The availability of UCIe PHY and controller IP from Cadence and other leading developers further eases the integration of chiplets in automotive designs.

The Role of Foundries and Packaging in Chiplets

Foundries have also pivoted their services to become a vital part of the chiplet process, providing specialized design kits that cater to the unique requirements of chiplets. In tandem, packaging has morphed from being a mere logistical afterthought to a value-added aspect of chiplets. Organizations now look to packaging to deliver enhanced performance, reduced power consumption, and the integrity required by the diverse range of technologies encompassed in a single chip or package. This shift requires advanced multiscale design and analysis strategies that resonate across a spectrum of design domains.

Tooling Up for Chiplets with Cadence

Cadence exemplifies the rise of comprehensive tooling and workflows to facilitate chiplet-based automotive electronics design. Their integrations address the challenges that chiplet-based SoCs present, ensuring a seamless design process from the initial concept to production. The Cadence suite of tools is tailored to work across design domains, ensuring coherence and efficiency at every step of the chiplet integration process.

For instance, Cadence Virtuoso RF subflows have become critical in navigating radio frequency (RF) challenges within the chiplets, while tools such as the Integrity 3D-IC Platform and the Allegro Advanced Multi-Die Package Design Solution have surfaced to enable comprehensive multi-die package designs. The Integrity Signal Planner extends its capabilities into the chiplet ecosystem, providing a centralized platform where system-wide signal integrity can be proactively managed. Sigrity and Celsius, on the other hand, offer universally applicable solutions that take on the challenges of chiplets in signal integrity and thermal considerations, irrespective of the design domain. Each of these integrated analysis solutions underscores the intricate symphony between technology, design, and packaging essential in unlocking the potential of chiplets for automotive electronics.

Cadence portfolio includes solutions for system analysis, optimization, and signoff to complement these domain-specific tools, ensuring that the challenges of chiplet designs don't halt progress toward innovative automotive electronics. Cadence enables designers to engage in power- and thermal-aware design practices through their toolset, a necessity as automotive systems become increasingly sophisticated and power-efficient.

A Standardized Approach to Success with Chiplets

Cadence’s support for UCIe underscores the criticality of standardized approaches for heterogeneous integration by conforming to UCIe standards, which numerous industry stakeholders back. By co-chairing the UCIe Automotive working group, Cadence ensures that automotive designs have a universal and standardized Die-to-Die (D2D) high-speed interface through which chiplets can intercommunicate, unleashing the true potential of modular design.

Furthermore, Cadence champions the utilization of virtual platforms by providing transaction-level models (TLMs) for their UCIe D2D IP to simulate the interaction between chiplets at a higher level of abstraction. Moreover, individual chiplets can be simulated within a chiplet-based SoC context leveraging virtual platforms. Utilizing UVM or SCE-MI methodologies, TLMs, and virtual platforms serve as first lines of defense in identifying and addressing issues early in the design process before physical silicon even enters the picture.

Navigating With the Right Tools

The road to chiplet-driven automotive electronics is one paved with complexity, but with a commitment to standards, it is a path that promises significant rewards. By leveraging Cadence UCIe Design and Verification IP, tools, and methodologies, automotive designers are empowered to chart a course toward chiplets and help to establish a chiplet ecosystem. With challenges ranging from die-to-die interconnect to standardization, heterogeneous integration, and advanced packaging, the need for a seamless integrated flow and highly automated design approaches has never been more apparent. Companies like Cadence are tackling these challenges, providing the key technology for automotive designers seeking to utilize chiplets for the next-generation E/E architecture of vehicular technology.

In summary, chiplets have the potential to revolutionize the automotive electronics industry, breathing new life into the way vehicles are designed, manufactured, and operated. By understanding the significance of chiplets and addressing the challenges they present, automotive electronics is poised for a paradigm shift—one that combines the art of human ingenuity with the power of modular and scalable microchips to shape a future that is not only efficient but truly intelligent.

Learn more about how Cadence can help to enable automakers and OEMs with various aspects of automotive design.

Today's high-performance computing systems often require the designer to instantiate multiple CPU or DSP cores in their subsystem. However, the performance gained by using multiple CPUs comes with additional programming complexity, especially when accessing shared memory data structures and hardware peripherals. CPU cores need to access shared data in an atomic fashion in a multi-core environment. Locking is the most basic requirement for data sharing. A core takes the lock, accesses the shared data structure, and releases the lock. While one core has the lock, other cores are disallowed from accessing the same data structure. Typically, locking is implemented using an atomic read-modify-write bus transaction on a variable allocated in an uncached memory.

This blog shares the AXI4 locking mechanism when implementing an Xtensa LX-based multi-core system on a Xilinx FPGA platform. It uses a dual-core design mapped to a KC705 platform as an example.

Exclusive Access to Accomplish Locking

The Xtensa AXI4 manager provides atomic access using the AXI4 atomic access mechanism. While Xtensa's AXI manager interface generates an exclusive transaction, the subordinate's interface is also expected to support exclusive access, i.e., AXI monitoring. Xilinx BRAM controller's AXI subordinate interface does not support exclusive access, i.e., AXI monitoring: AXI Feature Adoption in Xilinx FPGAs.

Leveraging Xtensa AXI4 Subordinate Exclusive Access

The Xtensa LX AXI subordinate interface supports exclusive access. One approach is to utilize this support and allocate locks in one of the core's local data memories. Ensure that the number of external exclusive managers is configured, typically to the number of cores (Figure 1).

Figure 1

Note that the Xtensa NX AXI subordinate interface does not support exclusive access. For an Xtensa NX design, shared memory with AXI monitoring is required.

In Figure 2, the AXI_crossbar#2 (block in green) routes core#0's manager AXI access (blue connection) to both core's local memories. Core#1's manager AXI (yellow connection) can also access both core's local memories. Locks can be allocated in either core's local data memory.

In-Bound Access on Subordinate Interface

On inbound access, the Xtensa AXI subordinate interface expects a local memory address, i.e., an external entity needs to present the same address as the core would use to access local memory in its 4GB address space. AXI address remap IP (block in pink) translates the AXI system address to each core's local address. For example, assuming locks are allocated in core#0's local memory, core#1 generates an AXI exclusive to access a lock allocated in core#0's local memory (yellow connection). AXI_crossbar#2 forwards transaction to M03_AXI port (green connection). AXI_address_remap#1 translates the AXI system address to the local memory address before presenting it to core#0's AXI subordinate interface (pink connection).

It is possible to configure cores with disjoint local data memory addresses and avoid the need for an address remap IP block. But then it will be a heterogeneous multi-core design with a multi-image build. An address remap IP is required to keep things simple, i.e., a homogeneous multi-core with a single image build. A single image uses a single memory map. Therefore, both cores must have the same view of a lock, i.e., the lock's AXI bus address must be the same for both.

Figure 2

AXI ID Width

Note Xtensa AXI manager interface ID width=4 bits. Xtensa's AXI subordinate interface ID width=12 bits. So, you must configure AXI crossbar#2 and AXI address remap AXI ID width higher than 4. AXI IDs on a manager port are not globally defined; thus, an AXI crossbar with multiple manager ports will internally prefix the manager port index to the ID and provide this concatenated ID to the subordinate device. On return of the transaction to its manager port of origin, this ID prefix will be used to locate the manager port, and the prefix will be truncated. Therefore, the subordinate port ID is wider in bits than the manager port ID. Figure 3 shows the Xilinx crossbar IP AXI ID width configuration.

Figure 3

Software Tools Support

Cadence tools provide a way to place locks at a specific location. For more details, please refer to Cadence's Linker Support Packages (LSP) Reference Manual for Xtensa SDK. .xtos.lock(green) resides in core#0's local memory and holds user-defined and C library locks. The lock segment memory attribute is defined as shared inner (cyan) so that L32EX and S32EX instructions generate an exclusive transaction on an AXI bus. See Figure 4. The stack and per-core Xtos and C library contexts are allocated in local data memory (yellow).

…………..LSP memory map………….
BEGIN dram0
0x40000000: dataRam : dram0 : 0x8000 : writable ;
dram0_0 : C : 0x40000400 - 0x40007fff : STACK : .dram0.rodata .clib.percpu.data .rtos.percpu.data .dram0.data .clib.percpu.bss .rtos.percpu.bss .dram0.bss;
END dram0
…………………
BEGIN sysViewDataRam0
0xA0100000: system : sysViewDataRam0 : 0x8000 : writable, uncached, shared_inner;
lockRam_0 : C : 0xA0100000 - 0xA01003ff : .xtos.lock;
END sysViewDataRam0
…………..

Figure 4

Please visit the Cadence support site for more information on emulating Xtensa cores on FPGAs.

By David Vye, Senior Product Marketing Manager, AWR, Cadence When designing multi-octave high-power amplifiers, it is a challenge to achieve both broadband gain and power matching using a combination of lumped and distributed techniques. One approach...(read more)

Hello,

I am trying to load some of the signals of the design saved in the signals.svwf to the waveform windown via the tcl file, I am using the following commands but nothing works, Can you please help 

 -submit waveform loadsignals -using "Waveform 2" FB1.svwf but it gives me the below error

-submit waveform new -reuse -name Waveforms

I want to use a transmission gate in my design, but it is not available as a standard cell for Genus RTL synthesis. How can I perform an analysis of area, power, and critical path delay that includes the transmission gate alongside standard cells?

Could you provide guidance or a methodology for integrating custom cells, like the transmission gate, into the synthesis flow for accurate analysis?

Hi，

There are mang components in BGA ball side of flipchip package.

Are there DFA check space of compont body or pin soldermask to BGA ball or BGA PAD or bga  soldermask in allegro APD?

I only find space of compont to compont in APD DFA. 

In a package design, designers often need to perform degassing. This is typically done at the end of the design process before sending the design to the manufacturer.

Degassing is a process where you perforate power planes, voltage planes, and filled shapes in your design. Degassing holes let the gas escape from beneath the metal during manufacturing of the substrate. The perforations or holes for degassing are generally small, having a specified size and shape, and are spaced regularly across the surface of the plane. If the degassing process is not done, it may result in the formation of gas bubbles under the metal, which may cause the surface of the metal to become uneven. After you degas the design, it is recommended to perform electrical verification.

Allegro X APD has degassing features that allow users to automate the process and place holes in the entire shape.

In today’s topic, we will talk about how to avoid adding  degassing holes on a particular shape.

Sometimes, a designer may need to avoid adding degassing holes to a particular shape on a layer. All other shapes on the layer can have degassing holes but not this shape. Using the Layer Based Degassing Parameters option, the designer can set the degassing parameters for all shapes on the layer. Now, the designer would like to defer adding degassing holes for this particular shape.

You may wonder if there is an easy way to achieve this. We will now see how this can be done with the tool.

Once the degassing parameters are set, performing Display > Element on any of the shapes on that layer will show the degassing parameters set.

You can apply the Degas_Not_Allowed property to a shape to specify that degassing should not be performed on this shape, even if the degassing requirements are met. Select the shape and add the property as shown below.

Switch to Shape Edit application mode (Setup > Application mode > Shape Edit) and window-select all shapes on the layer. Then, right-click and select Deferred Degassing > All Off.

Now, all shapes on the layer will have degassing holes except for the shape which has the Degas_Not_Allowed property attached to it.

On November 5, 2024, the Cadence Bangalore Toastmasters Club celebrated a significant milestone by hosting its 50th meeting. Established in December 2020, the club was created to provide a supportive environment for individuals looking to improve their communication and leadership skills. Over the years, the club has evolved into a vibrant community filled with success stories of personal development and newfound confidence. A testament to the club's dedication is its achievement of the "Select Distinguished Club" status during the 2023-2024 program year. By fulfilling 7 out of 10 distinguished goals, the club highlighted its commitment to excellence—a success driven by its vibrant members' relentless focus and perseverance. The strategic insight gained from regular Toastmasters committee meetings and the influential "Moments of Truth" sessions held in 2023 and 2024 are key to this success. Our club members have consistently demonstrated strong performance in various speech contests, with notable achievements across multiple levels. In 2023, members excelled in Evaluation and Table Topics contests, reaching the district level while advancing to the Division Level in the International Speech Contest. Continuing their success into 2024, members again qualified for area-level contests, securing third-place positions in the Evaluation and Table Topics categories, highlighting the club's dedication and competitive spirit. The 50th meeting was based on the theme of serendipity. It was not only a milestone celebration but also a vibrant festival of achievements and growth. The day buzzed with energy as activities like a spirited Treasure Hunt injected enthusiasm and camaraderie among attendees. Distinguished guests, including Kripa Venkitachalam and Madhavi Rao, enriched the occasion with inspiring speeches. Madhavi reignited the club's spirit, while Kripa's discourse on the Growth Mindset and the "Power of Yet" encouraged members to pursue continuous self-improvement. The Cadence Bangalore Toastmasters Club is enthusiastic about its promising future and is committed to creating an environment that promotes personal and professional growth. Many members are close to completing their Toastmasters levels and pathways, and this term, a new group of approximately 30 individuals has joined, bringing the total membership to 52. This vibrant community is just beginning its journey and is eager to reach new milestones together through mutual support and a shared commitment to excellence. The transformations experienced by many club members are truly compelling. They often share how the club has significantly improved their communication skills and boosted their confidence. One member recalls, "Before joining, I found public speaking intimidating. Now, I embrace every opportunity to share my ideas." Another member highlights how the club's supportive environment helped him overcome his fear of public speaking, propelling his career to new heights. This culture of constructive feedback and continuous improvement has inspired countless members to pursue their dreams with renewed determination and optimism. The Cadence Bangalore Toastmasters Club's journey is a living testament to the power of community and the potential within each of us to grow and achieve greatness. As the club continues to evolve and inspire, it serves as a beacon for those aspiring to transform their skills and seize their moment in the spotlight. Learn more about life at Cadence.

Hi,

I need to design EPC8002 eGaN switch in cadence. Can someone provide me step by step guide on hoe to add EPC8002 into my cadence. I am working on BCD180.

Thank you 

Ihsan

This is the 22nd installment of The Rationalist, my column for the Times of India.

Trade wars are on the rise, and it’s enough to get any nationalist all het up and excited. Earlier this week, Narendra Modi’s government announced that it would start imposing tariffs on 28 US products starting today. This is a response to similar treatment towards us from the US.

There is one thing I would invite you to consider: Trump and Modi are not engaged in a war with each other. Instead, they are waging war on their own people.

Let’s unpack that a bit. Part of the reason Trump came to power is that he provided simple and wrong answers for people’s problems. He responded to the growing jobs crisis in middle America with two explanations: one, foreigners are coming and taking your jobs; two, your jobs are being shipped overseas.

Both explanations are wrong but intuitive, and they worked for Trump. (He is stupid enough that he probably did not create these narratives for votes but actually believes them.) The first of those leads to the demonising of immigrants. The second leads to a demonising of trade. Trump has acted on his rhetoric after becoming president, and a modern US version of our old ‘Indira is India’ slogan might well be, “Trump is Tariff. Tariff is Trump.”

Contrary to the fulminations of the economically illiterate, all tariffs are bad, without exception. Let me illustrate this with an example. Say there is a fictional product called Brump. A local Brump costs Rs 100. Foreign manufacturers appear and offer better Brumps at a cheaper price, say Rs 90. Consumers shift to foreign Brumps.

Manufacturers of local Brumps get angry, and form an interest group. They lobby the government – or bribe it with campaign contributions – to impose a tariff on import of Brumps. The government puts a 20-rupee tariff. The foreign Brumps now cost Rs 110, and people start buying local Brumps again. This is a good thing, right? Local businesses have been helped, and local jobs have been saved.

But this is only the seen effect. The unseen effect of this tariff is that millions of Brump buyers would have saved Rs 10-per-Brump if there were no tariffs. This money would have gone out into the economy, been part of new demand, generated more jobs. Everyone would have been better off, and the overall standard of living would have been higher.

That brings to me to an essential truth about tariffs. Every tariff is a tax on your own people. And every intervention in markets amounts to a distribution of wealth from the people at large to specific interest groups. (In other words, from the poor to the rich.) The costs of this are dispersed and invisible – what is Rs 10 to any of us? – and the benefits are large and worth fighting for: Local manufacturers of Brumps can make crores extra. Much modern politics amounts to manufacturers of Brumps buying politicians to redistribute money from us to them.

There are second-order effects of protectionism as well. When the US imposes tariffs on other countries, those countries may respond by imposing tariffs back. Raw materials for many goods made locally are imported, and as these become expensive, so do those goods. That quintessential American product, the iPhone, uses parts from 43 countries. As local products rise in price because of expensive foreign parts, prices rise, demand goes down, jobs are lost, and everyone is worse off.

Trump keeps talking about how he wants to ‘win’ at trade, but trade is not a zero-sum game. The most misunderstood term in our times is probably ‘trade-deficit’. A country has a trade deficit when it imports more than what it exports, and Trump thinks of that as a bad thing. It is not. I run a trade deficit with my domestic help and my local grocery store. I buy more from them than they do from me. That is fine, because we all benefit. It is a win-win game.

Similarly, trade between countries is really trade between the people of both countries – and people trade with each other because they are both better off. To interfere in that process is to reduce the value created in their lives. It is immoral. To modify a slogan often identified with libertarians like me, ‘Tariffs are Theft.’

These trade wars, thus, carry a touch of the absurd. Any leader who imposes tariffs is imposing a tax on his own people. Just see the chain of events: Trump taxes the American people. In retaliation, Modi taxes the Indian people. Trump raises taxes. Modi raises taxes. Nationalists in both countries cheer. Interests groups in both countries laugh their way to the bank.

What kind of idiocy is this? How long will this lose-lose game continue?

The India Uncut Blog © 2010 Amit Varma. All rights reserved.
Follow me on Twitter.

For reasons too complicated to go into here, I need to generate the code for a veriloga view from a outside the normal Verilog-A editor. I would start with an "empty" veriloga view generated from the symbol in the normal way so I get the port order correct, then use external code to provide "guts" of the veriloga view by overwriting the generated code.

My understanding is that and code changes made external to the normal flow do not get picked up by Cadence - the Verilog-A code gets read at design time, not at netlist time. Would simply forcing a check and save of the veriloga view after the code is modified fix that problem? Or is there an easier way to incorporate externally generated Verilog-A code?

Hello,
I'm trying to characterize a full adder that use transmission gate.
Unfortunately, the power calculation are wrong for the cell are always negative.
Is there any method or commands that can can help in power calculation or add the power consumption by the input pins to the power calculation ?
Another question, Is liberate support the characterization or transmission gate cells as standard cells or I should use liberate AMS for these type of cells ?
Thanks in advance,
Tareq 

Hi,

reading Verilog®-A Language Reference I found this description of ddt function I don't understand:

Use the time derivative operator to calculate the time derivative of an argument.

ddt( input [ , abstol | nature ] )

input is a dynamic expression.

abstol is a constant specifying the absolute tolerance that applies to the output of the ddt operator. Set abstol at the largest signal level that you consider negligible.

nature is a nature from which the absolute tolerance is to be derived.

Can anyone explain how abstol and nature are defined? how using them? an example would be really appreciated.

Thanks

Andrea

The traditional methods of power analysis lag by various shortcomings and challenges:

• Getting an accurate measure of RTL power consumption during design exploration
• Getting consistent power through the design progress from RTL to P&R.
• System-level verification tools are disconnected from the implementation tools that translate RTL to gates and wires.

The Cadence Joules RTL Power Solution closes this gap by delivering time-based RTL power analysis with system-level runtimes, capacity, and high-quality estimates of gates and wires based on production implementation technology. The Cadence Joules RTL Power Solution is an RTL power analysis tool that provides a unified engine to compute gate netlist power and estimate RTL power. The Joules solution delivers 20X faster time-based RTL power analysis and can analyze multi-million instance designs overnight, with impressive accuracy within 15% of signoff power.

Moreover, it integrates seamlessly with numerous Cadence platforms, eliminating compatibility and correlation issues! In addition, the Joules RTL Power Solution GUI (Graphical User Interface) helps you analyze/debug the power estimation/results using several GUI capabilities.

Want to take a tour of this power estimation world? Gear up to attend the training class created just for you to dive deep into the entire flow and explore this exciting power estimation method/flow with hands-on labs in two days!

Training

In the Joules Power Calculator Training course, you will identify solutions and features for RTL power using Cadence Joules RTL Power Solution. You will set up and run the RTL power flow with Joules RTL Power Solution and identify Joules's Graphical User Interface (GUI) capabilities. The training also explores how you can estimate power using vectorless power, stimulus flow, RTL Stim to Gate flow, and replay flow, and also interfaces Joules with Cadence's Palladium Emulation Platform. You will estimate power at the chip level and understand how to navigate the design and data mining using Joules.

The training also covers power exploration features and how to analyze ideal power and ODC-driven sequential clock gating. You will identify low-activity registers at the clock gate. You will also identify techniques to analyze power, generate various reports, and analyze results through Joules GUI. The training covers multiple strategies to debug low stimulus annotation and how you can better correlate RTL power with signoff. You also identify Genus-Joules Integration. In addition, we ensure that your learning journey is smooth with hands-on labs covering various design scenarios.

Lab Videos

To start you on your exciting journey as an RTL power analysis expert, we have created a series of short channel lab videos on our Customer Support site: Lab Demo: Setting Up and Running Basic RTL Power Flow in Joules RTL Power Solution (Video). You can refer to each lab module's instructions in demo format. This will help accelerate your tool ramp-up and help you perform the lab steps more quickly if you are stuck. You might be a beginner in the RTL power analysis world, but we can help you sail through it smoothly.

What's Next?

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