1 Nepalese Rupee = 0.0474 Brazilian Real

1 Nepalese Rupee = 0.057 Bolivian Boliviano

1 Nepalese Rupee = 0.0117 Brunei Dollar

1 Nepalese Rupee = 0.0031 Bahraini Dinar

1 Nepalese Rupee = 0.0149 Bulgarian Lev

1 Nepalese Rupee = 0.7028 Bangladeshi Taka

1 Nepalese Rupee = 0.0127 Australian Dollar

1 Nepalese Rupee = 0.5497 Argentine Peso

1 Nepalese Rupee = 0.0148 Netherlands Antillean Guilder

1 Nepalese Rupee = 0.0304 United Arab Emirates Dirham

1 Bangladeshi Taka = 1.4229 Nepalese Rupee

1 Moldovan Leu = 6.7823 Nepalese Rupee

1 Colombian Peso = 0.031 Nepalese Rupee

If college football is forced to play in the spring, it won't be the first time that has happened. You just have to go back to the 19th century.

1 Uruguayan Peso = 2.8034 Nepalese Rupee

1 Uzbekistan Som = 0.012 Nepalese Rupee

1 Russian Ruble = 1.6475 Nepalese Rupee

1 Iraqi Dinar = 0.1016 Nepalese Rupee

1 Cayman Islands Dollar = 145.0844 Nepalese Rupee

1 Swiss Franc = 124.5502 Nepalese Rupee

1 CFA Franc BCEAO = 0.1999 Nepalese Rupee

1 Vietnamese Dong = 0.0052 Nepalese Rupee

1 Macedonian Denar = 2.1282 Nepalese Rupee

1 Zambian Kwacha = 0.0233 Nepalese Rupee

1 South Korean Won = 0.0991 Nepalese Rupee

1 Jordanian Dinar = 170.4515 Nepalese Rupee

1 Lebanese Pound = 0.0799 Nepalese Rupee

1 Bahraini Dinar = 319.7851 Nepalese Rupee

1 Chilean Peso = 0.1464 Nepalese Rupee

1 Maldivian Rufiyaa = 7.8005 Nepalese Rupee

1 Malaysian Ringgit = 27.9038 Nepalese Rupee

1 Nicaraguan Cordoba Oro = 3.5152 Nepalese Rupee

The Redskins quarterback's broken leg led to an insidious infection that could have cost him his life.

1 Netherlands Antillean Guilder = 67.3663 Nepalese Rupee

1 Estonian Kroon = 8.4793 Nepalese Rupee

1 Danish Krone = 17.5756 Nepalese Rupee

1 Fiji Dollar = 53.6768 Nepalese Rupee

1 New Zealand Dollar = 74.2303 Nepalese Rupee

1 Croatian Kuna = 17.4295 Nepalese Rupee

1 Peruvian Nuevo Sol = 35.5795 Nepalese Rupee

1 Dominican Peso = 2.1972 Nepalese Rupee

1 Papua New Guinean Kina = 35.2544 Nepalese Rupee

1 Brunei Dollar = 85.5724 Nepalese Rupee

In the book “The World of _____” by Bennett Alan Weinberg and Bonnie K Bealer, there is a photograph of a label from a jar of pharmaceutical-grade crystals. It reads:

“WARNING: MAY BE HARMFUL IF INHALED OR SWALLOWED. HAS CAUSED MUTAGENIC AND REPRODUCTIVE EFFECTS IN LABORATORY ANIMALS. INHALATION CAUSES RAPID HEART RATE, EXCITEMENT, DIZZINESS, PAIN, COLLAPSE, HYPOTENSION, FEVER, SHORTNESS OF BREATH. MAY CAUSE HEADACHE, INSOMNIA, VOMITING, STOMACH PAIN, COLLAPSE AND CONVULSIONS.”

Fill in the blank.

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This is the 23rd installment of The Rationalist, my column for the Times of India.

I had a strange dream last night. I dreamt that the government had passed a law that made using laptops illegal. I would have to write this column by hand. I would also have to leave my home in Mumbai to deliver it in person to my editor in Delhi. I woke up trembling and angry – and realised how Indian farmers feel every single day of their lives.

My column today is a tale of two satyagrahas. Both involve farmers, technology and the freedom of choice. One of them began this month – but first, let us go back to the turn of the millennium.

As the 1990s came to an end, cotton farmers across India were in distress. Pests known as bollworms were ravaging crops across the country. Farmers had to use increasing amounts of pesticide to keep them at bay. The costs of the pesticide and the amount of labour involved made it unviable – and often, the crops would fail anyway.

Then, technology came to the rescue. The farmers heard of Bt Cotton, a genetically modified type of cotton that kept these pests away, and was being used around the world. But they were illegal in India, even though no bad effects had ever been recorded. Well, who cares about ‘illegal’ when it is a matter of life and death?

Farmers in Gujarat got hold of Bt Cotton seeds from the black market and planted them. You’ll never guess what happened next. As 2002 began, all cotton crops in Gujarat failed – except the 10,000 hectares that had Bt Cotton. The government did not care about the failed crops. They cared about the ‘illegal’ ones. They ordered all the Bt Cotton crops to be destroyed.

It was time for a satyagraha – and not just in Gujarat. The late Sharad Joshi, leader of the Shetkari Sanghatana in Maharashtra, took around 10,000 farmers to Gujarat to stand with their fellows there. They sat in the fields of Bt Cotton and basically said, ‘Over our dead bodies.’ ¬Joshi’s point was simple: all other citizens of India have access to the latest technology from all over. They are all empowered with choice. Why should farmers be held back?

The satyagraha was successful. The ban on Bt Cotton was lifted.

There are three things I would like to point out here. One, the lifting of the ban transformed cotton farming in India. Over 90% of Indian farmers now use Bt Cotton. India has become the world’s largest producer of cotton, moving ahead of China. According to agriculture expert Ashok Gulati, India has gained US$ 67 billion in the years since from higher exports and import savings because of Bt Cotton. Most importantly, cotton farmers’ incomes have doubled.

Two, GMO crops have become standard across the world. Around 190 million hectares of GMO crops have been planted worldwide, and GMO foods are accepted in 67 countries. The humanitarian benefits have been massive: Golden Rice, a variety of rice packed with minerals and vitamins, has prevented blindness in countless new-born kids since it was introduced in the Philippines.

Three, despite the fear-mongering of some NGOs, whose existence depends on alarmism, the science behind GMO is settled. No harmful side effects have been noted in all these years, and millions of lives impacted positively. A couple of years ago, over 100 Nobel Laureates signed a petition asserting that GMO foods were safe, and blasting anti-science NGOs that stood in the way of progress. There is scientific consensus on this.

The science may be settled, but the politics is not. The government still bans some types of GMO seeds, such as Bt Brinjal, which was developed by an Indian company called Mahyco, and used successfully in Bangladesh. More crucially, a variety called HT Bt Cotton, which fights weeds, is also banned. Weeding takes up to 15% of a farmer’s time, and often makes farming unviable. Farmers across the world use this variant – 60% of global cotton crops are HT Bt. Indian farmers are so desperate for it that they choose to break the law and buy expensive seeds from the black market – but the government is cracking down. A farmer in Haryana had his crop destroyed by the government in May.

On June 10 this year, a farmer named Lalit Bahale in the Akola District of Maharashtra kicked off a satyagraha by planting banned seeds of HT Bt Cotton and Bt Brinjal. He was soon joined by thousands of farmers. Far from our urban eyes, a heroic fight has begun. Our farmers, already victimised and oppressed by a predatory government in countless ways, are fighting for their right to take charge of their lives.

As this brave struggle unfolds, I am left with a troubling question: All those satyagrahas of the past by our great freedom fighters, what were they for, if all they got us was independence and not freedom?

© 2007 IndiaUncut.com. All rights reserved.
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For a netlist vs. netlist LEC flow we have to solve the following problem:

- in the RTL code we replicate a large array of N x M all-identical hard-macros, let call them MACRO_A

- MACRO_A is pre-assembled in Innovus and contains digital parts and analog parts (bottom-up hierarchical flow)

- at top-level (full-chip) we instantiate this array of all-identical macros

- in the top-level place-and-route flow we perform ecoChangeCell to remaster the top row of this array with MACRO_B

- MACRO_B is just a copy of the original MACRO_A cell containing same pins position, same internal digital functionality and also same digital layout, only slight differences in one analog block inside the macro

- MACRO_A and MACRO_B have the same .lib file generated with the do_extract_model command at the end of the Innovus flow, they only differ in the name of the macro

- when performing post-synthesis netlist vs post-place-and-route we load .lib files of both macros in Conformal LEC

- the LEC flow fails because Conformal LEC sees only MACRO_A instantiated in the post-synthesis netlist and both MACRO_A and MACRO_B in the post-palce-and-route netlist

Since both digital functionality and STD cells layout are the same between MACRO_A and MACRO_B we don't want to keep track of this difference already at RTL stage, we just want to perform this ECO change in place-and-route and force Conformal to assume equivalence between MACRO_A and MACRO_B .

Basically what I'm searching for is something similar to the add_instance_equivalences Conformal command but that works between Golden and Revised designs on cell primitives/black-boxes .

Is this flow supported ?

Thanks in advance

Luca

Complexity is driving the urgency for advanced artificial intelligence systems more than ever—and that means someone has to supply the tools to create those systems. Cadence is up to the task: we’ve been expanding our AI offerings. If you haven’t already seen what Cadence can do for your AI needs, or if you’re not quite up-to-date on this whole AI boom, let this presentation given by K.T. Moore at the Cadence Theater at DAC bring you up to speed.

The technology behind AI isn’t as new as you’d think—the principles that govern how AI learns have been in development since 1959, when Arthur Samuel defined the concept of “machine learning.” At the time, there was nothing even resembling the necessary compute power to put Samuel’s concepts into practice—but now we can. AI designs are huge, and they’re massively parallel—simulating them on older computers and simulators would have taken ages; never mind how long it would take to do some by-hand measure like they had to do in the '60s.

But with advancements in server technology and the parallelization technology in products like Xcelium Parallel Logic Simulator and JasperGold smart technology, plus hardware-based engines like the Palladium and Protium platforms, verifying AI designs is not only possible—it’s easy.  But, read on, its not just about simulation technology.

AI tech is flooding the industry. It’s applicable to almost every vertical—cloud computing can use AI to intelligently manage a user’s required resources, consumer electronics are using it to tailor a user experience based on a whole host of collected data, automotive companies want to use AI to drive cars, healthcare to assist in diagnoses given a set of symptoms and a database of other, similar patients—and that’s saying nothing of the multitude of industrial applications. AI is also useful in the creation of developers’ tools themselves. Part of what’s causing the semiconductor industry boom is just this—an exploding interest in AI chips. And with 5G technology imminent, and with the looming billion-gate plus sizes of the SoCs that implement 5G, AI-assisted developers' tools might need to become the norm, not an outlier.

So: in all of this, where is Cadence?

Cadence is focusing its efforts on two areas, dubbed “machine learning inside” and “machine learning outside.” ML inside in the digital design flow refers to improving PPA, faster engines, and better testing and diagnostics. None of this physically affects how you use a tool, but it makes using that tool a much better experience. ML outside talks about the design flow in general, working toward an automated design flow, as well as productivity improvements across the flow. These things do change how you use a tool, but don’t worry, it’s all for the better.

Additionally, Cadence is working to improve design enablement; that is, hardware and software co-design. Smart Genus and Innovus solutions make designing your SoC easier than ever—using the full flow can result in up to a 21% PPA gain.

If you’re looking specifically for IP to enable AI on your SoC, the Tensilica DNA 100 processor has you covered, too. It’s great for companies designing edge or AI chips, offers great compression rates and efficient power usage, and has 4.7X the performance of other AI SoC IP on similar array sizes.

Cadence has you covered no matter where you’re going in this new world of AI systems—with our AI-enabled tools, IP,  and our strong partner ecosystem, you can be at ease knowing you’ll be supported no matter how complex your needs are.

Everyone keeps talking about “the cloud” this and “the cloud” that these days—but you’re a semiconductor designer. Everyone keeps saying “the cloud” is revolutionizing all aspects of electronics design—but what does it mean for you? Cadence's own Tom Hackett discussed this in a presentation at the Cadence Theater during DAC 2019.

What people refer to as “the cloud” is commonly divided into three categories: Infrastructure as a Service (IaaS), Platform as a Service (PaaS), and software as a Service (SaaS). With IaaS, you bring your own software—i.e. loading your owned or appropriately licensed tools onto cloud hardware that you rent by the minute. This service is available from providers like Google Cloud Platform, Amazon Web Service, and Microsoft Azure. In PaaS (also available from the major cloud providers), you create your own offering using capabilities and a software design environment provided by the cloud vendor that makes subsequent scaling and distribution really easy because the service was “born in the cloud”.  Lastly, there’s SaaS, where the cloud is used to access and manage functionality and data without requiring users to set up or manage any of the underlying infrastructure used to provide it.  SaaS companies like Workday and Salesforce deliver their value in this manner.  The Cadence Cloud portfolio makes use of both IaaS and SaaS, depending on the customers’ interest.  Cadence doesn’t have PaaS offerings because our customers don’t create their own EDA software from building blocks that Cadence provides.

All of these designations are great, but you’re a semiconductor designer. Presumably you use Workday or some similar software, or have in the past when you were an intern, but what about all of your tools? Those aren’t on the cloud.

Wait—actually, they are.

Using EDA tools in the cloud allows you to address complexity and data explosion issues you would have to simply struggle through before. Since you don’t have to worry about having the compute-power on-site, you can use way more power than you could before. You may be wary about this new generation of cloud-based tools, but don’t worry: the old rules of cloud computing no longer apply. Cloud capacity is far larger than it used to be, and it’s more secure. Updates to scheduling software means that resource competition isn’t as big of a deal anymore. Clouds today have nearly unlimited capacity—they’re so large that you don’t ever need to worry about running out of space.

The vast increase in raw compute available to designers through the cloud makes something like automotive functional safety verification, previously an extremely long verification task, doable in a reasonable time frame. With the cloud, it’s easy to scale the amount of compute you’re using to fit your task—whether it’s an automotive functional safety-related design or a small one.

Nowadays, the Cadence Cloud Portfolio brings you the best and brightest in cloud technology. No matter what your use case is, the Cadence Cloud Portfolio has a solution that works for you. You can even access the Palladium Cloud, allowing you to try out the benefits of an accelerator without having to buy one.

Cloud computing is the future of EDA. See the future here.

Emulators are great. They vastly speed up verification to the point where it’s hard to imagine life without them; as designs grow in complexity, simple simulation can’t keep up for the biggest designs. The extra oomph from emulation is almost a necessity for the top percentages of design sizes. However, many users of Palladium aren’t efficiently using their unit’s processing power, and as a result they’re missing out on the full speed-up potential that Palladium can provide.

Altair’s HERO is here for you. With its help, your Palladium unit can be even more amazing for your productivity than before.

HERO (that’s Hardware Emulator Resource Optimizer) adds emulator support to Altair’s Accelerator. You already know and love Altair’s scheduling tools; so why not make them do more for you, so you can be one of those people who are making the most out of their Palladium system?

Emulators are kind of like big computers, but it’s a lot harder to manage leftover resources on an emulator than it is on, say, a CPU. A scheduler like HERO neatly sidesteps this problem by more intelligently using the resources available to ensure that there’s a minimal patchwork of leftover resources to begin with.

HERO supports past generations of Palladium as well, so if you’re still using an older version, you can still take advantage of the upgrades HERO provides. There’s a wide variety of features HERO has that make your emulator easier to use. HERO separates a job into a “select” section and a “run” section: the “select” part makes a last-minute decision on which domains or boards to use, while the “run” part is the actual job. This makes it easier to ensure that your Palladium emulator is being used as efficiently as possible. Jobs are placed using “shapes”, which are a set of job types; these can be selected from a list of pre-defined ones by the user. Shapes can have special constraints if those are needed.

A new reservation system also helps HERO organize Palladium’s processing power better. HERO offers both “hard” reservations and “soft” reservations. A hard reservation locks other users out of reserving any part of the emulator at all, while a soft reservation allows a user to reserve a part of the emulator for a later use. Think of it like this: a soft reservation is like grabbing a ticket from the deli counter, while a hard reservation stops you from ever entering the market.

When using HERO, you can manage your entire verification workload. You’ll find that your utilization of your emulator vastly increases—it’s been reported that some users using only 30% of the capabilities of their Palladium unit(s) saw a massive increase to over 90% once they made the switch to HERO.

If you’re ready to take your Palladium productivity to the next level, Altair has a HERO for you.

To see the full presentation given by Andrea Casotto in the Cadence Theater at DAC 2019, check here.

Freescale was a successful Incisive® simulation CPF low-power user when they decided to step up their game. In November 2013, at CDNLive India, they presented a paper explaining how they improved their ability to find power-related bugs using a more sophisticated verification flow.  We were able to catch up with Abhinav Nawal just after his presentation to capture this video explaining the key points in his paper.

Abhinav had already established a low-power simulation process using directed tests for a design with power intent captured in CPF. While that is a sound approach, it tends to focus on the states associated with each power control module and at least some of the critical power mode changes.  Since the full system can potentially exercise unforeseen combinations of power states, the directed test approach may be insufficient. Abhinav built a more complete low-power verification approach rooted in a low-power verification plan captured in Cadence® Incisive Enterprise Manager.  He still used Incisive Enterprise Simulator and the SimVision debugger to execute and debug his design, but he also added Incisive Metric Center to analyze coverage from his low-power tests and connect that data back to the low-power verification plan.  As a result, he was able to find many critical system-level corner case issues, which, left undetected, would have been catastrophic for his SoC.  In the paper, Abhinav presents some of the key problems this approach was able to find.

You can achieve results similar to Abhinav. Incisive Enterprise Simulator can generate a low-power verification plan from the power format, power-aware assertions, and it can collect power-aware knowledge.  To get started, you can use the Incisive Low-Power Simulation Rapid Adoption Kit (RAK) for CPF available on Cadence Online Support.

Just another happy Cadence low-power verification user!

Regards,

Adam "The Jouler" Sherer