Systems, among other embodiments, include topologies (data and/or control/address information) between an integrated circuit buffer device (that may be coupled to a master, such as a memory controller) and a plurality of integrated circuit memory devices. For example, data may be provided between the plurality of integrated circuit memory devices and the integrated circuit buffer device using separate segmented (or point-to-point link) signal paths in response to control/address information provided from the integrated circuit buffer device to the plurality of integrated circuit buffer devices using a single fly-by (or bus) signal path. An integrated circuit buffer device enables configurable effective memory organization of the plurality of integrated circuit memory devices. The memory organization represented by the integrated circuit buffer device to a memory controller may be different than the actual memory organization behind or coupled to the integrated circuit buffer device. The buffer device segments and merges the data transferred between the memory controller that expects a particular memory organization and actual memory organization.

An apparatus includes a first terminal configured to communicate data with an outside of the apparatus, a second terminal configured to receive a first power source potential, a third terminal configured to receive a second power source potential lower than the first power source potential, a fourth terminal configured to be coupled to a calibration resistor, an output buffer including first to third nodes coupled to the first to third terminals respectively, and a replica circuit including fourth and fifth nodes coupled to the second and third terminals respectively, and sixth node coupled to the fourth terminal.

A semiconductor memory device may include: a memory bank comprising a plurality of word lines; a smart command generation unit suitable for generating a smart refresh command, which is enabled at a random cycle, in response to an active command; and a refresh operation control unit suitable for performing a refresh operation to at least one of adjacent word lines of a target word line among the plurality of word lines in response to the smart refresh command.

A refresh controller of a memory device may include a timing controller, a refresh counter and an address generator. The timing controller generates a counter refresh signal in response to receiving a refresh command provided from an external device, and generates a hammer refresh signal that is activated periodically. The refresh counter generates a counter refresh address signal in response to the counter refresh signal, such that the counter refresh address signal represents a row address, the refresh counter being configured sequentially change the counter refresh address signal. The address generator generates a hammer refresh address signal in response to the hammer refresh signal, the hammer refresh address signal representing an address of a row of the memory device that is physically adjacent to a row of the memory device corresponding to a hammer address that is accessed intensively.

A device including a memory cell and write assist circuit is disclosed. The memory cell includes a first inverter and a second inverter cross-coupled with the first inverter. The write assist circuit is coupled to the memory cell. During a write operation of the memory cell, the write assist circuit is configured to adjust a voltage level of an operational voltage provided to the first inverter or the second inverter by a bias voltage difference.

A bit line architecture for dual-port static random-access memory (DP SRAM) is provided. An array of memory cells is arranged in rows and columns, and comprises a first subarray and a second subarray. A first pair of complementary bit lines (CBLs) extends along a column, from a first side of the array, and terminates between the first and second subarrays. A second pair of CBLs extends from the first side of the array, along the column, to a second side of the array. The CBLs of the second pair of CBLs have stepped profiles between the first and second subarrays. A third pair of CBLs and a fourth pair of CBLs extend along the column. The first and third pairs of CBLs electrically couple to memory cells in the first subarray, and the second and fourth pairs of CBLs electrically couple to memory cells in the second subarray.

According to one embodiment, a semiconductor storage apparatus includes a memory cell array and a read circuit. The memory cell array includes a memory cell which is connected to a word line. A threshold voltage of the memory cell corresponds to a data value of multiple bits. The read circuit receives designation of one bit among the multiple bits, applies a first reading voltage and a second reading voltage corresponding to the designated bit to the word line, senses ON or OFF of the memory cell for each reading voltage, and outputs a first sensed value and a second sensed value after performing the sensing for each reading voltage. The first sensed value is a sensing result in a case where the first reading voltage is applied. The second sensed value is a sensing result in a case where the second reading voltage is applied.

A method is provided for a reading memory even if there is a threshold voltage in an overlapped threshold voltage (VTH) region between a first state distribution and a second state distribution. The method includes ramping a bias on a memory cell a first time to determine a first threshold voltage (VTH1) of the memory cell and determining whether the VTH1 is within the overlapped VTH region. Upon determination that the memory cell is within the overlapped VTH region, the method further includes applying a write pulse to the memory cell; ramping a bias on the memory cell a second time to determine a second threshold voltage (VTH2); and determining the state of the memory cell prior to receiving the write pulse based on a comparison between the VTH1 and the VTH2.

A memory device includes a first string and a second string. The first string includes first and second transistors and first cell transistors coupled in series between a source line and a bit line. The second string includes third and fourth transistors and second cell transistors coupled in series between the source line and the bit line. During a read, a gate of the fourth transistor is applied with a voltage to turn off the transistor, and after start of application of voltages to the first cell transistors, the gate of the fourth transistor is applied with a voltage substantially the same as a voltage applied to the source line.

A method of operating a nonvolatile memory device includes: first programming a target transistor of a cell string of the nonvolatile memory device, wherein the target transistor has a first threshold voltage distribution after the first programming, and wherein the cell string includes a plurality of transistors; and second programming the target transistor of the cell string, wherein the first transistor has a second threshold voltage distribution after the second programming, wherein a width of the second threshold voltage distribution is less than a width of the first threshold voltage distribution.

According to one embodiment, a first well of the first conductivity type which is formed in a substrate. a second well of a second conductivity type which is formed in the first well. The plurality of memory cells, the plurality of first bit line select transistors, and the plurality of second bit line select transistors are formed in the second well, and the plurality of first bit line select transistors and the plurality of second bit line select transistors are arranged on a side of the sense amplifier with respect to the plurality of memory cells of the plurality of bit lines.

According to one embodiment, a semiconductor memory device includes: first to third pages; first to third word line; and row decoder. In data writing, data is written into the first page before data is written into the second page. The row decoder is configured to apply first to third verify voltages to the gates of the first to third memory cells in a program verify operation.

A memory system may include a memory device including 0th to N-1th memory blocks, wherein N is a positive integer; and a controller having a first list and a second list, wherein the first list includes 0th to N-1th erase count values respectively for the 0th to N-1th memory blocks, wherein the second list includes 0th to N-1th difference values respectively for the 0th to N-1th memory blocks, wherein each of the 0th to N-1th difference values is a difference between an average value of the 0th to N-1th erase count values and each of the 0th to N-1th erase count values, wherein the controller selects a source block and a target block among the 0th to N-1th memory blocks depending on the 0th to N-th erase count values included in the first list and the 0th to N-1th difference values included in the second list to perform a wear leveling between the source block and the target block.

Semiconductor memory devices are provided. The semiconductor memory device includes an input/output (I/O) drive controller, a data I/O unit and a data transmitter. The input/output (I/O) drive controller generates drive control signals and an input control signal for driving first and second global I/O lines in a first test mode or a second test mode. The data I/O unit drives the first global I/O line in response to an input data when a write operation is executed in the first test mode and to drive the first and second global I/O lines in response to the drive control signals when the write operation is executed in the second test mode. The data transmitter transfers the data on the first global I/O line onto first and second local I/O lines to store the data on the first global I/O line in a memory cell array portion when the write operation is executed in the first test mode. The data transmitter also transfers the data on the first and second global I/O lines onto the first and second local I/O lines to store the data on the first and second global I/O lines in the memory cell array portion when the write operation is executed in the second test mode. Related methods are also provided.

An integrated circuit may include nonvolatile memory suitable for outputting stored data during the boot-up operation, one or more registers suitable for receiving the data output by the nonvolatile memory and storing the received data when the boot-up operation is performed, and one or more internal circuits suitable for operating using the data stored in the one or more registers. In no-update mode, although the boot-up operation is performed, a data update from the nonvolatile memory to the registers may not be performed.

Devices are provided in which a metastable state can be detected in a memory device by means of a metastability detector. Corresponding information can be conveyed to a further device which, in dependence thereon, can process data from the memory device.

A semiconductor device includes a substrate comprising a trench; a gate dielectric layer formed over a surface of the trench; a gate electrode positioned at a level lower than a top surface of the substrate, and comprising a lower buried portion embedded in a lower portion of the trench over the gate dielectric layer and an upper buried portion positioned over the lower buried portion; and a dielectric work function adjusting liner positioned between the lower buried portion and the gate dielectric layer; and a dipole formed between the dielectric work function adjusting liner and the gate dielectric layer.

A method of forming a ferroelectric memory cell. The method comprises forming an electrode material exhibiting a desired dominant crystallographic orientation. A hafnium-based material is formed over the electrode material and the hafnium-based material is crystallized to induce formation of a ferroelectric material having a desired crystallographic orientation. Additional methods are also described, as are semiconductor device structures including the ferroelectric material.

Manufacturing methods of JFET-type compact three-dimensional memory (3D-MC) are disclosed. In a memory level stacked above the substrate, an x-line extends from a memory array to an above-substrate decoding stage. A JFET-type transistor is formed on the x-line as a decoding device for the above-substrate decoding stage, where the overlap portion of the x-line with the control-line (c-line) is semi-conductive.

A magnetoresistive random access memory (MRAM) structure includes a bottom electrode structure. A magnetic tunnel junction (MTJ) element is over the bottom electrode structure. The MTJ element includes an anti-ferromagnetic material layer. A ferromagnetic pinned layer is over the anti-ferromagnetic material layer. A tunneling layer is over the ferromagnetic pinned layer. A ferromagnetic free layer is over the tunneling layer. The ferromagnetic free layer has a first portion and a demagnetized second portion. The MRAM also includes a top electrode structure over the first portion.

A memorial product is presently disclosed that includes a glass structure having a first helix of cremation remains and a second helix of a second material, wherein the helix of the cremation remains and the helix of the second material are intertwined to form a double helix in the glass structure. In some embodiments, the second material is additional cremation remains or a colored material selected to correspond to the deceased represented by the cremation remains. Also disclosed is a method of manufacturing a memorial product including forming a first portion of molten glass into a substantially cylindrical shape having an exterior surface, applying cremation remains on a first portion of the exterior surface, applying a second material on a second portion of the exterior surface, and gathering a second portion of molten glass over the first portion of molten glass to encase the cremation remains and the second material.

An apparatus including a mounting platform, wherein the mounting platform includes a substantially planar mounting surface; a clamping mechanism on the mounting surface; a memorial item retained by the clamping mechanism; and an arrangement of handles on a side of the mounting platform, wherein the side is substantially normal to the plane of the mounting surface.

A decorative memorial serves to display a sealed, visible portion of cremation ashes.

A hanging memorial for displaying pictures and ashes of the deceased, and storing keepsakes. The hanging memorial includes a frame and an urn; the urn being integrated into the frame. A lateral wall and a front panel of the frame define a storage volume in which keepsakes can be placed. Alternatively an internal storage box can define the storage volume. The frame further includes a frame insert that can be configured to display a physical painting or photograph, or configured to display digital pictures. The urn is removably attached or pivotally connected to the frame by an at least one bracket, such that the contents of the urn are readily accessible. The hanging memorial may further include a niche about which the at least one bracket is positioned and into which the urn is positioned. Alternative support mechanism may also be used in place of the at least one bracket.

A memorial urn includes a central core having at least one vessel stored therein, the vessel functioning to house and identify cremated remains. A plurality of commemoratory items are secured to the central core and a protective outer shell having a plurality of indicia are secured around the core and commemoratory items. A candleholder is positioned onto the outer coating and functions to receive any number of conventional candles.

The invention provides a M.2 interface memory device and a M.2 interface connection seat insertedly provided thereof. The M.2 interface memory device comprises a M.2 interface card and a housing provided with at least one guide groove. The M.2 interface connection seat is disposed on a circuit board, and comprises two arms and a base comprising a M.2 interface slot. At least one arm is provided with a guide rail. An opening direction of the M.2 interface slot is horizontal to a surface of the circuit board. When the M.2 interface card is inserted into the M.2 interface slot in a horizontal direction, the M.2 interface memory device will be fixed within the M.2 interface connection seat by embedding between the guide groove and the guide rail. Thus, M.2 interface memory devices of a variety of specification lengths are able to be inserted into the M.2 interface connection seat.

Disclosed is a housing for electronic/electrical that includes an inner panel and an outer panel, a strip of metal plate, and a strip of shape memory material. The inner panel and the outer panel are disposed parallel to each other at regular intervals to define an internal space. The strip of metal plate extends from an inner surface of the outer panel. The strip of shape memory material extends from an inner surface of the inner panel and is attached or detached to/from the metal plate on the outer panel while changing into an original straight shape or a bent shape according to a temperature variation. Here, when the temperature increase beyond a first transition temperature, the shape memory material straightens to form a heat transfer path. At a low temperature environment, the shape memory material bends and is separated from the metal plate to interrupt the heat transfer path.

Techniques are described that includes using a memory to store data within a system. The techniques include lowering a supply voltage applied to said memory and ceasing use of the memory to store data within the system. The techniques further include reading values from the memory with the supply voltage being lowered. The techniques further include determining a radiation level from an amount of corrupted ones of the values.

The present invention relates to methods of determining if a subject has an increased risk of suffering from memory impairment. The methods comprise analyzing at least one sample from the subject to determine a value of the subject's exosomal profile or combined biomarker profile (lipids plus exosomal cargo) and comparing the value of the subject's exosomal or combined biomarker profile with the value of a normal exosomal or biomarker profile, respectively. A change in the value of the subject's exosomal or combined biomarker profile, including a change in the subject's exosomal or combined biomarker profile, over normal values is indicative that the subject has an increased risk of suffering from memory impairment compared to a normal individual.

A method of making a MRAM device includes forming a magnetic tunnel junction on an electrode, the magnetic tunnel junction comprising a reference layer positioned in contact with the electrode, a tunnel barrier layer arranged on the reference layer, and a free layer arranged on the tunnel barrier layer; and depositing an encapsulating layer on and along sidewalls of the magnetic tunnel junction; wherein the exposing of the magnetic tunnel junction to hydrogen plasma is performed at a temperature from about 150 to about 250° C. An MRAM device including an encapsulating layer comprising either silicon nitride or aluminum oxide is also provided.

A pattern-forming method includes providing a first ion beam at a first incidence angle and a second ion beam at a second incidence angle to a surface of an etch target layer formed on a substrate. Patterns are formed by patterning the etch target layer using the first and second ion beams. The first ion beam and the second ion beam are substantially symmetrical to each other with respect to a normal line that is perpendicular to a top surface of the substrate. Each of the first and second incidence angles is greater than 0 degrees and smaller than an angle obtained by subtracting a predetermined angle from 90 degrees.

A HAMPSHIRE charity has launched its annual search for local good causes that need a cash boost.

NEW Forest carp farmers Heather Fisheries were delighted to be asked to provide a memorial fish for the Stone family to put into Christchurch Angling Club’s Hucklesbrook Lake.

EVEN from a young age he wanted to conquer the world of sailing.

ALTHOUGH it is not possible to go to the berth Titanic sailed from, ABP do allow members of the public to visit the Titanic memorial.

THE WINNING design for a stained glass window to the Titanic crew who perish in the disaster has been revealed this weekend.

The family of the helmsman of the Titanic, whose final resting place was a mystery for decades, have now marked his grave with a headstone in Aberdeen.

Bandai Namco announced they are collaborating with Aardman Studios and game studio DigixArt on WWI game 11-11: Memories Retold.

A ROYAL is saddling up for the unveiling a hampshrie 's tribute to horses that died on the battlefield in the Great War.

SEVEN war memorials in Hampshire are among hundreds to be listed in a bid to protect thousands of memorials by next year - marking the centenary of the end of the First World War.

Despite a last minute cancellation of some of the final performances, the free 38th Annual Detroit Jazz festival provided a ray of light shining down on the festival goers experiencing new and familar regional and national acts all Labor Day weekend in downtown Detroit.

IN 1945 my late father, Peter Samuel Winton, was 18 years old and a merchant seaman sailing from Southampton on the dangerous Atlantic Convoy Run.

THIS picture of a VE Day children’s party took place in Eastleigh, we do not know the exact date of the picture, but it was most likely on or around VE Day.

THIS photograph was taken by an Echo photographer on VE night and I was printed in the newspaper soon afterwards.

Celebrating the life of a once vibrant lane, soon to be lost due to development.

Steve Avillo, a childhood friend of Joey's, and Joey have a Zoom call to trade childhood stories. Steve gives his point of view of some of Joey's craziest stories and even reminds Joey of some stories that he forgot. 

Joey's going to be doing this type of podcast more often, to introduce you to the people who made Joey who he is today. 

Follow Steve's band, The Past Masters at http://tpmrocks.com/

Kings Heath Walk of Fame honour for cycling legend.

Birmingham celebrates 550th birth anniversary of founder of Sikh faith.

Sonic Sirius has announced availability of the Abc Soundset, a collection of 128 presets for the Messiah by Memory Moon, a software synthesizer inspired by the Prophet-5 polyphonic analog synth by Sequential Circuits. The soundset is suitable for Synth-Pop, New Wave, Electro, and other modern synth music. It includes arpeggios, bass, keys, leads, pads, and […]

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