An integrated-circuit memory controller outputs to a memory device a first signal in a first state to enable operation of synchronous data transmission and reception circuits within the memory device. A transaction queue within the memory controller stores memory read and write requests that, to be serviced, require operation of the synchronous data transmission and reception circuits, respectively, within the memory device. Power control circuitry within the memory controller determines that the transaction queue has reached a predetermined state and, in response, outputs the first signal to the memory device in a second state to disable operation of the synchronous data transmission and reception circuits within the memory device.

The present invention relates to a thermochromic color-memory composition containing: (I) an electron donating coloring organic compound, (II) an electron accepting compound, and (III) an ester compound represented by the following formula (1) as a reaction medium which controls color reaction of the components (I) and (II): (in the formula, X represents any of a hydrogen atom, an alkyl group having 1 to 4 carbon atoms, an alkoxy group having 1 to 4 carbon atoms, and a halogen atom, m represents an integer of from 1 to 3, and n represents an integer of from 1 to 20).

A method (and system) of emulation in a multiprocessor system, includes performing an emulation in which a host multiprocessing system of the multiprocessor system supports a weak consistency model, and the target multiprocessing system of the multiprocessor system supports a strong consistency model.

Various technologies and techniques are disclosed for using transactional memory hardware to accelerate virtualization or emulation. State isolation can be facilitated by providing isolated private state on transactional memory hardware and storing the stack of a host that is performing an emulation in the isolated private state. Memory accesses performed by a central processing unit can be monitored by software to detect that a guest being emulated has made a self modification to its own code sequence. Transactional memory hardware can be used to facilitate dispatch table updates in multithreaded environments by taking advantage of the atomic commit feature. An emulator is provided that uses a dispatch table stored in main memory to convert a guest program counter into a host program counter. The dispatch table is accessed to see if the dispatch table contains a particular host program counter for a particular guest program counter.

An energy harvesting system comprises a first region having a first temperature and a second region. A conduit is located at least partially within the first region. A heat engine configured for converting thermal energy to mechanical energy includes a shape memory alloy forming at least one generally continuous loop. The shape memory alloy is disposed in heat exchange contact with the first region and the second region. The shape memory alloy is driven to rotate around at least a portion of the conduit by the response of the shape memory alloy to the temperature difference between the first region and the second region. At least one pulley is driven by the rotation of the shape memory alloy, and the at least one pulley is operatively connected to a component to thereby drive the component.

A method for communication between computing devices includes identifying the parameters of a data transfer between a source computing device and a target computing device and identifying communication paths between a source computing device and target computing device, in which at least one of the communications paths is a physical network. A communication path is selected for the data transfer. When a data transfer over the physical network is selected as a communication path, a nonvolatile memory (NVM) unit is removed from the source computing device and placed in a cartridge and the cartridge is programmed with transfer information. The NVM unit and cartridge are transported through the physical network to the target computing device according to the transfer information and the NVM unit is electrically connected to the target computing device.

The present invention relates to a thermochromic color-memory toner containing: a microcapsule pigment encapsulating a thermochromic color-memory composition; and a binder resin, in which the microcapsule pigment shows a hysteresis characteristic that, in a temperature-rise process, decoloration starts when the temperature reaches t3 and the pigment completely reaches a decolored state in a temperature region of t4 or higher, and in a temperature-drop process, coloration starts when the temperature reaches t2 and the pigment completely reaches a colored state in a temperature region of ti or lower, and ti is in a range of from −50 to 0° C. and t4 is in a range of from 50 to 150° C.

Methods and systems for allocating memory of user terminals are disclosed. A user terminal may determine a weight for one or more categories, each category being associated with Internet information to be broadcast. The user terminal also may determine an available memory size of memory and may allocate memory to the one or more categories for storing the Internet information based on the weights and the available memory size.

A system for occluding a physical anomaly. One embodiment comprises a shape memory material body wherein the shape memory material body fits within the physical anomaly occluding the physical anomaly. The shape memory material body has a primary shape for occluding the physical anomaly and a secondary shape for being positioned in the physical anomaly.

A wireless media player and a related system and methodology are disclosed. One aspect of the wireless media player system pertains to a virtual connector system, apparatus, and method for the automatic establishment of wireless connectivity with other electronic devices. In one embodiment, the media player device employs the use of integrated Radio Frequency Identification (RFID) technology to exchange communication settings, media capability, and other parameters with an external device that also has integrated RFID technology. The automatic exchange of settings and other information via a proximity-based RFID data exchange allows a media player to quickly establish a secure communication link with another device via a commonly supported wireless protocol such as Ultra Wideband (UWB) or Bluetooth. Another aspect of the media player system pertains to a method of using the captured media capability of the connecting device to customize certain menu options and software parameters in the media player.

An apparatus comprising a plurality of chambers for receiving an associated plurality of staples, each formed with a shape memory that allows the staple to adopt a straightened configuration, when placed in a stapler, and a deployed configuration for suturing when released from the stapler; and a sleeve moveable relative to the chambers between a first position, in which the staples are trapped by the sleeve within the chambers in the straightened configuration, and a second position, whereby the staples are freed to adopt the deployed configuration, wherein the sleeve is adapted to move between the first and second positions by rotating relative to the chambers.

A counter in a non-volatile memory including at least two sub-counters, each counting with a different modulo, an increment of the counter being transferred on a single one of the sub-counters and the sub-counters being incremented sequentially.

A method for quickly calibrating a memory interface circuit from time to time in conjunction with operation of a functional circuit is described. The method uses controlling the memory interface circuit with respect to read data capture for byte lanes, including controlling CAS latency compensation for the byte lanes. In the method control settings for controlling CAS latency compensation are determined and set according to a dynamic calibration procedure performed from time to time in conjunction with functional operation of a circuit system containing one or more memory devices connected to the memory interface circuit. In the method, determining and setting the control settings for controlling CAS latency compensation is performed independently and parallely in each of the byte lanes.

A multi-chip package is provided. The multi-chip package includes a plurality of chips including at least one bad chip and at least one good chip that are stacked and a plurality of through electrodes each penetrating the chips. A logic circuit included in the at least one bad chip is isolated from each of the plurality of through electrodes.

Methods for fabricating integrated circuits include fabricating a logic device on a substrate, forming an intermediate semiconductor substrate on a surface of the logic device, and fabricating a capacitor-less memory cell on the intermediate semiconductor substrate. Integrated circuits with capacitor-less memory cells formed on a surface of a logic device are also disclosed, as are multi-core microprocessors including such integrated circuits.

A method for enhancing sales of stadium seat memorabilia by utilizing a stabilizing base, with a large surface area in the shape of sports memorabilia, such as baseball bats and/or sports figures, with or without brackets, to mount and stabilize a stadium seat for use outside of the stadium, such as at home or in a commercial setting.

A method applied in a tuning circuit comprising a plurality of turning cells is disclosed. the method comprises: laying out a array of tuning cells in a matrix configuration, the matrix comprising a first dimension and a second dimension; assigning a first index associated with the first dimension and a second index associated with the second dimension to each tuning cell; controlling each tuning cell using a word line and a bit line; and summing up outputs from all tuning cells to form a combined output. The tuning cell provides a first circuit value or a second circuit value according to the logical value of the bit line, and the difference between the first circuit value and the second circuit value is determined such that a turning resolution of the tuning circuit is determined.

A printing device includes at least one printing engine that has actuators and sensors. At least one engine controller is operatively connected to the printing engine, the engine controller uses software to control operations of the printing engine. At least one non-volatile memory is operatively connected to the engine controller. The non-volatile memory stores values used by the engine controller to control operations of the printing engine. Further, at least one adapter card is operatively connected to the non-volatile memory and to the actuators and sensors. The adapter card stores data and receives sensor feedback from the sensors. The adapter card uses the data and the sensor feedback to control the actuators by bypassing the engine controller when communicating with the actuators. The adapter card provides adapter card feedback to the non-volatile memory.

A system and method are disclosed to accomplish power savings in an electronic device, such as a memory chip, by performing selective frequency locking and subsequent instantaneous frequency switching in the DLL (delay locked loop) used for clock synchronization in the electronic device. By locking the DLL at a slow clock frequency, the operational frequency may be substantially instantaneously switched to an integer-multiplied frequency of the initial locking frequency without losing the DLL lock point. This DLL locking methodology allows for faster frequency changes from higher (during normal operation) to lower (during a power saving mode) clock frequencies without resorting to gradual frequency slewing to conserve power and maintain DLL locking. Hence, a large power reduction may be accomplished substantially instantaneously without adding complexity to the system clock generator. Because of the rules governing abstracts, this abstract should not be used in construing the claims.

An integrated circuit includes a circuit block to utilize a load current at a load voltage from a power input and two or more charge pump arrays. The outputs of the charge pump arrays are coupled to the power input of the circuit block. The integrated circuit includes one or more modifiable elements to disable one or more of the two or more charge pump arrays.

A demodulator processes a continuous-time signal to generate at a plurality of encoded bits. An inner decoder processes a first subset of bits within the plurality of encoded bits to correct selected ones of the first subset of bits to form a corrected first subset of bits and to generate partially corrected data from the plurality of encoded bits based on the corrected first subset of bits. An outer decoder processes the partially decoded data, to correct selected ones of a second subset of the plurality of encoded bits to form a corrected second subset of bits. A bit combiner generates data estimates by combining the corrected first subset of bits and the corrected second subset of bits.

Methods, apparatuses, and computer program products for improving memory training results corresponding to a plurality of memory modules are provided. Embodiments include detecting a hardware configuration change upon initiating a boot sequence of a system that includes the plurality of memory modules; generating for a plurality of training iterations, reference training values corresponding to aligning of a data strobe (DQS) signal with a data valid window of data (DQ) lines of the plurality of memory modules; identifying for each training iteration, any outer values within the reference training values generated for that training iteration; eliminating the identified outer values from the reference training values; generating a final reference training value based on an average of the remaining reference training values; and using the final reference training value as the DQ-DQS timing value for the boot sequence of the system.

In the present disclosure, there is disclosed a communication device including a pre-loading module configured to retrieve a first and a second set of flyer image tiles from a flyer image tile set stored in memory, the first set of flyer image tiles being associated with the most zoomed-out state and the second set of flyer image tiles being associated with a zoom level of a current viewport. The pre-loading module is further configured to associate the first set of flyer image tiles with an underlay viewport. The communication device further includes a display configured to display the first set of flyer image tiles in the underlay viewport that are visible in the current viewport and overlay the second set of flyer image tiles visible in the current viewport onto the first set of flyer image tiles.

Provided are three-dimensional nonvolatile memory devices and methods of fabricating the same. The memory devices include semiconductor pillars penetrating interlayer insulating layers and conductive layers alternately stacked on a substrate and electrically connected to the substrate and floating gates selectively interposed between the semiconductor pillars and the conductive layers. The floating gates are formed in recesses in the conductive layers.

A low resistivity interface material is provided between a self-aligned vertical heater element and a contact region of a selection device. A phase change chalcogenide material is deposited directly on the vertical heater element. In an embodiment, the vertical heater element in L-shaped, having a curved vertical wall along the wordline direction and a horizontal base. In an embodiment, the low resistivity interface material is deposited into a trench with a negative profile using a PVD technique. An upper surface of the low resistivity interface material may have a tapered bird-beak extension.

A multi-standard flash-memory-card carrier is about the same size as a thick credit card and fits into a wallet. The multi-standard flash-memory-card carrier has bays that accept flash-memory cards. Larger bays on one side receive SD cards and a Memory Stick Duo card, while micro bays on another side of the carrier receive microSD cards and Memory Stick Micro cards. A carrier spine sandwiched between top and bottom covers has openings forming the bays. Spring-clip tabs on spring-clip fingers fit into notches on the side of the flash-memory cards to secure the flash-memory cards into the multi-standard flash-memory-card carrier to prevent loss. The spring-clip fingers are movable parts of the carrier spine that are deformed during insertion of the flash-memory cards. Both micro and standard flash-memory cards can be carried in the same multi-standard flash-memory-card carrier that can be placed in plastic sleeves for credit cards in a person's wallet.

A preload mechanism for a memory alloy wire actuator is disclosed that includes a rotating element configured to rotate about a pivot. The rotating element has a first contact point that is configured to couple to the memory alloy wire actuator such that contraction of the memory alloy wire actuator displaces the first contact point such that the rotating element rotates from a first position to a second position. The preload mechanism also includes a bias element with a first end that is coupled to a second contact point of the rotating element and a second end configured to be pinned relative to the pivot. The bias element has a line of action extending from the second end through the first end. The line of action has an offset distance that is the minimum distance between the line of action and the pivot. The offset distance has a first value when the rotating element is in the first position and a second value when the rotating element is the second position, the second value being smaller than the first value.

Memory conserving versioning of an electronic document is provided. Client versioning factors are analyzed by a client versioning engine and server versioning factors are analyzed by a server versioning engine for determining when an electronic document should be stored as a new version. Accordingly, new versions of an electronic document are only created when determined to be sufficiently important, thus reducing the amount of memory required for increased version payload.

An actuator comprises an elongated shape-memory element wound around a first element and having one first end connected to the first element and one second end connected to a second element. Heating means are provided for heating the shape-memory element in order to obtain a displacement of one of the ends thereof. The elongated shape-memory element is guided so that it can slide within a closed channel made of a material having a low coefficient of friction, for example defined by a sheath.

Apparatus and methods are disclosed, such as a method that includes precharging channel material of a string of memory cells in an unselected sub-block of a block of memory cells to a precharge voltage during a first portion of a programming operation. A programming voltage can then he applied to a selected memory cell in a selected sub-block of the block of memory cells during a second portion of the programming operation. The selected memory cell is coupled to a same access line as an unselected memory cell in the unselected sub-block. Additional methods and apparatus are disclosed.

A semiconductor memory device includes first and second memory cells, each of which includes a charge storage layer, a first bit line that is connected to the first memory cell, and a second bit line that is connected to the second memory cell. A writing operation includes multiple loops of a programming operation and a verification operation, and first data is written in the first memory cell, and second data different from the first data is written in the second memory cell through the writing operation. In a first loop of the writing operation, a first voltage is applied to the first bit line and the second bit line is maintained in an electrically floating state during the programming operation, and a verification operation relating to the second data is not performed and a verification operation relating to the first data is performed.

A nonvolatile memory device is provided as follows. A memory cell array includes a plurality of memory cells. An address decoder provides a first verify voltage to selected memory cells among the plurality of memory cells in a first program loop and provides a second verify voltage to the selected memory cells in a second program loop. A control logic determines the second program loop as a verify voltage offset point in which the first verify voltage is changed to the second verify voltage based on a result of a verify operation of the first program loop.

A programmable memory including a self-latching read data path. A sense amplifier senses the voltage level at a bit line, the bit line communicating the data state of a selected memory cell in its associated column. A data latch coupled to the output of the sense amplifier passes the sensed data state. Set-reset logic is provided that receives the output of the data latch in the read data path and, in response to a transition of the data state in a read cycle, latches the data latch and isolates it from the sense amplifier. The set-reset logic resets the data latch at the start of the next read cycle. In some embodiments, a timer is provided so that the latch is reset after a time-out period in a long read cycle in which no data transition occurs.

A radiation hardened memory cell includes an odd number of storage elements configured to redundantly store an input data logic signal. The storage elements include output lines for outputting respective logic signals having respective logic values. A logic combination network receives the respective logic signals and is configured to generate an output signal having a same logic value as a majority of the logic signals output from the storage elements. An exclusive logic sum circuit receives the respective logic signals output from the storage elements and is configured to produce a refresh of the logic data signal as stored in the storage elements when one of the logic signals output from the storage elements undergoes a logic value transition due to an error event.

A read sensing method for an OTP non-volatile memory is provided. The memory array is connected with plural bit lines. Firstly, a selected memory cell of the memory array is determined, wherein one of the plural bit lines connected with the selected memory cell is a selected bit line and the other bit lines are unselected bit lines. Then, the unselected bit lines are precharged to a precharge voltage. Then, the selected bit line is connected with the data line, and the data line is discharged to a reset voltage. After a cell current from the selected memory cell is received, a voltage level of the data line is gradually changed from the reset voltage. According to at least one result of comparing a voltage level of the data line with a comparing voltage, an output signal is generated.

To provide a magnetic element capable of performing skyrmion transfer, a skyrmion memory to which this magnetic element is applied, and a shift register, for example, a magnetic element capable of performing skyrmion transfer is provided, the magnetic element providing a transverse transfer arrangement in which the skyrmion is transferred substantially perpendicular to a current between an upstream electrode and a downstream electrode, and including a plurality of stable positions in which the skyrmion exists more stably than in other regions of a magnet, and a skyrmion sensor that detects a position of the skyrmion.

To provide a magnetic element which can generate a skyrmion, and a skyrmion memory which applies the magnetic element or the like. To provide a magnetic element with a chiral magnet for generating a skyrmion, the chiral magnet is made of a magnetic material having a β-Mn type crystal structure. Also, to provide a magnetic element with a chiral magnet for generating a skyrmion, the chiral magnet is made of a magnetic material having an Au4Al type crystal structure.

A magnetic element capable of generating and erasing a skyrmion, including a magnet shaped as a thin layer and including a structure surrounded by a nonmagnetic material; a current path provided surrounding an end region including an end portion of the magnet, on one surface of the magnet; and a skyrmion sensor that detects the generation and erasing of the skyrmion. With Wm being width of the magnet and hm being height of the magnet, a size of the magnet, with the skyrmion of a diameter λ being generated, is such that 2λ>Wm>λ/2 and 2λ>hm>λ/2. With W being width of the end region in a direction parallel to the end portion of the magnet and h being height of the end region in a direction perpendicular to the end portion of the magnet, the end region is such that λ≧W>λ/4 and 2λ>h>λ/2.

A nonvolatile memory circuit may include: a cell array including a first region comprising a plurality of first cell groups and a second region comprising a plurality of second cell groups, each of the first and second cell groups having one or more nonvolatile memory cells; and a control unit suitable for controlling the cell array to sequentially output repair addresses of the plurality of cells groups included in a region which is not over used among the first and second regions when one of the first and second regions is over used.

An SRAM includes an SRAM array comprising a plurality of SRAM cells arranged in a matrix. Each of the SRAM cells includes six vertical field effect transistors. The SRAM array includes a plurality of groups of conductive regions extending in the column direction. Each of the plurality of groups of conductive regions includes a first to a fourth conductive region arranged in this order in the row direction, and the first to fourth conductive regions are separated by insulating regions from each other. The first, second and third conductive regions are coupled to sources of first conductive type VFETs, and the fourth conductive region is coupled to sources of second conductive type VFETs. The plurality of groups are arranged in the row direction such that the fourth conductive region of one group of conductive regions is adjacent to the first conductive region of adjacent one group of conductive regions.

A compact CMOS anti-fuse memory cell. In one aspect, an apparatus includes an N− well and an anti-fuse cell formed on the N− well. The anti-fuse cell includes a lightly doped drain (LDD) region deposited in the N− well, an oxide layer deposited on the N− well and having an overlapping region that overlaps the LDD region, and a control gate deposited on the oxide layer, wherein a bit of the anti-fuse cell is programmed when a voltage difference between the control gate and the LDD region exceeds a voltage threshold of the oxide layer and forms a leakage path from the control gate to the LDD region, and wherein the leakage path is confined to occur in the overlapping region.

The invention relates to an integrated circuit (1), comprising: a field-effect transistor (2), comprising:first and second conduction electrodes (201, 202);a channel zone (203) arranged between the first and second conduction electrodes;a gate stack (220) arranged vertically in line with the channel zone, and comprising a gate electrode (222);an RRAM-type memory point (31) formed under the channel zone, or formed in the gate stack under the gate electrode.

Provided is a magnetic element capable of generating one skyrmion and erasing the one skyrmion. The magnetic element includes a magnet shaped like a substantially rectangular flat plate, an upstream electrode connected to the magnet in a width Wm direction of the magnet and made of a non-magnetic metal, a downstream electrode connected to the magnet in the width Wm direction to oppose the upstream electrode and made of a non-magnetic metal, and a skyrmion sensor configured to detect the skyrmion. Here, a width Wm of the substantially rectangular magnet is such that 3·λ>Wm≧λ, where λ denotes a diameter of the skyrmion, a length Hm of the substantially rectangular magnet is such that 2·λ>Hm≧λ, and the magnet has a notch structure at the edge between the upstream electrode and the downstream electrode.

A magnetic memory of an embodiment includes: a first to third terminals; a magnetoresistive element including a first magnetic layer, a second magnetic layer, and a first nonmagnetic layer; a second nonmagnetic layer including a first to third portions, the first portion being located between the second and the third portions, the second and third portions being electrically connected to the second and third terminals respectively, the first magnetic layer being disposed between the first portion and the first nonmagnetic layer; and a third nonmagnetic layer including a fourth to sixth portions, the fourth portion being located between the first portion and the first magnetic layer, the fifth portion including a first region extending from the magnetoresistive element to the second terminal, the sixth portion including a second region extending from the magnetoresistive element to the third terminal.

Examples of the present disclosure provide apparatuses and methods for performing shift operations in a memory. An example method comprises performing a shift operation a first element stored in a first group of memory cells coupled to a first access line and a number of sense lines of a memory array and a second element stored in a second group of memory cells coupled to a second access line and the number of sense lines of the memory array. The method can include shifting the first element by a number of bit positions defined by the second element by performing a number of AND operations, OR operations, SHIFT operations, and INVERT operations performed without transferring data via an input/output (I/O) line.

A memory circuit may be provided. The memory circuit may include a memory array. The memory circuit may include an input and output path circuit coupled to a probe pad and a bump pad, and may be configured to input and output a signal between an exterior of the memory circuit and the memory array. The memory circuit may include a scanning circuit configured to generate a sensing signal by sensing a signal outputted through the bump pad while performing scanning of at least one of a reference voltage and a test strobe signal.

A circuit and method for adaptive trimming of the reference signal for sensing data during a read operation of magnetic memory cells to improve read margin for the magnetic memory cells. The circuit has a trim one-time programmable memory array programmed with offset trim data applied to magnetic memory array sense amplifiers. Sense amplifier trimming circuits receive and decode the trim data to determine offset trim signal magnitude to adjust the reference signal to improve the read margin. The method sets the offset trim level to each increment of the offset trim level. Data is written and read to the magnetic memory array, the number of errors in the array is accumulated for each setting of the offset trim level. The error levels are compared and the appropriate trim level is programmed to the trim memory cells such that a read margin of the sense amplifier is improved.

Systems, devices and methods are disclosed. In an embodiment of one such method, a method of decoding received command signals, the method comprises decoding the received command signals in combination with a signal provided to a memory address node at a first clock edge of a clock signal to generate a plurality of memory control signals. The received command signals, in combination with the signal provided to the memory address node at the first clock edge of the clock signal, represent a memory command. Furthermore, the signal provided to the memory address node at a second clock edge of the clock signal is not decoded in combination with the received command signals. The memory command may be a reduced power command and/or a no operation command.

An address generation circuit may include: a first latch unit suitable for latching an address obtained by inverting a part of an input address; a second latch unit suitable for latching the partly inverted input address of the first latch unit, and suitable for latching an added/subtracted address after a first refresh operation during a target refresh period; a third latch unit suitable for latching the partly inverted input address of the first latch unit during a period other than the target refresh period; and an addition/subtraction unit suitable for generating the added/subtracted address by adding/subtracting a predetermined value to/from the latched address of the second latch unit.

A semiconductor memory device may include: a plurality of memory mats; and a plurality of sense amplifier arrays arranged alternately with the memory mats, each sense amplifier array being suitable for sensing and amplifying data of memory mats adjacent thereto, wherein during a data sensing operation to a memory mat among the plurality of memory mats, in addition to a sense amplifier for the memory mat and sense amplifiers positioned immediately above and below the sense amplifier for the memory mat, at least one additional sense amplifier closest to the sense amplifier for the memory mat is also activated for providing additional amplification.