DEPARTMENT OF STATE: Office of the Alcoholic Beverage Control Commissioner

Noted Kannada actor and director Guruprasad was found dead in his Bengaluru apartment today, the police said.

A controversy over a WhatsApp group named 'Mallu Hindu Officers', allegedly administered by Kerala Industry and Commerce Department Director K. Gopalakrishnan, is in the spotlight.

Kerala Chief Minister and veteran Marxist leader Pinarayi Vijayan intensified his attack on the Congress, alleging that its general secretary, Priyanka Gandhi Vadra, is contesting the Wayanad Lok Sabha by-election with the backing of Jamaat-e-Islami.

One of the wonderful aspects about my client-facing role at SAS is the breadth of audiences that I get to work with. No matter where you fall on this list: Data engineer. Business or marketing analyst. Citizen data scientist. Data scientist. Statistician. Executive. One topic is certain: We all love [...]

SAS Customer Intelligence 360: Automated explanation and supervised segmentation was published on Customer Intelligence Blog.

Read the in depth Review of Blaupunkt SBWL03 Soundbar Audio Video. Know detailed info about Blaupunkt SBWL03 Soundbar configuration, design and performance quality along with pros & cons, Digit rating, verdict based on user opinions/feedback.

Read the in depth Review of Blaupunkt Cybersound 43 inch 4K LED TV TV. Know detailed info about Blaupunkt Cybersound 43 inch 4K LED TV configuration, design and performance quality along with pros & cons, Digit rating, verdict based on user opinions/feedback.

Read the in depth Review of Logitech G Pro X SUPERLIGHT Gaming. Know detailed info about Logitech G Pro X SUPERLIGHT configuration, design and performance quality along with pros & cons, Digit rating, verdict based on user opinions/feedback.

Need more space on your Google Account? Here are a few tips to help you free up more space in your Google Account. We've listed down six different methods to help you free up more space

I am gratified to see the continuing adoption of Forecast Value Added by organizations worldwide. FVA is an easy to understand and easy to apply approach for identifying bad practices in your forecasting process. And I'm particularly gratified to see coverage of FVA in two new books, which the authors [...]

The post Vandeput's Data Science for Supply Chain Forecasting (book excerpt) appeared first on The Business Forecasting Deal.

A year-old murder case has been re-opened in Uttar Pradesh's Meerut after a hired killer, who is out on bail, approached the police for not being paid a ransom for the job.

In a horrifying incident at a fair in Kannauj, Uttar Pradesh, a teenage girl's hair became entangled in the roller of a swing, resulting in her entire scalp being ripped out.

A Bengaluru couple found themselves in legal trouble after they posted videos of their balcony garden on Facebook. The posts included images of plants later identified as ganja.

Industrialist Ratan Tata, who passed away at the age of 86, is credited with transforming the Tata Group's portfolio during his tenure as chairman to include products from salt to software to sports cars.

1. Pushpa 2: Sreeleela’s ‘Kissik’ song shoot wrapped up  123telugu
2. Sreeleela Earns 60 Percent Less Than Samantha Ruth Prabhu For Pushpa 2 Song? Fee Details Out  News18
3. Sreeleela's Remuneration For Pushpa 2 Item Song: Hottie Gets Only 40% Of What Samantha Got For Oo Antava  Oneindia
4. Sreeleela's renumeration for 'Pushpa 2' item song revealed; Is way lower than Samantha's 'Oo Antava'  TOI Etimes
5. Meet Sreeleela who has replaced Samantha Ruth Prabhu in Pushpa 2's hot item song; her photo with Allu Arjun l  India.com

1. Battered Reliance Shares To Make A Comeback? This Analyst Sees 29% Upside Ahead  Benzinga India
2. Reliance Industries shares may see 30% upside according to CLSA, who cites this key trigger  CNBCTV18
3. RIL shares are down 20% from record high, oversold on charts; here's what analysts say  Business Today
4. Six of India’s top 10 most valuable firms shed Rs 1.55 lakh crore in market value  Moneycontrol
5. Reliance Industries Share Price Today on 13-11-2024: Reliance Industries share price are down by -0.63%, Nifty down by -0.8%  Mint

1. Stock market today: Trade setup for Nifty 50 to Q2 results today; five stocks to buy or sell on Wednesday — Nov 13 | Stock Market News  Mint
2. Sensex, Nifty50 decline for 5th straight session; now down over 9% from peak  Mint
3. Indices trade with deep cuts; auto shares decline for 5th day  Business Standard
4. Stock Market LIVE Updates: Nifty at 23,700, Sensex tanks 520 pts; auto, metal, realty major drag  Moneycontrol
5. GIFT Nifty down 45 points; here's the trading setup for today's session  The Economic Times

1. Elon Musk, Vivek Ramaswamy to lead DOGE to clean up US bureaucracy: Trump  India Today
2. Trump’s 'Manhattan Project' of government reform: Musk and Ramaswamy to lead efficiency crusade  The Times of India
3. Democrat Senator's 'efficient' dig at Elon Musk-Vivek Ramaswamy heading DOGE  India Today
4. Donald Trump picks Elon Musk, Vivek Ramaswamy to lead newly formed Department of Government Efficiency (DOGE)  The Hindu
5. A dope for DOGE (and Dogecoin): Trump taps Musk in efficiency team, crypto fans rejoice  The Economic Times

1. BREAKING| 'Bulldozer Reminds Of Lawlessness' : Supreme Court Says Properties Can't Be Demolished Merely...  Live Law - Indian Legal News
2. "Officials To Pay From Salary": Top Court Guidelines On 'Bulldozer Justice'  NDTV
3. ‘Heavens won’t fall on authorities if they hold their hands for some period’: SC sets pan India guidelines against bulldozer action  The Financial Express
4. Executive Can't Become Judge, Pronounce Guilt Of Persons & Punish Them By Demolishing Their Properties :...  Live Law - Indian Legal News
5. ‘Officials will pay for demolitions from their salary’: 5 Key SC observations on ‘chilling’ side of ‘bulldozer justice’  Mint

The headphones come with a rather lightweight design, Sony's integrated V1 processor and noise-cancelling duties.

The post Save up to 40% with the Sony WH-CH720N Headphones! appeared first on Phandroid.

The TicWatch Pro 3 Ultra packs some nifty features, in addition to impressive battery endurance.

The post Save up to 50% with the TicWatch Pro 3 Ultra! appeared first on Phandroid.

In a unique online romance scam, a man in Tianjin, China, fell victim to a bizarre "marriage bed burning" ritual, costing him Rs 11 lakh.

Kapil Sharma wasted no time in diving into their personal stories, focusing on how Deepinder met his Mexican wife.

Positioned near the side of her head, the eye provides an expansive field of vision, while a thick layer of protective blubber shields it from harm and maintains warmth.

The $20 Merry Multiplier scratch-off ticket she chose turned out to be a $250,000 top prize winner.

The couple, together for nine years, had announced the wedding date in January and were eagerly looking forward to their long-awaited special day.

[The Conversation Africa] Despite the flaws in the latest novel by South African writer Nthikeng Mohlele, there is something alluring about Revolutionaries' House. It is Mohlele's most political novel, and the parallels drawn between love and politics - and their pitfalls - are intriguing.

We are currently setting up the Tempus flow and have ran into some mismatched data regarding ECO and timing reports. I generated a timing report before running ECO and saw six total setup violations. When running opt_signoff -setup, the initial setup summary that was printed in the shell only showed one violation. I can see that violation from the initial setup summary in my pre-ECO timing report and it is not the worst path. Upon further investigation, I forced the tool to try to fix setup on one of the other five violations from the timing report using the opt_signoff_select_setup_endpoints attribute and the tool said that the endpoint had positive slack and would be ignored.

Has anyone experienced something like this before?

Hi, I'm using genus (Version 21.14-s082_1) to synthesis a VHDL-design with multiple power-domains. After reading the power intent file and calling 'apply_power_intent',  I get the following warning:

Warning : Potential problem while applying power intent of 1801 file. [1801-99]
: Cannot find any instance for scope '/:CHIP_TOP'. Rest of commands in this scope will be skipped (set_scope:../../upf/CHIP_TOP.upf:2).
: Check the power intent. If the scenario is expected, this message can be ignored.

The fist two lines of CHIP_TOP.upf:

upf_version 3.1
set_scope :CHIP_TOP

I simulated the same  UPF and VHDL files with Xeclium and was able to verify all the IEEE1801/UPF aspects I need without any problems. I don't know, why genus is having a problem with the 'scope'.
In genus, after getting the warning, running 'set_db power_domain:CHIP_TOP/BLOCK_A/PD_CORE_D .library_domain PD0V5' returns the following error:

Error : <Start> word is not recognized. [TUI-182] [set_db]
: 'power_domain:CHIP_TOP/BLOCK/PD_CORE_D' is not a recognized object/attribute. Type 'help root:' to get a list of all supported objects and attributes.
: Check if the given <Start> word is a valid object_type, object or attribute.

Running 'commit_power_intent' gives me:

Started inserting low power cells...
====================================
Info : Command 'commit_power_intent' cannot proceed as there are no power domains present. [CPI-507]
: Design with no power domains is 'design:CHIP_TOP'.
Completed inserting low power cells (runtime 0.00).
====================================================

I'm suspecting that the problem lies in 'set_scope' and VHDL. I never had such problems with Verilog. I tried every way to reference the hierarchy in the code and now I'm at my wit's end and I need your help o/
How to set the scope with 'set_scope' in UPD 3.1 to the toplevel in VHDL, so that genus accepts it? Or is the problem caused by something else?

Best,

Iqbal

When starting a new design, it's important to take the time to consider design recommendations that prevent problems that can arise later in the design cycle. This two-part compilation of guidelines for starting a new design is the result of years of Cadence AWR Design Environment platform Support experience with designs. Pre-design decisions for user interface, simulation, layout, and library configuration lay the groundwork for a successful and efficient AWR design. This blog covers the user interface (UI) and simulation considerations designers should note prior to starting a design.(read more)

When starting a new design, it's important to take the time to consider design recommendations that prevent problems that can arise later in the design cycle. This two-part compilation of guidelines for starting a new design is the result of years of Cadence AWR Design Environment platform Support experience with designs. Pre-design decisions for user interface, simulation, layout, and library configuration lay the groundwork for a successful and efficient AWR design. This blog, part 2, covers the layout and component library considerations designers should note prior to starting a design.(read more)

I am trying to understand the Linting process. I know that mainly JasperGold is the tool for this purpose. Though I think JasperGold is more suited for later stages of the design. As a RTL Design Engineer, I want to make sure that if another tool has the capability of doing Linting earlier in the flow. for example, does Xcelium, Genus or Confomal support linting. I have seen some contradicting information online regarding this topic, though I can't find anything related to Linting on any of these tools.

Thanks

As technology continues to evolve at a rapid pace, the importance of robust and efficient interconnect standards cannot be overstated. Peripheral Component Interconnect Express (PCIe) has been a cornerstone in high-speed data transfer, enabling seamless communication between various hardware components.   

With the advent of PCIe 6.1 ECN, a significant advancement in speed and efficiency, ensuring the accuracy and reliability of its operations is paramount. One critical aspect of this is the verification of shared credit updates. For detailed understanding on Shared Credit, please refer Understanding PCIe 6.0 Shared Flow Control. 

In this blog, we will discuss why this verification is essential and what it entails.  

Introduction 

PCIe 6.1 ECN brings numerous advancements over earlier versions, such as increased bandwidth and faster data transfer speeds.   

A crucial mechanism for efficient data transmission in PCIe 6.0 is the credit-based flow control system. In this system, devices monitor credits, representing the buffer capacity available for incoming data.   

When a device transmits data, it uses credits, which are replenished or adjusted once the data is received and processed. This system ensures that the sender does not overload the receiver.  

Given the critical role of shared credit updates in maintaining the integrity and efficiency of data transfers, verification of these updates is crucial.  Proper management of credit updates is essential to ensure data integrity, as any discrepancies can lead to data loss, corruption, or system crashes.   

Verification also guarantees efficient resource allocation, preventing scenarios where some components are starved of credit while others have an excess, thus avoiding inefficiencies.  Credit inefficiencies pose issues in low power negotiations by preventing devices from entering low power states. Additionally, verification involves checking for proper error handling mechanisms, ensuring that the system can recover gracefully from errors in credit updates and maintain overall stability.   

PCIe 6.1 ECN Flow Control Optimizations Over PCIe 6.0

PCIe 6.1 ECN builds on the FLIT-based architecture introduced in PCIe 6.0, further optimizing flow control mechanisms to handle increased data rates and improved efficiency.  PCIe 6.1 ECN introduced refinements in credit management, making the allocation and advertisement of credits more precise, which helps in reducing bottlenecks and improving data flow efficiency.  Enhancements in flow control protocols ensure better management of buffer spaces and more efficient credit allocation. These enhancements are designed to handle the increased data rates and throughput demands of next-generation applications, ensuring robust and efficient data flow across PCIe devices.  

Below are some major updates: 

1. There have been improvements in error detection and correction mechanisms in PCIe 6.1 ECN to enhance flow control reliability by ensuring that corrupted data packets are detected and handled appropriately without disrupting the flow of valid packets.  
2. The merged credit system, which was a key feature introduced int PCIe 6.0 to simplify and optimize credit management, was further enhanced in PCIe 6.1 ECN to improve performance and efficiency.  
3. PCIe 6.1 ECN introduced better algorithms for allocating and reclaiming merged credits to handle high data rates, introduced more robust error detection and correction mechanism reducing the degradation or system instability. 
4. PCIe 6.1 ECN provided clear guidelines on how to implement the merged credit system correctly, helping developers to implement more reliable systems. For more details, please refer to Specifications section 2.6.1 Flow Control (FC) Rules.

Summary 

In summary, PCIe 6.0 is a complex protocol with many verification challenges. You must understand many new Spec changes and think about the robust verification plan for the new features and backward compatible tests impacted by new features. Cadence’s PCIe 6.0 Verification IP is fully compliant with the latest PCIe Express 6.0 specifications and provides an effective and efficient way to verify the components interfacing with the PCIe 6.0 interface. Cadence VIP for PCIe 6.0 provides exhaustive verification of PCIe-based IP and SoCs, and we are working with early adopter customers to speed up every verification stage.   

More Information

For more info on how Cadence PCIe Verification IP and Triple Check VIP enable users to confidently verify PCIe 6.0, see VIP for PCI Express, VIP for Compute Express Link  and TripleCheck for PCI Express    

See the PCI-SIG website for more details on PCIe in general and the different PCI standards.  

For more information on PCIe 6.0 new features, please visit PCIeLaneMargin, PCIe6.0LaneMargin, and Demonstrating PCIe 6.0 Equalization Procedure.

How do we purge/remove the duplicated vias in the same location of the PCB editor? These vias are not the one stacked and they are just blind vias running in internal layers 12-14. I find there is an additional copy of the blind via at the same location. Not sure what caused this issue.

Allegro part of DPI does not support scaling above 150%

hello,

We have a number of workstations with version 17.2 that work on a floating license server

We want to know if it can be upgraded to version 17.4

If so, should the floating license server be upgraded as well?

In addition, how can you know where the license was purchased from?

Thanks!

Hello,

A mybe silly question came to my mind: When routing sense lines, is it better to hav them as close as possible to DUT or afer the decoupling capacitors ?

Force in red, sense in purple.

Best way is 1 or 2 ?

Thanks in advance and Merry Christmas to everybody !

Hi, 

When I try to run Monte Carlo it gives me a 3 items message for possible failure:

1. It says the machine selected in the current job setup policy isnot reachable

2. The Cadence hierarchy is not detected, not installed properly. or

3. Job start script (with a path and a name like swiftNetlistService#) is not found on the remote machines.

Any recommendation on how to fix this?

Hello everyone,

I hope you're all doing well. I’ve set up two testbenches (TB1 and TB2) for my Design Under Test (DUT) using Cadence IC6.1.8-64b.500.21 tools, as shown in the attached figure. The DUT has multiple views available: schematic, Calibre, Maestro, and Symbol, and each testbench uses the same DUT in different scenarios. Currently, I have to manually switch between these views, but I would like to streamline this process.

My goal is to use a single config view that allows me to switch between the schematic and the extracted (Calibre) views. Ideally, I would like to have a configuration file where making changes once would update both testbenches (TB1 and TB2) automatically. In other words, when I modify one config, both testbenches should reflect this update for a single simulation run.

I would really appreciate it if you could guide me on the following:

1. How to create a config view for my DUT that can be used to easily switch between the schematic and extracted views, impacting both TB1 and TB2.
2. Where to specify view priorities or other settings to control which view is used during simulation.
3. Best practices for using a config file in this scenario, so that it ensures consistency across multiple testbenches.

Please refer to the attached figure to get a better understanding of the setup I’m using, where both TB1 and TB2 include the same DUT with multiple available views.

Thank you so much for your time and assistance!

I exported vplan to .odf file in vManager and after editing it I imported it to vManager. The vplan was expected to be synchronized and updated. However, nothing has changed to it. Does anyone know why?

Please include a brief summary of how to use it.

With the latest release (Sigrity and Systems Analysis 2022.1 HF2) of Clarity  3D Solver, support for encrypted component models is now available. With this functionality, vendors that supply 3D components, such as connectors, can now merge their...(read more)

I get multiple results at the same frequency in a 3-tone simulation.

I try to determine the IP3 of a mixer. I have 3 large signal tones: 0.75 GHz, 1.25 GHz and 1.26 GHz.

At the IM3 frequency of 490 MHz I observe 4 results, see also the screenshot of the table output. The frequencies are exactly the same (even when I subtract 490 MHz by using xval() ).

Which of the values do I have to use to determine the correct IP3?

Is there an option to merge these results?

Hello everyone,

For my cross-coupled oscillator design, I have a problem with stability analysis. Based on my achieved results which are attached, where is my design problem?

Best,

https://ibb.co/bgKFP4N

https://ibb.co/3FGRLmV

https://ibb.co/pwSZDSF

This blog introduces the new Voltus-XFi Custom Power Integrity Solution, a transistor-level EM-IR tool that enables designers to complete comprehensive analysis and debugging easily and quickly.(read more)

hello

is there a way to update one dynamic shape instead of updating all dynamic shapes?

i have over 6000 dynamic shapes on my design and it takes over 10 mins to update them all.

i just would like to update only one dynamic shape sometimes to find out if placing vias and lines in a shape has enough space or not.

regards

masa

The default behaviour of Place replicate update is to select every new net item connected to the replicate module. This leads to an abundant number of clines, vias and shapes being selected, most of which I don't want to add to the replicate group. It is very tedious to unselect all these items and more often than not, I miss one or two items and then end up with a via or cline in a completely different place on the board or outside of the board.

Is there a way to change this rather annoying behaviour? I haven't found any way to disable it or to batch deselect everything the tool has decided to add to the replicate group.

The question has been asked before, but it didn't get any answers and the thread is now locked.

/F

I am using OrCAD PCB Designer Standard version 17.4-2019. I want to force update the Package_Height_Max property on the place bound top shape. The footprint library that we've created has that property set in the dra file, but I'd like to override that from capture so I can be certain that the height is correct.

This is coming from a place where we have created a very large footprint library over that past ++ years. Everyone who creates a new footprint is supposed to make sure that we add Package_Height_Max to the footprint, but of course footprints get reused for various parts, not all of which will have the same package height. What I want to do is export a list of package heights from our part database and then import the package heights into Capture and override the package height in the footprint.

I have found a post here  Using Height Property from Orcad Capture which says its not possible, but it also says its from 15 years ago, so maybe things have changed?