1 Dominican Peso = 0.0326 Netherlands Antillean Guilder

Last week the weather disrupted the Indians as they opened the Outdoor Season at Pittsburg State University.  Thunderstorms and lightning prevented numerous races and events from running on schedule.  For many, the meet yesterday was their opportunity to finally compete.

Haskell will play host to the 2014 Midlands Collegiate Athletic Conference Outdoor Track and Field Championships on April 25th and 26th. 

1 Papua New Guinean Kina = 5.3495 South African Rand

1 Papua New Guinean Kina = 1107.8423 Ugandan Shilling

1 Papua New Guinean Kina = 1.9699 Trinidad and Tobago Dollar

1 Papua New Guinean Kina = 0.4749 New Zealand Dollar

1 Papua New Guinean Kina = 0.243 Cayman Islands Dollar

1 Papua New Guinean Kina = 42.6308 Icelandic Krona

1 Papua New Guinean Kina = 0.5233 Netherlands Antillean Guilder

1 Brunei Dollar = 12.9848 South African Rand

1 Brunei Dollar = 2689.0452 Ugandan Shilling

1 Brunei Dollar = 4.7815 Trinidad and Tobago Dollar

1 Brunei Dollar = 1.1528 New Zealand Dollar

1 Brunei Dollar = 0.5898 Cayman Islands Dollar

1 Brunei Dollar = 103.4771 Icelandic Krona

1 Brunei Dollar = 1.2703 Netherlands Antillean Guilder

PCI-SIG DevCon 2019 APAC tour has come to Tokyo and Taipei this year. The focus is predominantly around the latest updates for PCIe Gen 5 which its version 1.0 specification was just released this year in May.  A series of presentations provided by PCI-SIG on the day 1 with comprehensive information covering all aspects of Gen 5 specification, including protocol, logical, electrical, compliance updates. On the day 2 (only in Taipei), several member companies shared their view on Testing, PCB analysis and Signal integrity. The exhibit is also another spotlight of this event where the member companies showcased their latest PCIe solutions.

Presentation Track (Taipei), Exhibit (Tokyo), Exhibit (Taipei) 

Cadence, as the market leading PCIe IP vendor, participated APAC tour this year with bringing in its latest PCIe IP solution offering (Gen 5/4) to the region as well as showcasing two live demo setups in the exhibit floor. One setup is the PCIe software development kit (SDK) while the other is the Interop/compliance/debug platform. Both come with the Cadence PCIe Gen 4 hardware setup and its corresponding software kit.

The SDK can be used for Device Driver Development, Firmware Development, and for pre-silicon emulation as well. It supports Xtensa and ARM processor with Linux OS and it also equip with Ethernet interface which can be used for remote debugging. It also supports PCIe stress tests for Speed change, link enable/disable, entry/exist for lower power states, …etc. 

Cadence PCIe 4.0 Software Development Kit

The “System Interop/Compliance/Debug platform” was set up to test with multiple endpoint and System platforms. This system come with integrated Cadence software for basic system debug without the need for analyzer to perform the analysis, such as LTSSM History, TS1/TS2 transmitted/received with time stamp, Link training phases, Capturing Packet errors details, Capturing PHY TX/RX internal state machine details, ...etc.

Cadence PCIe System Interop/Compliance/Debug Platform

The year 2019 is certainly a "fruitful year" for the PCIe as more Gen 4 products are now available in the market, Gen 5 v1.0 specification got officially ratified, and PCI-SIG's revealing of Gen 6 specification development. We were glad to be part of this APAC tour with the chance to further introduce Cadence’s complete and comprehensive PCIe IP solution.

See you all next year in APAC again!

More Information

For more information on Cadence's PCIe IP offerings, see our PCI Express page.

For more information on PCIe in general, and on the various PCI standards, see the PCI-SIG website.

Related Posts

• Blog: Did You “Stress Test” Yet? Essential Step to Ensure a Quality PCIe 4.0 Product
• Blog: PCIe Gen4: It’s Official, We’re Compliant
• Blog: PCIe 3.0 Still Shines While PCIe Keeps Evolving
• Blog: The PCIe 4.0 Era Continues at PCI-SIG Developers Conference 2016

Pablo Bartholomew’s beautiful photo-show “Outside In” opened in Manhattan a few evenings ago. The exhibition is being held at Bodhi Art in Chelsea. Black-and-white photographs from the seventies and the eighties—reflecting Bartholomew’s engagement with people and places in Delhi, Bombay, and Calcutta.

These are not the pictures that made Bartholomew famous. The undying image of the father brushing the dust from the face of the child he is burying—that was the iconic photograph from the Bhopal tragedy in 1984. It also won for Bartholomew, still in his twenties, the World Press Photo’s Picture of the Year Award.

The images in “Outside In” do not commemorate grim tragedies or celebrate well-publicised public events. Instead, they are documents that offer intimate recall of a period and a milieu. Please click here to look at these photographs.

People who share a context with the photographer will have their own private reading of the scenes. For me, they evoke days when happiness seemed only one chai and a Wills Navy Cut away. There is charm and candor in these scenes. And because the young believe they will live forever, there is nothing defensive or stuck-up or overly self-conscious about their faces and postures.

Even the language of the captions is true to this spirit: “Self-portrait after a trippy night…”; “Nona writing and Alok zonked out…”; “Hanging out with the Maharani Bagh gang….” The exhibition catalogue has a fine essay by Aveek Sen that has also been published in the latest issue of Biblio.

Rave Out © 2007 IndiaUncut.com. All rights reserved.
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Who used to be known as Dileep Kumar, and is now married to Saira Banu?

Workoutable © 2007 IndiaUncut.com. All rights reserved.
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X is a song written by Y and famously covered by Z. Time Magazine’s Josh Tyrangiel described it thus:

Y murmured the original like a dirge, but except for a single overwrought breath before the music kicks in, Z treated the 7-min. song like a tiny capsule of humanity, using his voice to careen between glory and sadness, beauty and pain, mostly just by repeating the word X. It’s not only Z’s best song — it’s one of the great songs, and because it covers so much emotional ground and is not (yet) a painfully obvious choice, it has become the go-to track whenever a TV show wants to create instant mood. ‘X can be joyous or bittersweet, depending on what part of it you use,’ says Sony ATV’s Kathy Coleman. ‘It’s one of those rare songs that the more it gets used, the more people want to use it.’

Name X, Y and Z.

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This is the 22nd installment of The Rationalist, my column for the Times of India.

Trade wars are on the rise, and it’s enough to get any nationalist all het up and excited. Earlier this week, Narendra Modi’s government announced that it would start imposing tariffs on 28 US products starting today. This is a response to similar treatment towards us from the US.

There is one thing I would invite you to consider: Trump and Modi are not engaged in a war with each other. Instead, they are waging war on their own people.

Let’s unpack that a bit. Part of the reason Trump came to power is that he provided simple and wrong answers for people’s problems. He responded to the growing jobs crisis in middle America with two explanations: one, foreigners are coming and taking your jobs; two, your jobs are being shipped overseas.

Both explanations are wrong but intuitive, and they worked for Trump. (He is stupid enough that he probably did not create these narratives for votes but actually believes them.) The first of those leads to the demonising of immigrants. The second leads to a demonising of trade. Trump has acted on his rhetoric after becoming president, and a modern US version of our old ‘Indira is India’ slogan might well be, “Trump is Tariff. Tariff is Trump.”

Contrary to the fulminations of the economically illiterate, all tariffs are bad, without exception. Let me illustrate this with an example. Say there is a fictional product called Brump. A local Brump costs Rs 100. Foreign manufacturers appear and offer better Brumps at a cheaper price, say Rs 90. Consumers shift to foreign Brumps.

Manufacturers of local Brumps get angry, and form an interest group. They lobby the government – or bribe it with campaign contributions – to impose a tariff on import of Brumps. The government puts a 20-rupee tariff. The foreign Brumps now cost Rs 110, and people start buying local Brumps again. This is a good thing, right? Local businesses have been helped, and local jobs have been saved.

But this is only the seen effect. The unseen effect of this tariff is that millions of Brump buyers would have saved Rs 10-per-Brump if there were no tariffs. This money would have gone out into the economy, been part of new demand, generated more jobs. Everyone would have been better off, and the overall standard of living would have been higher.

That brings to me to an essential truth about tariffs. Every tariff is a tax on your own people. And every intervention in markets amounts to a distribution of wealth from the people at large to specific interest groups. (In other words, from the poor to the rich.) The costs of this are dispersed and invisible – what is Rs 10 to any of us? – and the benefits are large and worth fighting for: Local manufacturers of Brumps can make crores extra. Much modern politics amounts to manufacturers of Brumps buying politicians to redistribute money from us to them.

There are second-order effects of protectionism as well. When the US imposes tariffs on other countries, those countries may respond by imposing tariffs back. Raw materials for many goods made locally are imported, and as these become expensive, so do those goods. That quintessential American product, the iPhone, uses parts from 43 countries. As local products rise in price because of expensive foreign parts, prices rise, demand goes down, jobs are lost, and everyone is worse off.

Trump keeps talking about how he wants to ‘win’ at trade, but trade is not a zero-sum game. The most misunderstood term in our times is probably ‘trade-deficit’. A country has a trade deficit when it imports more than what it exports, and Trump thinks of that as a bad thing. It is not. I run a trade deficit with my domestic help and my local grocery store. I buy more from them than they do from me. That is fine, because we all benefit. It is a win-win game.

Similarly, trade between countries is really trade between the people of both countries – and people trade with each other because they are both better off. To interfere in that process is to reduce the value created in their lives. It is immoral. To modify a slogan often identified with libertarians like me, ‘Tariffs are Theft.’

These trade wars, thus, carry a touch of the absurd. Any leader who imposes tariffs is imposing a tax on his own people. Just see the chain of events: Trump taxes the American people. In retaliation, Modi taxes the Indian people. Trump raises taxes. Modi raises taxes. Nationalists in both countries cheer. Interests groups in both countries laugh their way to the bank.

What kind of idiocy is this? How long will this lose-lose game continue?

© 2007 IndiaUncut.com. All rights reserved.
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This is the 23rd installment of The Rationalist, my column for the Times of India.

I had a strange dream last night. I dreamt that the government had passed a law that made using laptops illegal. I would have to write this column by hand. I would also have to leave my home in Mumbai to deliver it in person to my editor in Delhi. I woke up trembling and angry – and realised how Indian farmers feel every single day of their lives.

My column today is a tale of two satyagrahas. Both involve farmers, technology and the freedom of choice. One of them began this month – but first, let us go back to the turn of the millennium.

As the 1990s came to an end, cotton farmers across India were in distress. Pests known as bollworms were ravaging crops across the country. Farmers had to use increasing amounts of pesticide to keep them at bay. The costs of the pesticide and the amount of labour involved made it unviable – and often, the crops would fail anyway.

Then, technology came to the rescue. The farmers heard of Bt Cotton, a genetically modified type of cotton that kept these pests away, and was being used around the world. But they were illegal in India, even though no bad effects had ever been recorded. Well, who cares about ‘illegal’ when it is a matter of life and death?

Farmers in Gujarat got hold of Bt Cotton seeds from the black market and planted them. You’ll never guess what happened next. As 2002 began, all cotton crops in Gujarat failed – except the 10,000 hectares that had Bt Cotton. The government did not care about the failed crops. They cared about the ‘illegal’ ones. They ordered all the Bt Cotton crops to be destroyed.

It was time for a satyagraha – and not just in Gujarat. The late Sharad Joshi, leader of the Shetkari Sanghatana in Maharashtra, took around 10,000 farmers to Gujarat to stand with their fellows there. They sat in the fields of Bt Cotton and basically said, ‘Over our dead bodies.’ ¬Joshi’s point was simple: all other citizens of India have access to the latest technology from all over. They are all empowered with choice. Why should farmers be held back?

The satyagraha was successful. The ban on Bt Cotton was lifted.

There are three things I would like to point out here. One, the lifting of the ban transformed cotton farming in India. Over 90% of Indian farmers now use Bt Cotton. India has become the world’s largest producer of cotton, moving ahead of China. According to agriculture expert Ashok Gulati, India has gained US$ 67 billion in the years since from higher exports and import savings because of Bt Cotton. Most importantly, cotton farmers’ incomes have doubled.

Two, GMO crops have become standard across the world. Around 190 million hectares of GMO crops have been planted worldwide, and GMO foods are accepted in 67 countries. The humanitarian benefits have been massive: Golden Rice, a variety of rice packed with minerals and vitamins, has prevented blindness in countless new-born kids since it was introduced in the Philippines.

Three, despite the fear-mongering of some NGOs, whose existence depends on alarmism, the science behind GMO is settled. No harmful side effects have been noted in all these years, and millions of lives impacted positively. A couple of years ago, over 100 Nobel Laureates signed a petition asserting that GMO foods were safe, and blasting anti-science NGOs that stood in the way of progress. There is scientific consensus on this.

The science may be settled, but the politics is not. The government still bans some types of GMO seeds, such as Bt Brinjal, which was developed by an Indian company called Mahyco, and used successfully in Bangladesh. More crucially, a variety called HT Bt Cotton, which fights weeds, is also banned. Weeding takes up to 15% of a farmer’s time, and often makes farming unviable. Farmers across the world use this variant – 60% of global cotton crops are HT Bt. Indian farmers are so desperate for it that they choose to break the law and buy expensive seeds from the black market – but the government is cracking down. A farmer in Haryana had his crop destroyed by the government in May.

On June 10 this year, a farmer named Lalit Bahale in the Akola District of Maharashtra kicked off a satyagraha by planting banned seeds of HT Bt Cotton and Bt Brinjal. He was soon joined by thousands of farmers. Far from our urban eyes, a heroic fight has begun. Our farmers, already victimised and oppressed by a predatory government in countless ways, are fighting for their right to take charge of their lives.

As this brave struggle unfolds, I am left with a troubling question: All those satyagrahas of the past by our great freedom fighters, what were they for, if all they got us was independence and not freedom?

© 2007 IndiaUncut.com. All rights reserved.
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This is the 24th installment of The Rationalist, my column for the Times of India.

Back in the last decade, I was a cricket journalist for a few years. Then, around 12 years ago, I quit. I was jaded as hell. Every game seemed like déjà vu, nothing new, just another round on the treadmill. Although I would remember her fondly, I thought me and cricket were done.

And then I fell in love again. Cricket has changed in the last few years in glorious ways. There have been new ways of thinking about the game. There have been new ways of playing the game. Every season, new kinds of drama form, new nuances spring up into sight. This is true even of what had once seemed the dullest form of the game, one-day cricket. We are entering into a brave new world, and the team leading us there is England. No matter what happens in the World Cup final today – a single game involves a huge amount of luck – this England side are extraordinary. They are the bridge between eras, leading us into a Golden Age of Cricket.

I know that sounds hyperbolic, so let me stun you further by saying that I give the IPL credit for this. And now, having woken up you up with such a jolt on this lovely Sunday morning, let me explain.

Twenty20 cricket changed the game in two fundamental ways. Both ended up changing one-day cricket. The first was strategy.

When the first T20 games took place, teams applied an ODI template to innings-building: pinch-hit, build, slog. But this was not an optimal approach. In ODIs, teams have 11 players over 50 overs. In T20s, they have 11 players over 20 overs. The equation between resources and constraints is different. This means that the cost of a wicket goes down, and the cost of a dot ball goes up. Critically, it means that the value of aggression rises. A team need not follow the ODI template. In some instances, attacking for all 20 overs – or as I call it, ‘frontloading’ – may be optimal.

West Indies won the T20 World Cup in 2016 by doing just this, and England played similarly. And some sides began to realise was that they had been underestimating the value of aggression in one-day cricket as well.

The second fundamental way in which T20 cricket changed cricket was in terms of skills. The IPL and other leagues brought big money into the game. This changed incentives for budding cricketers. Relatively few people break into Test or ODI cricket, and play for their countries. A much wider pool can aspire to play T20 cricket – which also provides much more money. So it makes sense to spend the hundreds of hours you are in the nets honing T20 skills rather than Test match skills. Go to any nets practice, and you will find many more kids practising innovative aggressive strokes than playing the forward defensive.

As a result, batsmen today have a wider array of attacking strokes than earlier generations. Because every run counts more in T20 cricket, the standard of fielding has also shot up. And bowlers have also reacted to this by expanding their arsenal of tricks. Everyone has had to lift their game.

In one-day cricket, thus, two things have happened. One, there is better strategic understanding about the value of aggression. Two, batsmen are better equipped to act on the aggressive imperative. The game has continued to evolve.

Bowlers have reacted to this with greater aggression on their part, and this ongoing dialogue has been fascinating. The cricket writer Gideon Haigh once told me on my podcast that the 2015 World Cup featured a battle between T20 batting and Test match bowling.

This England team is the high watermark so far. Their aggression does not come from slogging. They bat with a combination of intent and skills that allows them to coast at 6-an-over, without needing to take too many risks. In normal conditions, thus, they can coast to 300 – any hitting they do beyond that is the bonus that takes them to 350 or 400. It’s a whole new level, illustrated by the fact that at one point a few days ago, they had seven consecutive scores of 300 to their name. Look at their scores over the last few years, in fact, and it is clear that this is the greatest batting side in the history of one-day cricket – by a margin.

There have been stumbles in this World Cup, but in the bigger picture, those are outliers. If England have a bad day in the final and New Zealand play their A-game, England might even lose today. But if Captain Morgan’s men play their A-game, they will coast to victory. New Zealand does not have those gears. No other team in the world does – for now.

But one day, they will all have to learn to play like this.

© 2007 IndiaUncut.com. All rights reserved.
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One reason for attending the upcoming Design Automation Conference (DAC 2015) is to learn about challenges other engineers have faced, and hear about their solutions. And the best place to do that is the Cadence Theater, located at the Cadence booth (#3515). The Theater will host continuous half-hour customer and partner presentations from 10:00 am Monday, June 8, to 5:30 pm Wednesday June 4.

As of this writing, 43 presentations are scheduled. This includes 17 customer presentations, 23 partner presentations, and 3 Cadence presentations, The presentations are open to all DAC attendees and no reservations are required.

Cadence customers who will be speaking include engineers from AMD, ams, Allegro Micro, Broadcom, IBM, Netspeed, NVidia, Renesas, Socionet, and STMicroelectronics. Partner presentations will be provided by ARM, Cliosoft, Dini Group, GLOBALFOUNDRIES, Methodics, Methods2Business, National Instruments, Samsung, TowerJazz, TSMC, and X-Fab.

These informal presentations are given in an interactive setting with an opportunity for questions and answers. Audio recordings with slides will be available at the Cadence web site after DAC. To access recordings of the 2014 DAC Theater presentations, click here.

This Cadence DAC Theater presentation drew a large audience at DAC 2015

Here’s a listing of the currently scheduled Cadence DAC Theater presentations. The latest schedule is available at the Cadence DAC 2015 site.

Monday, June 8

Tuesday, June 9

Wednesday, June 10

In a Wednesday session (June 10, 10:00 am) at the theater, the Cadence Academic Network will sponsor three talks on academic/industry collaboration models. Speakers are Dr. Zhou Li, architect, Cadence; Prof. Xin Li, Carnegie-Mellon University; and Prof. Laleh Behjat, University of Calgary.

As shown above, there will be a giveaways for a set of Bose noise-cancelling headphones, an iPad Mini, and a GoPro Hero3 video camera.

See the Cadence Theater schedule for further details. And be sure to view our Multimedia Site for live blogging and photos and videos from DAC. For a complete overview of Cadence activities at DAC, see our DAC microsite.

Richard Goering

Related Blog Posts

DAC 2015: See the Latest in Semiconductor IP at “IPTalks!”

Cadence DAC 2015 and Denali Party Update

DAC 2015: Tackling Tough Design Problems Head On

First, the good news. The EDA industry will grow from $6.2 billion in 2015 to $9.0 billion in 2019, according to Gary Smith, chief analyst at Gary Smith EDA. Year-to-year growth rates will range from +4% to +11.2%.

But in his annual presentation on the eve of the Design Automation Conference (DAC 2015), Smith noted that Wall Street is unimpressed. “The people I talk to want long-term steady growth, no sharp up-turns, no sharp downturns,” Smith said. “To the rest of Wall Street, we’re boring.”

Smith spent the rest of his talk noting how EDA can be a lot less boring and, potentially, a whole lot bigger. For starters, what if we add semiconductor IP to EDA revenues? Now we’re looking at $12.2 billion in revenue by 2019, Smith said. (He acknowledged, however, that the IP market itself is going to take a “dip” due to the move towards platform-based IP and away from conventional piecemeal IP).

This still is not enough to get Wall Street’s attention. Another possibility is to bring embedded software development into the EDA industry. This is not a huge market – about $2.6 billion today – but it is an “easy growth market for us,” according to Smith.

Chasing the Big Bucks

But the “big bucks” are in mechanical CAD (MCAD), Smith said. In the past the MCAD market has always been bigger than EDA, but now EDA is catching up. The MCAD market is about $6.6 billion now. Synopsys and Cadence are larger than PTC and Siemens, two of the main players in MCAD.

There may be some good acquisition possibilities coming up for EDA vendors, Smith said – and if we don’t buy MCAD companies, they might buy EDA companies. Consider, for example, that Ansoft bought Apache and Dassault bought Synchronicity. (Note: Siemens PLM Software is a first-time exhibitor at DAC 2015).

What about other domains? Smith said that EDA companies could conceivably move into optical design, applications development software, biomedical design, and chemical design. The last if these is probably the most tenuous; Smith noted that EDA vendors have yet to look into chemical design.

Applications development software is the biggest market on the above list, but that means competing with Microsoft, IBM, and Oracle. “You’re in with the big boys – is that a good idea?” Smith asked.

Perhaps there’s an opening for a “big play” for an MCAD provider. Smith noted that mechanical vendors are focusing on product data management (PDM). This “is really the IT of design,” Smith said. “They have a lot of hope that the IoT [Internet of things] market is going to give them an opportunity to capture the software that goes from the ground to the cloud. Maybe we can let them have PDM and see if we can take the tool market away from them, or acquire it away from them.”

In conclusion, Smith asked, should the EDA industry accelerate its growth? “The mechanical vendors have already shown interest in acquiring EDA vendors,” he said. “We may not have a choice.”

Richard Goering

NOTE: Catch our live blog from DAC 2015, beginning Monday morning, June 8! Click here

As a leading venture capitalist in the electronics technology, as well as CEO of Cadence, Lip-Bu Tan has unique insights into ongoing changes that will impact EDA providers and users. Tan shared some of those insights in a “fireside chat” with Ed Sperling, editor in chief of Semiconductor Engineering, at the Design Automation Conference (DAC 2015) on June 9.

Topics of this discussion included industry consolidation, the need for more talent and more startups, Internet of Things (IoT) opportunities and challenges, the shift from ICs to full product development, and the challenges of advanced nodes. Following are some excerpts from this conversation, held at the DAC Pavilion theater on the exhibit floor.

Ed Sperling (left) and Lip-Bu Tan (right) discuss trends in semiconductors and EDA

Q: As you look out over the semiconductor and EDA industries these days, what worries you most?

Tan: At the top of my list is all the consolidation that is going on. Secondly, chip design complexity is increasing substantially. Time-to-market pressure is growing and advanced nodes have challenges.

The other thing I worry about is that we need to have more startups. There’s a lot of innovation that needs to happen. And this industry needs more top talent. At Cadence, we have a program to recruit over 10% of new hires every year from college graduates. We need new blood and new ideas.

Q: EDA vendors were acquiring companies for many years, but now the startups are pretty much gone. Where does the next wave of innovation come from?

Tan: I’ve been an EDA CEO for the last seven years and I really enjoy it because so much innovation is needed. System providers have very big challenges and very different needs. You have to find the opportunities and go out and provide the solutions.

The opportunities are not just in basic tools. Massive parallelism is critical, and the power challenge is huge. Time to market is critical, and for the IoT companies, cost is going to be critical. If you want to take on some good engineering challenges, this is the most exciting time.

Q: You live two lives—you’re a CEO but you’re also an investor. Where are the investments going these days and where are we likely to see new startups?

Tan: Clearly everybody is chasing the IoT. There is a lot of opportunity in the cloud, in the data center. Also, I’m a big believer in video, so I back companies that are video related. A big area is automotive. ADAS [Advanced Driver Assistance Systems] is a tremendous opportunity.

These companies can help us understand how the industry is transforming, and then we can provide solutions, either in terms of IP, tools, or the PCB. Then we need to connect from the system level down to semiconductors. I think it’s a different way to design.

Q: What happens as we start moving from companies looking to design a semiconductor to system companies who are doing things from the perspective that we have this purpose for our software?

Tan: We are extending from EDA to what we call system design enablement, and we are becoming more application driven. The application at the system level will drive the silicon design. We need to help companies look at the whole system including the power envelope and signal integrity. You don’t want to be in a position where you design a chip all the way to fabrication and then find the power is too high.

We help the customers with hardware/software co-design and co-verification. We have a design suite and a verification suite that can provide customers with high-level abstractions, as well as verify IP blocks at the system level. Then we can break things down to the component level with system constraints in mind, and drive power-aware, system-aware design.

We are starting to move into vertical markets. For example, medical is a tremendous opportunity.

Q: How does this approach change what you provide to customers?

Tan: Every year I spend time meeting with customers. I think it is very important to understand what they are trying to design, and it is also important to know the customer’s customer requirements. We might say, “Wait a minute, for this design you may want to think about power or the library you’re using.” We help them understand what foundry they should use and what process they should use. They don’t view me as a vendor—they view me as a partner.

We also work very closely with our IP and foundry partners. We work as one team—the ultimate goal is customer success.

Q: Is everybody going to say, FinFETs are beautiful, we’re going to go down to 10nm or 7nm—or is it a smaller number of companies who will continue down that path?

Tan: Some of the analog/mixed-signal companies don’t need to go that far. We love those customers—we have close to 50% of that business. But we also have customers in the graphics or processor area who are really pushing the envelope, and need to be in 16nm, 14nm, or 10nm. We work very closely with those guys to make sure they can go into FinFETs.

We always want to work with the customer to make sure they have a first-time silicon success. If you have to do a re-spin, you miss the opportunity and it’s very costly.

Q: There’s a new market that is starting to explode—IoT. How real is that world to you? Everyone talks about large numbers, but is it showing up in terms of tools?

Tan: Everybody is talking about huge profits, but a lot of the time I think it is just connecting old devices that you have. Billions of units, absolutely yes, but if you look close enough the silicon percentage of that revenue is very tiny. A lot of the profit is on the service side. So you really need to look at the service killer app you are trying to provide.

What’s most important to us in the IoT market is the IP business. That’s why we bought Tensilica—it’s programmable, so you can find the killer app more quickly. The other challenges are time to market, low power, and low cost.

Q: Where is system design enablement going? Does it expand outside the traditional market for EDA?

Tan: It’s not just about tools. IP is now 11% of our revenue. At the PCB level, we acquired a company called Sigrity, and through that we are able to drive system analysis for power, signal integrity, and thermal. And then we look at some of the verticals and provide modeling all the way from the system level to the component level. We make sure that we provide a solution to the end customer, rather than something piecemeal.

Q: What do you think DAC will look like in five years?

Tan: It’s getting smaller. We need to see more startups and innovative IP solutions. I saw a few here this year, and that’s good. We need to encourage small startups.

Q: Where do we get the people to pull this off? I don’t see too many people coming into EDA.

Tan: I talk to a lot of university students, and I tell them that this small industry is a gold mine. A lot of innovation is needed. We need them to come in [to EDA] rather than join Google or Facebook. Those are great companies, but there is a lot of fundamental physical innovation we need.

Richard Goering

Related Blog Posts

- Gary Smith at DAC 2015: How EDA Can Expand Into New Directions

- DAC 2015: Google Smart Contact Lens Project Stretches Limits of IC Design

- Q&A with Nimish Modi: Going Beyond Traditional EDA

Design and verification standards are critical if we want to get a new generation of Internet of Things (IoT) devices into the market, according to panelists at an Accellera Systems Initiative breakfast at the Design Automation Conference (DAC 2015) June 9. However, IoT devices for different vertical markets pose very different challenges and requirements, making the standards picture extremely complicated.

The panel was titled “Design and Verification Standards in the Era of IoT.” It was moderated by industry editor John Blyler, CEO of JB Systems Media and Technology. Panelists were as follows, shown left to right in the photo below:

• Lu Dai, director of engineering, Qualcomm
• Wael William Diab, senior director for strategy marketing, industry development and standardization, Huawei
• Chris Rowen, CTO, IP Group, Cadence Design Systems, Inc.

In opening remarks, Blyler recalled a conversation from the recent IEEE International Microwave Symposium in which a panelist pointed to the networking and application layers as the key problem areas for RF and wireless standardization. Similarly, in the IoT space, we need to look “higher up” at the systems level and consider both software and hardware development, Blyler said.

Rowen helped set some context for the discussion by noting three important points about IoT:

• IoT is not a product segment. Vertical product segments such as automotive, medical devices, and home automation all have very different characteristics.
• IoT “devices” are components within a hierarchy of systems that includes sensors, applications, user interface, gateway application (such as cell phone), and finally the cloud, where all data is aggregated.
• A bifurcation is taking place in design. We are going from extreme scale SoCs to “extreme fit” SoCs that are specialized, low energy, and very low cost.

Here are some of the questions and answers that were addressed during the panel discussion.

Q: The claim was recently made that given the level of interaction between sensors and gateways, 50X more verification nodes would have to be checked for IoT. What standards need to be enhanced or changed to accomplish that?

Rowen: That’s a huge number of design dimensions, and the way you attack a problem of that scale is by modularization. You define areas that are protected and encapsulated by standards, and you prove that individual elements will be compliant with that interface. We will see that many interesting problems will be in the software layers.

Q: Why is standardization so important for IoT?

Dai: A company that is trying to make a lot of chips has to deal with a variety of standards. If you have to deal with hundreds of standards, it’s a big bottleneck for bringing your products to market. If you have good standardization within the development process of the IC, that helps time to market.

When I first joined Qualcomm a few years ago, there was no internal verification methodology. When we had a new hire, it took months to ramp up on our internal methodology to become effective. Then came UVM [Universal Verification Methodology], and as UVM became standard, we reduced our ramp-up time tremendously. We’ve seen good engineers ramp up within days.

Diab: When we start to look at standards, we have to do a better job of understanding how they’re all going to play with each other. I don’t think one set of standards can solve the IoT problem. Some standards can grow vertically in markets like industrial, and other standards are getting more horizontal. Security is very important and is probably one thing that goes horizontally.

Requirements for verticals may be different, but processing capability, latency, bandwidth, and messaging capability are common [horizontal] concerns. I think a lot of standards organizations this year will work on horizontal slices [of IoT].

Q: IoT interoperability is important. Any suggestions for getting that done and moving forward?

Rowen: The interoperability problem is that many of these [IoT] devices are wireless. Wireless is interesting because it is really hard – it’s not like a USB plug. Wireless lacks the infrastructure that exists today around wired standards. If we do things in a heavily wireless way, there will be major barriers to overcome.

Dai: There are different standards for 4G LTE technology for different [geographical] markets. We have to make a chip that can work for 20 or 30 wireless technologies, and the cost for that is tremendous. The U.S., Europe, and China all have different tweaks. A good standard that works across the globe would reduce the cost a lot.

Q: If we’re talking about the need to define requirements, a good example to look at is power. Certainly you have UPF [Unified Power Format] for the chip, board, and module.

Rowen: There is certainly a big role for standards about power management. But there is also a domain in which we’re woefully under-equipped, and that is the ability to accurately model the different power usage scenarios at the applications level. Too often power devolves into something that runs over thousands of cycles to confirm that you can switch between power management levels successfully. That’s important, but it tells you very little about how much power your system is going to dissipate.

Dai: There are products that claim to be UPF compliant, but my biggest problem with my most recent chip was still with UPF. These tools are not necessarily 100% UPF compliant.

One other concern I have is that I cannot get one simulator to pass my Verilog code and then go to another that will pass. Even though we have a lot of tools, there is no certification process for a language standard.

Q: When we create a standard, does there need to be a companion compliance test?

Rowen: I think compliance is important. Compliance is being able to prove that you followed what you said you would follow. It also plays into functional safety requirements, where you need to prove you adhered to the flow.

Dai: When we [Qualcomm] sell our 4G chips, we have to go through a lot of certifications. It’s often a differentiating factor.

Q: For IoT you need power management and verification that includes analog. Comments?

Rowen: Small, cheap sensor nodes tend to be very analog-rich, lower scale in terms of digital content, and have lots of software. Part of understanding what’s different about standardization is built on understanding what’s different about the design process, and what does it mean to have a software-rich and analog-rich world.

Dai: Analog is important in this era of IoT. Analog needs to come into the standards community.

Richard Goering

Cadence Blog Posts About DAC 2015

Gary Smith at DAC 2015: How EDA Can Expand Into New Directions

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DAC 2015: Lip-Bu Tan, Cadence CEO, Sees Profound Changes in Semiconductors and EDA

DAC 2015: “Level of Compute in Vision Processing Extraordinary” – Chris Rowen

DAC 2015: Can We Build a Virtual Silicon Valley?

DAC 2015: Cadence Vision-Design Presentation Wins Best Paper Honors

Let’s face it – the EDA industry needs new people and new ideas. One of the best places to find both is academia, and a presentation at the Cadence Theater at the recent Design Automation Conference (DAC 2015) described collaboration models that are working today.

The presentation was titled “Industry/Academia Engagement Models – From PhD Contests to R&D Collaborations.” It included these speakers, shown from left to right in the photo below:

• Prof. Xin Li, Electrical and Computer Engineering, Carnegie-Mellon University (CMU)
• Chuck Alpert, Senior Software Architect, Cadence
• Prof. Laleh Behjat, Department of Electrical and Computer Engineering, University of Calgary

Alpert, who was filling in for Zhuo Li, Software Architect at Cadence, was the vice chair of DAC 2015 and will be the general chair of DAC 2016 in Austin, Texas. “My team at Cadence really likes to collaborate with universities,” he said. “We’re a big proponent of education because we really need the best and brightest students in our industry.”

Contests Boost EDA Research

One way that Cadence collaborates with academia is participation in contests. “It’s a great way to formulate problems to academia,” Alpert said. “We can have the universities work on these problems and get some strategic direction.”

For example, Cadence has been involved with the annual CAD contest at the International Conference on Computer-Aided Design (ICCAD) since the contest was launched in 2012. This is the largest worldwide EDA R&D contest, and it is sponsored by the IEEE Council on EDA (CEDA) and the Taiwan Ministry of Education. Its goals are to boost EDA research in advanced real-world problems and to foster industry-academia collaboration.

Contestants can participate in one of more problems in the three areas of system design, logic synthesis and verification, and physical design. The 2015 contest has attracted 112 teams from 12 regions. Cadence contributes one problem per year in the logic synthesis area. Zhuo Li was the 2012 co-chair and the 2013 chair. The awards will be given at ICCAD in November 2015.

Another step that Cadence has taken, Alpert said, is to “hire lots of interns.” His own team has four interns at the moment. One advantage to interning at Cadence, he said, is that students get to see real-world designs and understand how the tools work. “It helps you drive your research in a more practical and useful direction,” he said.

The Cadence Academic Network co-sponsors the ACM SIGDA PhD Forum at DAC, and Xin Li and Zhuo Li are on the organizing committee. This event is a poster session for PhD students to present and discuss their dissertation research with people in the EDA community. This year’s forum was “packed,” Alpert said, and it’s clear that the event needs a bigger room.

Finally, Alpert noted, Cadence researchers write and publish technical papers at DAC and other conferences, and Cadence people serve on the DAC technical program committee. “We try to be involved with the academic community on a regular basis,” Alpert said. “We want the best and the brightest people to go into EDA because there is still so much innovation that’s needed. It’s a really cool place to be.”

Research Collaboration Exposes Failure Rates

Xin Li presented an example of a successful research collaboration between CMU and Cadence. The challenge was to find a better way to estimate potential failure rates in memory. As noted in a previous blog post, PhD student Shupeng Sun met this challenge with a new statistical methodology that won a Best Poster award at the ACM SIGDA PhD Forum at DAC 2014.

The new methodology is called Scaled-Sigma Sampling (SSS). It calculates the failure rate and accounts for variability in the manufacturing process while only requiring a few hundred, or a few thousand, sample circuit blocks. Previously, millions of samples were required for an accurate validation of a new design, and each sample could take minutes or hours to simulate. It could take a few weeks or months to run one validation.

The SSS methodology requires greatly reduced simulation times. It makes it possible, Li noted, to run simulations overnight and see the results in the morning.

Li shared his secret for success in collaborations. “I want to emphasize that before the collaboration, you have to understand the goal. If you don’t have a clear goal, don’t collaborate. Once you define the goal, stick to it and make it happen.”

Contest Provides Learning Experience

Last year Laleh Behjat handed two of her new PhD students a challenge. “I told them there is an ISPD [International Symposium for Physical Design] contest on placement, and I expect you to participate and I expect you to win. Not knowing anything about placement, I don’t think they realized what I was asking them.”

The 2015 contest was called the Blockage-Aware Detailed Routing-Driven Placement Contest. Results were announced at the end of March at ISPD. And the University of Calgary team, despite its lack of placement experience, took second place.

Such contests provide a good learning tool, according to Behjat. Graduate students in EDA, she said, “have to be good programmers. They have to work in teams and be collaborative, be able to innovate, and solve the hardest problems I have seen in engineering and science. And they have to think outside the box.” A contest can bring out all these attributes, she said.

Further, Behjat noted, contest participants had access to benchmarks and to a placement tool. They didn’t have to write tools to find out if their results were good. Industry sponsors, meanwhile, got access to good students and new approaches for solving problems.

“You can see Cadence putting a big amount of time, effort and money to get students here and get them excited about doing contests,” she said. She advised students in the theater audience to “talk to people in the Cadence booth and see if you can have more ideas for collaboration.”

Richard Goering

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BSIM-CMG FinFET Model – How Academia and Industry Empowered the Next Transistor

In 1985, as a relatively new editor at Computer Design magazine, I was asked to go forth and cover a new business called CAE (computer-aided engineering). I knew nothing about it, but I had been writing about design for test, so there seemed to be somewhat of a connection. Little did I know that “CAE” would turn into “EDA” and that I’d write about it for the next 30 years, for Computer Design, EE Times, Cadence, and a few others.

Now that I’m about to retire, I’m looking back over those 30 years. What a ride it has been! By the numbers I covered 31 Design Automation Conferences (DACs), hundreds of new products, dozens of acquisitions and startups, dozens of lawsuits, and some blind alleys that didn’t work out (like “silicon compilation”). Chip design went from gate arrays and PLDs with a few thousand gates to processors and SoCs with billions of transistors.

In 1985 there were three big CAE vendors – Daisy Systems, Mentor Graphics, and Valid Logic. All sold bundled packages that included workstations and CAE software; in fact, Daisy and Valid designed and manufactured their own workstations. In the early 1980s a workstation with schematic capture and gate-level logic simulation might have set you back $120,000. In 1985 OrCAD, now part of Cadence, came out with a $500 schematic capture package running on IBM PCs.

Cadence and Synopsys emerged in the late 1980s, and by the 1990s the EDA industry was pretty much a software-only business (apart from specialized machines like simulation accelerators). Since the early 1990s the “big three” EDA vendors have been Cadence, Synopsys, and Mentor, giving the industry stability but allowing for competition and innovation.

Here, in my view, are some of the highlights that occurred during the past 30 years of EDA.

EDA is a Highlight

The biggest highlight in EDA is the existence of a commercial EDA industry! Marching hand in hand with the fabless semiconductor revolution, commercial EDA made it possible for hundreds of companies to design semiconductors, as opposed to a small handful that could afford large internal CAD operations and fabs. With hundreds of semiconductor companies as opposed to a half-dozen, there’s a lot more creativity, and you get the level of sophistication and intelligence that you see in your smartphone, video camera, tablet, gaming console, and car today.

CAE + CAD = EDA. This is not just a terminology issue. By the mid-1980s it became clear that front-end design (CAE) and physical design (CAD) belonged together. The big CAE vendors got involved in IC and PCB CAD, and presented increasingly integrated solutions. People got tired of writing “CAE/CAD” and “EDA” was born.

The move from gate-level design to RTL. This move happened around 1990, and in my view this is EDA’s primary technology success story during the past 30 years. Moving up in abstraction made the design and verification of much larger chips possible. Going from gate-level schematics to a hardware description language (HDL) revolutionized logic design and verification. Which would you rather do – draw all the gates that form an adder, or write a few lines of code and let a synthesis tool find an adder in your chosen technology?

Two developments made this shift in design possible. One was the emergence of commercial RTL synthesis (or “logic synthesis”) tools from Synopsys and other companies, which happened around 1990. Another was the availability of Verilog, developed by Gateway Design Automation and purchased by Cadence in 1989, as a standard RTL HDL. Although most EDA vendors at the time were pushing VHDL, designers wanted Verilog and that’s what most still use (with SystemVerilog coming on strong in the verification space).

IC functional verification underwent huge changes in the late 1990s and early 2000s, largely due to new technology developed by Verisity, which was acquired by Cadence in 2005. Before Verisity, verification engineers were writing and running directed tests in an ad-hoc manner. Verisity introduced or improved technologies such as pseudo-random test generation, coverage metrics, reusable verification IP, and semi-automated verification planning. The Verisity “e” language became a widely used hardware verification language (HVL).

The biggest way that EDA has expanded its focus has been through semiconductor IP. Today Synopsys and Cadence are leading providers in this area. Thanks to the availability of design and verification IP, many SoC designs today reuse as much as 80% of previous content. This makes it much, much faster to design the remaining portion. While IP began with fairly simple elements, today commercially available IP can include whole subsystems along with the software that runs on them. With IP, EDA vendors are providing not only design tools but design content.

Finally, the EDA industry has done an amazing job of keeping up with SoC complexity and with advanced process nodes. Thanks to intense and early collaboration between foundries, IP, and EDA providers, tools and IP have been ready for process nodes going down to 10nm.

Where Does ESL Fit?

In some ways, electronic system level (ESL) design is both a lowlight and a highlight. It’s a lowlight because people have been talking about it for 30 years and the acceptance and adoption have come very slowly. ESL is a highlight because it’s finally starting to happen, and its impact on design and verification flows could be dramatic. Still, ESL is vaguely defined and can be used to describe almost anything that happens at a higher abstraction level than RTL.

High-level synthesis (HLS) is an ESL technology that is seeing increasing use in production environments. Current HLS tools are not restricted to datapaths, and they produce RTL code that gives better quality of results than hand-written RTL. Another ESL methodology that’s catching on is virtual prototyping, which lets software developers write software pre-silicon using SystemC models. Both HLS and virtual prototyping are made possible by the standardization of SystemC and transaction-level modeling (TLM). However, it’s still not easy to use the same SystemC code for HLS and virtual prototyping.

And Now, Some Lowlights

Every new industry has some twists and turns, and EDA is no exception. For example, the EDA industry in the 1980s and 1990s sparked a lot of lawsuits. At EE Times my colleagues and I wrote a number of articles about EDA legal disputes, mostly about intellectual property, trade secrets, or patent issues. Over the past decade, fortunately, there have been far fewer EDA lawsuits than we had before the turn of the century.

Another issue that was troublesome in the 1980s and 1990s was so-called “standards wars.” These would occur as EDA vendors picked one side or the other in a standards dispute. For example, power intent formats were a point of conflict in the early 2000s, but the Common Power Format (CPF) and the Unified Power Format (UPF) are on the road to convergence today with the IEEE 1801 effort. As mentioned previously, Verilog and VHDL were competing for adoption in the early 1990s. For the most part, Verilog won, showing that the designer community makes the final decision about which standards will be used.

How on earth did there get to be something like 30 DFM (design for manufacturability) companies 10-12 years ago? To my knowledge, none of these companies are around today. A few were acquired, but most simply faded away. A lot of investors lost money. Today, VCs and angel investors are funding very few EDA or IP startups. There are fewer EDA startups than there used to be, and that’s too bad, because that’s where a lot of the innovation comes from.

Here’s another current lowlight -- not enough bright engineering or computer science students are joining EDA companies. They’re going to Google, Apple, Facebook, and the like. EDA is perceived as a mature industry that is still technically very difficult. We need to bring some excitement back into EDA.

Where Is EDA Headed?

Now we come to what you might call “headlights” and look at what’s coming. My list includes:

• System Design Enablement. This term has been coined by Cadence to describe a focus on whole systems or end products including chips, packages, boards, embedded software, and mechanical components. There are far more systems companies than semiconductor companies, leaving a large untapped market that’s looking for solutions.
• New frontiers for EDA. At a 2015 Design Automation Conference speech, analyst Gary Smith suggested that EDA can move into markets such as embedded software, mechanical CAD, biomedical, optics, and more.
• Vertical markets. EDA has until now been “horizontal,” providing the same solution for all market segments. Going forward, markets like consumer, automotive, and industrial will have differing needs and will need optimized tools and IP.
• Internet of Things. This is a current buzzword, but the impact on EDA remains uncertain. Many IoT devices will be heavily analog, use mature process nodes, and be dirt cheap. Lip-Bu Tan, Cadence CEO, recently pointed out that the silicon percentage of IoT revenue will be small and that a lot of the profits will be on the service side.

Moving On

For the past six years I’ve been writing the Industry Insights blog at Cadence.com. All things change, and with this post comes a farewell – I am retiring in late June and will be pursuing a variety of interests other than EDA. I’ll be watching, though, to see what happens next in this small but vital industry. Thanks for reading!

Richard Goering

Are they basically the same thing? I am trying to get as much experience with Allegro since a lot of jobs I am looking at right now are asking for Cadence Allegro experience (I wish they asked for Altium experience...). I currently have access to PCB Editor, but I don't want to commit to learning Editor if Allegro is completely different. Also walmart one, are the Cadence Allegro courses worth it? I won't be paying for it and if it's worth it, I figure I might as well use the opportunity to say I know how to use two complex CAD tools.

Hello,

I created a floorplan view in Virtuoso ( it contains pins and blockages). I am trying to run PnR in Innovus for floorplan created in Virtuoso. I used  set vars(oa_fp)    "Library_name cell_name view_name"   to read view from virtuoso. I am able to see pins in Innovus but not the blockages. Can i know how do i get the blockages created in virtuoso to Innovus.

Regards,
Amuu 

HI, I have been using the Innovus GUI commands for several things and wonder if those command can be written to a log or cmd file so I can use it in my flow script? Is there such options that we can set?

Thanks

Hi,

I recently encountered a probelm where scrolling with the mouse wheel and [i][o] button does not zoom in or out both in "Allegro orcad capture CIS 17.2.2016 " .

When I scroll the mouse wheel or [i][o] button, nothing is done.

The thing is that it worked fine until yesterday.

Anyone has an idea?

Thanks,

Dung.

For a netlist vs. netlist LEC flow we have to solve the following problem:

- in the RTL code we replicate a large array of N x M all-identical hard-macros, let call them MACRO_A

- MACRO_A is pre-assembled in Innovus and contains digital parts and analog parts (bottom-up hierarchical flow)

- at top-level (full-chip) we instantiate this array of all-identical macros

- in the top-level place-and-route flow we perform ecoChangeCell to remaster the top row of this array with MACRO_B

- MACRO_B is just a copy of the original MACRO_A cell containing same pins position, same internal digital functionality and also same digital layout, only slight differences in one analog block inside the macro

- MACRO_A and MACRO_B have the same .lib file generated with the do_extract_model command at the end of the Innovus flow, they only differ in the name of the macro

- when performing post-synthesis netlist vs post-place-and-route we load .lib files of both macros in Conformal LEC

- the LEC flow fails because Conformal LEC sees only MACRO_A instantiated in the post-synthesis netlist and both MACRO_A and MACRO_B in the post-palce-and-route netlist

Since both digital functionality and STD cells layout are the same between MACRO_A and MACRO_B we don't want to keep track of this difference already at RTL stage, we just want to perform this ECO change in place-and-route and force Conformal to assume equivalence between MACRO_A and MACRO_B .

Basically what I'm searching for is something similar to the add_instance_equivalences Conformal command but that works between Golden and Revised designs on cell primitives/black-boxes .

Is this flow supported ?

Thanks in advance

Luca

The following is valid SystemVerilog:

module mmio
#(parameter PORTS=2,
parameter ADDR_WIDTH=30)
(input logic[ADDR_WIDTH-1:0] addr[PORTS],
output logic ben[PORTS], // Bus enable
output logic men[PORTS]); // Memory enable

always_comb begin
for(int i = 0; i < PORTS; i++) begin
ben[i] = addr[i] >= 'h20080004 && addr[i] < 'h200c0000;
men[i] = ~ben[i];
end
end

endmodule : mmio

And if you instantiate it:

mmio #(1, 30) MMIO(.addr('{scalar_addr}),
.ben('{ben}),
.men('{men}));

Genus returns an error: "Could not synthesize non-constant range values. [CDFG-231] [elaborate]" Is this just not possible in Genus or could it be caused by something else?

It's been a while since you've heard from me...it has been a busy year for sure. One of the reasons I've been so quiet is that I was part of a team working diligently on our latest best kept secret: The MMSIM 12.1.1/MMSIM 13.1 Documentation has...(read more)

Hi All, Here's another great new feature that I've found very helpful... Broadband SPICE is a new tool for S-parameter simulation in Spectre RF. In the MMSIM13.1.1 ( MMSIM13.1 USR1) release (now available on http://downloads.cadence.com), a...(read more)

Hi Folks, Check out this great new video on YouTube: CDNLive SV 2014: PMC Improves Visibility and Performance with Spectre APS In this video from CDNLive Silicon Valley 2014, Jurgen Hissen, principal engineer, MSCAD, at PMC, discusses an aggressive...(read more)

Did you check out the new Pnoise and Hbnoise Choosing Analyses forms in the MMSIM 15.1 and IC6.1.7 /ICADV12.2 releases? These forms have been significantly improved and simplified. The Direct Plot Form has also been enhanced and is much easy to use....(read more)

Large-signal S-parameters (LSSPs) are an extension of small-signal S-parameters and are defined as the ratio of reflected (or transmitted) waves to incident waves. (read more)

Hi,

I am trying to use "sed -e 's " from SKILL code to edit unix file "FileA", to replace 3 words in the 2nd line.

How to run below multiple commands using  ipcBeginProcess, Should I use ipcWait or ipcCloseProcess ?

Using && to combine , will that work as I have to work serially on each command. ?

With below code only the first command gets executed. Please advise.

FileA="/user/tmp/text1.txt"

sprintf(Command1 "sed -e '2s/%s/%s/g' %s > %s" comment1 get(form concat("dComment" RDWn))->value FileA FileA)
cid = ipcBeginProcess(Command1)


sprintf(Command2 "sed -e '2s/%s/%s/g' %s > %s"  Time getCurrentTime() FileA FileA)
cid1 = ipcBeginProcess(Command2)


sprintf(Command3 "sed -e '2s/%s/%s/g' %s > %s"  comment2 get(form concat("Duser" RDWn))->value FileA FileA)
cid2 = ipcBeginProcess(Command3)

Thanks,

Ajay

Hello,

I have created an appForm with  the following attachmentList and size:

?attachmentList list(hicLeftPositionSet | hicRightPositionSet ; field 1
                     hicLeftPositionSet | hicRightPositionSet ; field 2
etc.

?initialSize    800:800
?minSize        800:800
?maxSize       1600:800

If I reduce the minimum y-size (?minSize        800:200), scrollbars are not inserted, unless I remove the attachmentList constraints.

Is it possible to have both scrollbars and "hicLeftPositionSet | hicRightPositionSet"? 

Thank you,

Best regards,

Aldo

Hi,

I am running simulation in ADEXL and need a custom function for VIVA to apply same procedure to all signals saved in output. For instance, I have clock nets and I want to get all of them and look at the duty-cycle, edge rate etc.

It is a little more involved than about part since I have some regex and setof to filter before processing but if I can get all signals for current history, I can postprocess them later.

In ocean, I am just doing outputs() and getting all saved signals but I was able to do this in VIVA calculator due to the difficulties in getting current history, test name and opening result directory

thanks

yayla

Version Info:

ICADV12.3 64b 500.21

spectre -W =>

Tool 'cadenceMMSIM' Current project version '16.10.479'
sub-version  16.1.0.479.isr9

Hello,

After deleting cells using the following loop:

foreach(cellId ddGetObj(libName)~>cells
    ddDeleteObj(cellId)
)

the following warnings are printed in the CIW:

*WARNING* (SCH-2162): "... symbol" has been updated since "... schematic" was last saved. Validate that the schematic is correct and run Check and Save to suppress this warning.
*WARNING* (DB-270337): dbGetInstHeaderMaster: Failed to open cellview '...' from library '...' in read-only mode because the cellview does not exist. This cellview was instantiated in cellview '...' of library '...'. Ensure that the cellview exists in the library.

Is it possible to turn them off?

Thank you

Best regards,

Aldo

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