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Cadence tapes out 32G UCIe interface IP for high speed, highly efficient chiplet designs and demonstrate high data rate performance in TSMC's 3nm technology(read more)

Hi! 

I am attempting to create a very simple test pcell that contains a single Nmos 4 terminal device (Gate, Source, Drain, Backgate). However, unlike other devices I have used in the past, the backgate terminal of the device I wish to include within the pcell is an inherited connection, and the other 3 are physical terminals. Note that for the pcell master, I do not want any inherited connections, just physical pins. Hence I need to drive this inherited connection with a pin within my pcell. I started implementing the symbol and schematic first, ensuring I could obtain the correct connectivity, extract netlist, etc. I thought I had it hooked up correctly, but alas I am failing to export the CDL. Let me explain my current approach.

Schematic:

Create the 4 physical pins using a combination of dbCreateInst (for the pin isnt), dbMakeNet, dbCreateTerm and dbCreatePin.

Create the device instance using dbCreateInstByMasterName and setting the desired cdf parameters + callbacks.

For the physical terminals of the device, I'm using dbCreateConnByName to make the connection to the appropriate net that was created above.

For the inherited connection, I am creating a netSet property like so: dbCreateProp(newinst deviceTermName "netSet" netName)

Symbol:

Create the 4 physical pins using a combination of dbCreateRect, dbMakeNet, dbCreateTerm, dbCreatePin.

And then create whatever symbol design I wish using the likes of dbCreateRect, dbCreateLine, etc. 

Everything works fine when using a device without an inherited connection, so I'm guessing I'm missing something along this line... Also, if I copy the contents of the pcell schematic to a regular schematic view, do a check and save, the view extracts just fine. So I wonder if the check and save it fixing the connectivity that I may not have. 

Thanks for any possibly engagement or suggestions 🙂

Keelan

Microwave Office is Cadence’s tool-of-choice for RF and microwave designers designing everything from III-V 5G chips, to RF systems in board and package technologies. These types of designs require close interaction between the schematic and its layout. A new Training Byte demonstrates how the schematic-layout connections is built into Microwave Office.(read more)

At times, there might arise a condition in the design where you need to push the net of selected pins to all its physically connected objects. For example, a few pins are updated with a new net, and it is required to push the new net to all its connected objects. At times, you might update the die or copy routing to other components, when a portion of routing gets the wrong net.

To propagate the net of the pin to all its physically connected objects, Allegro X APD uses the standalone command, Push Connectivity.

You can call the command through Logic > Push Connectivity.

Alternately, you can use the push connectivity command at the command line. Once the command is active, it lets you select pins or symbols that will be used to push net connectivity to all connected objects.

Presently, dynamic shapes and filled rectangles are not considered as part of connectivity. Static shapes are supported.

Please give me some ideas. Thank you very much.

Read this blog to know how you can easily create and insert connect modules using Spectre AMS Designer with the Verilog-AMS standard language defined by Accellera. (read more)

Read this blog to know more about the innovation behind Universal Connect Modules (UCM).(read more)

Hi 

I am looking into chamfering the edge of PCB for Board edge connectors. I have performed fillet command earlier but new to chamfering.

Below is the description :

As seen above, the PCB edge are chamfered in thickness as well as at the corners.

Using OrCAD PCB hotfix S023.

I have a design which says there are 6 unconnected nets. But 'Display All Nets, shows only 4 unconnected. When I try to look at the non-connection, is appears connected and nothing shows??

What is happening?

Hello,


I would like to use the simulation software xrun/simvision that comes with XCELIUM. We are currently using classroom licenses and want to disable all ip addresses on the student pcs except the license server ip. We want to make sure that students cannot copy confidential data from the Cadence tools.


Problem:

When I launch the xrun simulation while all ip addresses are blocked, it starts but the performance is very slow. The GUI starts after 5 minutes and the simulation is ready after 10 minutes. The interesting thing is that when I enable all blocked ip addresses, everything works at a reasonable speed.

Terminal Output (execution without internet connection):

xrun -gui design.vhd

waiting for SimVision/Verisium Debug to connect...


Is there a way to run the simulation tools without an Internet connection? Or can you give me the ip addresses that are used by the simulation tools so that I can enable only those specific ips?


Regards,

Max

First time user of JasperGold. Chip level verif. I want to prove that an arbiter and a buffer are connected. I want to use the connectivity app to do that.

I see from the user guide, that I should provide a connectivity map, but i have no idea how to construct one.
The training videos said use this command: check_conn -generate_template jasper_template.xlsm -xlsm
But that did nothing, or at least it did not produce a file that i could find

[<embedded>] % check_conn -generate_template jasper_template.xlsm -xlsm
ERROR (ESW104): Invalid command formation.
Problem occurs with "-generate_template -xlsm".

And even if it did, I don't even know what's in the file, and whether it contains the two ips I'm trying to check.

I'm hoping someone can give me a bit of a boost here with some knowledge.

Cadence Clarity 3D Solver supports encrypted component models! Using this functionality, vendors can supply their 3D components, such as connectors, to end customers without revealing the physical IP of these designs. The first connector vendor to take advantage of this functionality is Japan Aviation Electronics (JAE),(read more)

I have a small shape for connecting three SMD pads, but it won't connect to one of the pads (0.2x0.6 mm). Thermal relief connects are set to Full contact for SMD pin in Shape parameters, but that doesn't help.

However, if I decrease the Minimum aperture for gap width in Void controls in Shape parameters to something below 0.2 mm the shape connects to the pad. But it is a little contracted at the pad entrance. Just 0.002 mm. What is going on here? 

Tried to attach some pictures, but I get: "An error occurred. Please try again or contact your administrator.". Will try later again.

/F