An amorphous oxide thin film containing amorphous oxide is exposed to an oxygen plasma generated by exciting an oxygen-containing gas in high frequency. The oxygen plasma is preferably generated under the condition that applied frequency is 1 kHz or more and 300 MHz or less and pressure is 5 Pa or more. The amorphous oxide thin film is preferably exposed by a sputtering method, ion-plating method, vacuum deposition method, sol-gel method or fine particle application method.

An object is to manufacture and provide a highly reliable semiconductor device including a thin film transistor with stable electric characteristics. In a method for manufacturing a semiconductor device including a thin film transistor in which a semiconductor layer including a channel formation region serves as an oxide semiconductor film, heat treatment for reducing impurities such as moisture (heat treatment for dehydration or dehydrogenation) is performed after an oxide insulating film serving as a protective film is formed in contact with an oxide semiconductor layer. Then, the impurities such as moisture, which exist not only in a source electrode layer, in a drain electrode layer, in a gate insulating layer, and in the oxide semiconductor layer but also at interfaces between the oxide semiconductor film and upper and lower films which are in contact with the oxide semiconductor layer, are reduced.

A transistor device includes a compound semiconductor body having a first surface and a two-dimensional charge carrier gas disposed below the first surface in the compound semiconductor body. The transistor device further includes a source in contact with the two-dimensional charge carrier gas and a drain spaced apart from the source and in contact with the two-dimensional charge carrier gas. A first passivation layer is in contact with the first surface of the compound semiconductor body, and a second passivation layer is disposed on the first passivation layer. The second passivation layer has a different etch rate selectivity than the first passivation layer. A gate extends through the second passivation layer into the first passivation layer.

Improved silicon solar cells, silicon image sensors and like photosensitive devices are made to include strained silicon at or sufficiently near the junctions or other active regions of the devices to provide increased sensitivity to longer wavelength light. Strained silicon has a lower band gap than conventional silicon. One method of making a solar cell that contains tensile strained silicon etches a set of parallel trenches into a silicon wafer and induces tensile strain in the silicon fins between the trenches. The method may induce tensile strain in the silicon fins by filling the trenches with compressively strained silicon nitride or silicon oxide. A deposited layer of compressively strained silicon nitride adheres to the walls of the trenches and generates biaxial tensile strain in the plane of adjacent silicon fins.

A semiconductor device, in particular a solar cell, comprises a semiconductor substrate having a semiconductor substrate surface and a passivation composed of at least one passivation layer which surface-passivates the semiconductor substrate surface, wherein the passivation layer comprises a compound composed of aluminum oxide, aluminum nitride or aluminum oxynitride and at least one further element.

The present teachings relate to new semiconducting polymers. The polymers disclosed herein can exhibit high carrier mobility and/or efficient light absorption/emission characteristics, and can possess certain processing advantages such as solution-processability and/or good stability at ambient conditions.

Accordingly, a method of forming a metal chalcogenide material may comprise introducing at least one metal precursor and at least one chalcogen precursor into a chamber comprising a substrate, the at least one metal precursor comprising an amine or imine compound of an alkali metal, an alkaline earth metal, a transition metal, a post-transition metal, or a metalloid, and the at least one chalcogen precursor comprising a hydride, alkyl, or aryl compound of sulfur, selenium, or tellurium. The at least one metal precursor and the at least one chalcogen precursor may be reacted to form a metal chalcogenide material over the substrate. A method of forming a metal telluride material, a method of forming a semiconductor device structure, and a semiconductor device structure are also described.

An optoelectronic semiconductor component includes a radiation emitting semiconductor chip having a radiation coupling out area. Electromagnetic radiation generated in the semiconductor chip leaves the semiconductor chip via the radiation coupling out area. A converter element is disposed downstream of the semiconductor chip at its radiation coupling out area. The converter element is configured to convert electromagnetic radiation emitted by the semiconductor chip. The converter element has a first surface facing away from the radiation coupling out area. A reflective encapsulation encapsulates the semiconductor chip and portions of the converter element at side areas in a form-fitting manner. The first surface of the converter element is free of the reflective encapsulation.

Disclosed are molecular and polymeric compounds having desirable properties as semiconducting materials. Such compounds can exhibit desirable electronic properties and possess processing advantages including solution-processability and/or good stability.

An input receiver circuit including a single-to-differential amplifier and a semiconductor device including the input receiver circuit are disclosed. The input receiver circuit includes a first stage amplifier unit and a second stage amplifier unit. The first stage amplifier unit amplifies a single input signal in a single-to-differential mode to generate a differential output signal, without using a reference voltage. The second stage amplifier unit amplifies the differential output signal in a differential-to-single mode to generate a single output signal.

A microwave semiconductor amplifier includes a semiconductor amplifier element, an input matching circuit and an output matching circuit. The semiconductor amplifying element includes an input electrode and an output electrode and has a capacitive output impedance. The input matching circuit is connected to the input electrode. The output matching circuit includes a bonding wire and a first transmission line. The bonding wire includes first and second end portions. The first end portion is connected to the output electrode. The second end portion is connected to one end portion of the first transmission line. A fundamental impedance and a second harmonic impedance seen toward the external load change toward the one end portion. The second harmonic impedance at the one end portion has an inductive reactance. The output matching circuit matches the capacitive output impedance of the semiconductor amplifying element to the fundamental impedance of the external load.

A semiconductor package device comprises a radio frequency power transistor having an output port operably coupled to a single de-coupling capacitance located within the semiconductor package device. The single de-coupling capacitance is arranged to provide both high frequency decoupling and low frequency decoupling of signals output from the radio frequency power transistor.

An apparatus of semiconductor process including a chuck and a vacuum source is provided. The chuck has a plurality of holes for holding a semiconductor substrate, and the vacuum source is used for providing vacuum suction through the holes to make the semiconductor substrate be subjected to varied suction intensities according to a warpage level thereof.

Provided are a polycrystalline silicon ingot casting mold and a method for producing a polycrystalline silicon ingot casting mold, with which high-quality silicon ingots can be obtained at high yields by minimizing sticking with the surfaces of the silicon ingot casting mold, and losses and damages that occur when solidified silicon ingot is released from the mold. The method for producing a polycrystalline silicon ingot casting mold having a release layer, including: forming a slurry by mixing a silicon nitride powder with water, coating the surface of the mold with the slurry, and heating the mold at 400 to 800° C. in an atmosphere containing oxygen, after coating the slurry.

A polycrystalline silicon ingot casting mold, and method for producing same. Mold release material being obtained by blending a silicon nitride powder (A) having an average particle diameter along the short axis of 0.6 to 13 μm with a silicon nitride powder (B) having an average particle diameter along the short axis of 0.1 to 0.3 μm at a weight ratio of 5:5 to 9:1; coating the mold surface with the slurry; and a heating the mold at 800 to 1200° C. in an atmosphere containing oxygen.

The present invention relates to an electronic device comprising at least one organic semiconducting material according to the following formula (I): wherein R1-4 are independently selected from H, halogen, CN, substituted or unsubstituted C1-C20-alkyl or heteroalkyl, C6-C20-aryl or C5-C20-heteroaryl, C1-C20-alkoxy or C6-C20-aryloxy, Ar is selected from substituted or unsubstituted C6-C20-aryl or C5-C20-heteroaryl, and R5 is selected from substituted or unsubstituted C6-C20-aryl or C5-C20-heteroaryl, H, F or formula (II).

According to one embodiment, a semiconductor light emitting device includes a first semiconductor layer, a light emitting layer, a second semiconductor layer, a p-side electrode, a plurality of n-side electrodes, a first insulating film, a p-side interconnect unit, and an n-side interconnect unit. The p-side interconnect unit is provided on the first insulating film to connect to the p-side electrode through a first via piercing the first insulating film. The n-side interconnect unit is provided on the first insulating film to commonly connect to the plurality of n-side electrodes through a second via piercing the first insulating film. The plurality of n-side regions is separated from each other without being linked at the second surface. The p-side region is provided around each of the n-side regions at the second surface.

The present invention relates to a silicone rubber like material and a printing device including a stamp layer (100;201) comprising such a material. The material is suitable for use in soft lithography as it enables stable features having dimensions in the nanometer range to be obtained on a substrate, and also allows for the accommodation onto rough and non-flat substrate surfaces. The invention also relates to methods for manufacturing the silicone rubber like material and stamp layer (100;201) and use thereof in lithographic processes.

A semiconductor apparatus includes a pattern conversion circuit configured to generate conversion data in response to a monitoring enable signal, pattern select signals and parallel input data; a transmission circuit configured to output the conversion data as serial data in response to a plurality of clocks; a reception circuit configured to output the serial data as parallel output data in synchronization with the plurality of clocks; and a monitoring circuit configured to generate a result signal in response to the plurality of clocks, clock select signals and the serial data.

A natural gas-containing stream such as biogas from landfills and sewage treatment plants is freed of siloxane contaminants by passing the biogas through a bed containing an adsorbent having a neutral surface, which adsorbs the siloxanes. When the bed of neutral adsorbent is filled to capacity, the adsorbent bed is heated to remove the siloxanes and regenerate the bed. The neutral adsorbent reduces disadvantageous reactions between the adsorbent and siloxane and other impurities in the natural gas-containing stream.

Tyre and rubber composition for tyre, based on at least one isoprene elastomer (for example natural rubber), an inorganic filler as reinforcing filler (for example silica) and a coupling system which provides the bonding between the said reinforcing inorganic filler and the isoprene elastomer, the said coupling system comprising, in combination: as first coupling agent, a silane sulphide compound;as second coupling agent, an at least bifunctional organosilicon compound (for example an organosilane or an organosiloxane) which can be grafted to the elastomer by means of an azodicarbonyl functional group (—CO—N═N—CO—).

A semiconductor device includes a plurality of circuits, a general bus configured to be connected to each of the plurality of circuits and to provide a general channel among the plurality of circuits, and a designated bus configured to be connected to a subgroup of circuits from among the plurality of circuits and to provide a designated channel among the subgroup of circuits.

A semiconductor substrate for use in an integrated circuit, the semiconductor substrate including a channel defined on a surface of the substrate. The channel includes a first wall, a second wall, and a third wall. The first wall is recessed from the surface. The second wall extends from the surface to the first wall. The third wall extends from the surface to the first wall and faces the second wall across the channel. At least one of the second wall and the third wall includes a plurality of structures projecting into the channel from the second wall or the third wall.

A silicon-based thermal energy transfer apparatus that aids dissipation of thermal energy from a heat-generating device, such as an edge-emitting laser diode, is provided. In one aspect, the apparatus comprises a silicon-based base portion having a first primary surface and a silicon-based support structure. The silicon-based support structure includes a mounting end and a distal end opposite the mounting end with the mounting end received by the base portion such that the support structure extends from the first primary surface of the base portion. The support structure includes a recess defined therein to receive the edge-emitting laser diode. The support structure further includes a slit connecting the distal end and the recess to expose at least a portion of a light-emitting edge of the edge-emitting laser diode when the edge-emitting laser diode is received in the support structure.

A Si or Ge semi-conductor substrate includes an oxygen monolayer on a surface thereof. The oxygen monolayer can be fractional or complete. A Si4+ or Ge4+ oxidation state of the surface of the Si or Ge substrate, respectively, resulting from the presence of the oxygen monolayer represents less than 50%, preferably less than 40% and more preferably less than 30% of the sum of Si1+, Si2+, Si3+ and Si4+ oxidation states or the sum of Ge1+, Ge2+, Ge3+ and Ge4+ oxidation states, respectively, as measured by XPS.

A method for slicing a plurality of wafers from a crystal includes providing a crystal of semiconductor material having a longitudinal axis, a cross section and at least one pulling edge. The crystal is fixed on a table and guided through a wire gang defined by sawing wire so as to form the wafers. The guiding is provided by a relative movement between the table and the wire gang such that entry sawing or exit sawing using the sawing wire occurs in a vicinity of the at least one pulling edge of the crystal.

A method for cooling a cylindrical workpiece during wire sawing includes applying a liquid coolant to a surface of the workpiece. The workpiece is made of semiconductor material having a surface including two end faces and a lateral face. The method includes sawing the workpiece with a wire saw including a wire web having wire sections arranged in parallel by penetrating the wire sections into the workpiece by an oppositely directed relative movement of the wire sections and the workpiece. Wipers are disposed so as to bear on the surface of the workpiece. The temperature of the workpiece is controlled during the wire sawing using a liquid coolant applied onto the workpiece above the wipers so as to remove the liquid coolant with the wipers bearing on the workpiece surface.

A method for detaching a semiconductor chip from a foil uses a die ejector comprising plates having a straight supporting edge and an L-shaped supporting edge comprises: lifting of the plates to a height H1 above the surface of a cover plate;lowering of a first pair of plates with L-shaped supporting edge;optionally, lowering of a second pair of plates with L-shaped supporting edge;lifting of the plates that have not yet been lowered to a height H2>H1;staggered lowering of plates that have not yet been lowered, with at least one or several plates not being lowered;optionally, lowering of the plates that have not yet been lowered to a height H3

The invention provides a method for producing grain-oriented silicon steel with single cold rolling, comprising: 1) smelting, refining and continuous casting to obtain a casting blank; 2) hot rolling; 3) normalization, i.e. normalizing annealing and cooling; 4) cold-rolling, i.e. single cold rolling at a cold rolling reduction rate of 75-92%; 5) decarburizing annealing at 780-880° C. for 80-350 s in a protective atmosphere having a due point of 40-80° C., wherein the total oxygen [O] in the surface of the decarburized sheet: 171/t≦[O]≦313/t (t represents the actual thickness of the steel sheet in mm), the amount of absorbed nitrogen: 2-10 ppm; 6) high temperature annealing, wherein the dew point of the protective atmosphere: 0-50° C., the temperature holding time at the first stage: 6-30 h, the amount of absorbed nitrogen during high-temperature annealing: 10-40 ppm; 7) hot-leveling annealing. The invention may control the primary recrystallization microstructure of steel sheet effectively by controlling the normalization process of hot rolled sheet to form sufficient favorable (Al, Si)N inclusions from nitrogen absorbed by slab during decarburizing annealing and low-temperature holding of high-temperature annealing, facilitating the generation of stable, perfect secondary recrystallization microstructure of the final products. In addition, the invention avoids the impact of nitridation using ammonia on the underlying layer in prior art, and thus the formation of a good glass film underlying layer is favored.

A low power consumption semiconductor device is provided. The semiconductor device includes a decoder, a signal generation circuit, and a display device. The decoder includes an analysis circuit and an arithmetic circuit. The analysis circuit has a function of determining whether to decode the received first image data using the received data. The signal generation circuit has a function of generating a signal including an instruction on whether to decode the first image data in response to the determination of the analysis circuit. The arithmetic circuit has a function of decoding the first image data in response to the signal. The display device has a function of maintaining a second image displayed on the display device in the case where the first image data is not decoded in the arithmetic circuit.

A semiconductor device includes first to fourth terminals, a switch circuit, and an integrating circuit. The integrating circuit includes an amplifier circuit having a (−) terminal, a first (+) terminal, and a second (+) terminal. The integrating circuit is configured to integrate an input signal of the (−) terminal using an average voltage of a voltage of the first (+) terminal and a voltage of the second (+) terminal as a reference voltage. The switch circuit is configured to electrically connect the (−) terminal to the second terminal, the first (+) terminal to the first terminal, the second (+) terminal to the third terminal the (−) terminal to the third terminal, the first (+) terminal to the second terminal, and the second (+) terminal to the fourth terminal. The present semiconductor device is used as a semiconductor device sensing a current flowing through a pixel in a display panel.

A semiconductor memory device includes first and second memory cells, each of which includes a charge storage layer, a first bit line that is connected to the first memory cell, and a second bit line that is connected to the second memory cell. A writing operation includes multiple loops of a programming operation and a verification operation, and first data is written in the first memory cell, and second data different from the first data is written in the second memory cell through the writing operation. In a first loop of the writing operation, a first voltage is applied to the first bit line and the second bit line is maintained in an electrically floating state during the programming operation, and a verification operation relating to the second data is not performed and a verification operation relating to the first data is performed.

The semiconductor device includes a bit line, a transistor, a retention node, and a capacitor. The transistor has a function of charging or discharging the retention node. The capacitor has a function of retaining a potential of the retention node. A voltage greater than the sum of a writing voltage and a threshold voltage is applied to a gate of the transistor. When the transistor is turned on, a first potential is supplied to the bit line with a reference potential in a floating state. A voltage less than the sum of the writing voltage and the threshold voltage is applied to the gate of the transistor. When the transistor is turned on, a second potential is supplied to the bit line with a reference potential in a floating state. With use of the first and second potentials, the threshold voltage of the transistor is calculated without being influenced by parasitic capacitance and variations in the storage capacitance of the capacitor.

A signal shifting circuit may include a bank selection signal generation unit suitable for generating a bank selection signal synchronized with a first clock in response to a bank address and an internal write signal; and a shifting device suitable for generating a shifted bank selection signal by shifting the bank selection signal by a number of times according to latency information and for advancing a phase of the shifted bank selection signal whenever shifting the bank selection signal once or more so that the shifted bank selection signal is synchronized with a second clock having a phase leading a phase of the first clock.

A semiconductor device capable of stably holding data for a long time is provided. A transistor including a back gate is used as a writing transistor of a memory element. In the case where the transistor is an n-channel transistor, a negative potential is supplied to a back gate in holding memory. The supply of the negative potential is stopped while the negative potential is held in the back gate. In the case where an increase in the potential of the back gate is detected, the negative potential is supplied to the back gate.

A semiconductor memory device may include: a plurality of memory mats; and a plurality of sense amplifier arrays arranged alternately with the memory mats, each sense amplifier array being suitable for sensing and amplifying data of memory mats adjacent thereto, wherein during a data sensing operation to a memory mat among the plurality of memory mats, in addition to a sense amplifier for the memory mat and sense amplifiers positioned immediately above and below the sense amplifier for the memory mat, at least one additional sense amplifier closest to the sense amplifier for the memory mat is also activated for providing additional amplification.

An apparatus includes a first terminal configured to communicate data with an outside of the apparatus, a second terminal configured to receive a first power source potential, a third terminal configured to receive a second power source potential lower than the first power source potential, a fourth terminal configured to be coupled to a calibration resistor, an output buffer including first to third nodes coupled to the first to third terminals respectively, and a replica circuit including fourth and fifth nodes coupled to the second and third terminals respectively, and sixth node coupled to the fourth terminal.

A semiconductor memory device may include: a memory bank comprising a plurality of word lines; a smart command generation unit suitable for generating a smart refresh command, which is enabled at a random cycle, in response to an active command; and a refresh operation control unit suitable for performing a refresh operation to at least one of adjacent word lines of a target word line among the plurality of word lines in response to the smart refresh command.

According to one embodiment, a semiconductor storage apparatus includes a memory cell array and a read circuit. The memory cell array includes a memory cell which is connected to a word line. A threshold voltage of the memory cell corresponds to a data value of multiple bits. The read circuit receives designation of one bit among the multiple bits, applies a first reading voltage and a second reading voltage corresponding to the designated bit to the word line, senses ON or OFF of the memory cell for each reading voltage, and outputs a first sensed value and a second sensed value after performing the sensing for each reading voltage. The first sensed value is a sensing result in a case where the first reading voltage is applied. The second sensed value is a sensing result in a case where the second reading voltage is applied.

A memory device includes a first string and a second string. The first string includes first and second transistors and first cell transistors coupled in series between a source line and a bit line. The second string includes third and fourth transistors and second cell transistors coupled in series between the source line and the bit line. During a read, a gate of the fourth transistor is applied with a voltage to turn off the transistor, and after start of application of voltages to the first cell transistors, the gate of the fourth transistor is applied with a voltage substantially the same as a voltage applied to the source line.

According to one embodiment, a first well of the first conductivity type which is formed in a substrate. a second well of a second conductivity type which is formed in the first well. The plurality of memory cells, the plurality of first bit line select transistors, and the plurality of second bit line select transistors are formed in the second well, and the plurality of first bit line select transistors and the plurality of second bit line select transistors are arranged on a side of the sense amplifier with respect to the plurality of memory cells of the plurality of bit lines.

According to one embodiment, a semiconductor storage device includes a memory cell array having memory cell capable of holding N-bit data; and a sense amplifier comprising a first latch holding information on a threshold distribution, a second latch holding write data, and a third latch holding lower information of the N-bit data, and supplying a first to a fourth voltages to the memory cell to write the data to the memory cell using the first to fourth voltages. The sense amplifier supplies the first to third voltages to the memory cell based on information in the second and the third latches, and based on a result of transfer of the information held by the first latch to the second latch, supplies the fourth voltage or the first voltage to the memory cell.

According to one embodiment, a semiconductor memory device includes: first to third pages; first to third word line; and row decoder. In data writing, data is written into the first page before data is written into the second page. The row decoder is configured to apply first to third verify voltages to the gates of the first to third memory cells in a program verify operation.

Semiconductor memory devices are provided. The semiconductor memory device includes an input/output (I/O) drive controller, a data I/O unit and a data transmitter. The input/output (I/O) drive controller generates drive control signals and an input control signal for driving first and second global I/O lines in a first test mode or a second test mode. The data I/O unit drives the first global I/O line in response to an input data when a write operation is executed in the first test mode and to drive the first and second global I/O lines in response to the drive control signals when the write operation is executed in the second test mode. The data transmitter transfers the data on the first global I/O line onto first and second local I/O lines to store the data on the first global I/O line in a memory cell array portion when the write operation is executed in the first test mode. The data transmitter also transfers the data on the first and second global I/O lines onto the first and second local I/O lines to store the data on the first and second global I/O lines in the memory cell array portion when the write operation is executed in the second test mode. Related methods are also provided.

Provided is a semiconductor device capable of holding data for a long period. The semiconductor device includes first to third transistors, a capacitor, and a circuit. The third transistor includes a first gate and a second gate. A gate of the first transistor is electrically connected to a first terminal of the capacitor. A first terminal of the first transistor is electrically connected to the second gate. A second terminal of the first transistor is electrically connected to the circuit. A gate of second transistor is electrically connected to a first terminal of the second transistor. A first terminal of the second transistor is electrically connected to the second gate. A second terminal of the second transistor is electrically connected to a first terminal of the capacitor. The circuit is configured to generate a negative potential. A channel formation region of the first transistor preferably includes an oxide semiconductor.

A method for fabricating a semiconductor device and a method for operating the semiconductor device are provided. The method for fabricating a semiconductor device includes forming a first electrode layer; forming a material layer, including conductive path components, over the first electrode layer; forming a second electrode layer over the material layer; performing a forming operation, which includes initially creating, in the material layer, a conductive path that electrically connects the first electrode layer to the second electrode layer by applying one of a predetermined voltage and a predetermined current between the first and second electrode layers, the conductive path including the conductive path components; and performing a first heat-treatment process at a predetermined temperature that removes some of the conductive path components from the conductive path, wherein a resistance state of the material layer changes based on the creation or dissolution of the conductive paths.

An aqueous dispersion for use as a finishing agent for textiles, wherein the dispersion contains a pyrogenically produced, aggregated silicon dioxide powder and a cationic polymer which is soluble in the dispersion, wherein the cationic polymer is present in a quantity such that the particles of the silicon dioxide powder exhibit a positive zeta potential.

A semiconductor device comprises a two-dimensional (2D) material layer, the 2D material layer comprising a channel region in between a source region and a drain region; a first gate stack and a second gate stack in contact with the 2D material layer, the first and second gate stack being spaced apart over a distance; the first gate stack located on the channel region of the 2D material layer and in between the source region and the second gate stack, the first gate stack arranged to control the injection of carriers from the source region to the channel region and the second gate stack located on the channel region of the 2D material layer; the second gate stack arranged to control the conduction of the channel region.

A control switch is connected to a power supply voltage and turns on based on a control signal to output a current. A clamp circuit is connected to a load and performs clamp control of the output voltage of the control switch. A current control element conducts or shuts off a current based on the output voltage to be clamp-controlled. A selector switch group includes switches, and performs switching based on a voltage varying with the current control by the current control element, thereby switching between paths for generating an internal power supply. The switch circuit connects or disconnects the coupling between the clamp circuit and the selector switch group.

A semiconductor device includes a first transistor and a clamping circuit. The first transistor is arranged to generate an output signal according to a control signal. The clamping circuit is arranged to generate the control signal according to an input signal, and to clamp the control signal to a predetermined signal level when the input signal exceeds the predetermined signal level.