An integrated circuit includes a drive circuit with a first inverter circuit with a first transistor of a first conductivity type and a second transistor of a second conductivity type. The drains of the first and second transistors are connected. An output circuit is provided having a third transistor of the second conductivity with a gate connected to the drains of the first and second transistors. A capacitor is connected between the gate and a drain of the third transistor and has a capacitance greater than 0.5 pF and less than or equal to 3.0 pF. A gate width of the first transistor when divided by a gate width of the third transistor has a value of less than 1/100. The output circuit is configured to output a transmission signal from the drain of the third transistor.

A clock generation circuit may include a reference clock generator configured to generate a pair of first reference clocks in an offset code generation mode, a correction code generator configured to generate a reference correction code according to a duty detection signal based on a phase difference between the pair of first reference clocks, and an offset code generator configured to generate an offset code based on the reference correction code and a preset reference code.

A power conversion system may include a plurality of power devices and a sensor operably coupled to at least one of the plurality of power devices and configured to detect a voltage, current, or electromagnetic signature signal associated with the plurality of power devices. The power converter may also include circuitry operably coupled to the plurality of power devices and the sensor. The circuitry may send a respective gate signal to each respective power device of the plurality of power devices, such that each respective gate signal is delayed by a respective compensation delay that is determined for the respective power device based on a respective time delay of the respective power device and a maximum time delay of the plurality of power devices.

A device (442) for producing a dynamic reference signal (UREF) for a control circuit for a power semiconductor switch comprises a reference signal generator (442) for providing a dynamic reference signal (UREF), which has a stationary signal level after elapse of a predefined time following a switching process of the power semiconductor switch, a passive charging circuit (450) which is configured to increase a signal level of the dynamic reference signal in reaction to a switching of a control signal of the power semiconductor switch from an OFF state to ON state for at least one part of the predefined time above the stationary signal level, in order to produce the dynamic reference signal and an output (A) for tapping the dynamic reference signal (UREF).

A system includes a SiC semiconductor power device; a power supply board that is configured to provide power to a first gate driver board via a connector; the first gate driver board that is coupled and configured to provide current to the SiC semiconductor power device, wherein the first gate driver board is coupled to the power supply board via the connector, and wherein the first gate driver board is separated from the power supply board; and an interconnect board that is coupled to the first gate driver board, wherein the interconnect board is configured to couple the first gate driver board a second gate driver board.

A semiconductor apparatus may include a noise determination circuit, a strobe signal control circuit, and a reception circuit. The noise determination circuit may sense and determine noise of a reference voltage, and generate an up control signal and a down control signal. The strobe signal control circuit may adjust a transition timing of a strobe signal in response to the up control signal and the down control signal, and output a control strobe signal. The reception circuit may generate internal data signal in response to external data signal, the reference voltage, and the control strobe signal.

Disclosed is a silicon-based anode active material for a lithium secondary battery. The silicon-based anode active material imparts high capacity and high power to the lithium secondary battery, can be used for a long time, and has good thermal stability. Also disclosed is a method for preparing the silicon-based anode active material. The method includes (A) binding metal oxide particles to the entire surface of silicon particles or portions thereof to form a silicon-metal oxide composite, (B) coating the surface of the silicon-metal oxide composite with a polymeric material to form a silicon-metal oxide-polymeric material composite, and (C) heat treating the silicon-metal oxide-polymeric material composite under an inert gas atmosphere to convert the coated polymeric material layer into a carbon coating layer.

A semiconductor device has a plurality of semiconductor die. A first prefabricated insulating film is disposed over the semiconductor die. A conductive layer is formed over the first prefabricated insulating film. An interconnect structure is formed over the semiconductor die and first prefabricated insulating film. The first prefabricated insulating film is laminated over the semiconductor die. The first prefabricated insulating film includes glass cloth, glass fiber, or glass fillers. The semiconductor die is embedded within the first prefabricated insulating film with the first prefabricated insulating film covering first and side surfaces of the semiconductor die. The interconnect structure is formed over a second surface of the semiconductor die opposite the first surface. A portion of the first prefabricated insulating film is removed after disposing the first prefabricated insulating film over the semiconductor die. A second prefabricated insulating film is disposed over the first prefabricated insulating film.

A method of making a semiconductor device can include providing a wafer comprising a plurality of semiconductor die, wherein each semiconductor die comprises an active surface and a backside opposite the active surface. A photosensitive layer can be formed over the wafer and on a backside of each of the plurality of semiconductor die within the wafer with a coating machine. An identifying mark can be formed within the photosensitive layer for each of the plurality of semiconductor die with a digital exposure machine and a developer, wherein a thickness of the identifying mark is less than or equal to 50 percent of a thickness of the photosensitive layer. The photosensitive layer can be cured. The wafer can be singulated into a plurality of semiconductor devices.

A semiconductor package is provided, including: an insulating base body having a first surface with an opening and a second surface opposite to the first surface; an insulating extending body extending outward from an edge of the first surface of the insulating base body, wherein the insulating extending body is less in thickness than the insulating base body; an electronic element having opposite active and inactive surfaces and disposed in the opening with its inactive surface facing the insulating base body; a dielectric layer formed in the opening of the insulating base body and on the first surface of the insulating base body, the insulating extending body and the active surface of the electronic element; and a circuit layer formed on the dielectric layer and electrically connected to the electronic element. The configuration of the insulating layer of the invention facilitates to enhance the overall structural rigidity of the package.

A semiconductor device includes a first moisture-resistant ring disposed in a peripheral region surrounding a circuit region on a semiconductor substrate in such a way as to surround the circuit region and a second moisture-resistant ring disposed in the peripheral region in such a way as to surround the first moisture-resistant ring.

A semiconductor mounting apparatus includes a storing unit that stores a liquid or a gas, a contact unit that comes into contact with a semiconductor chip when the storing unit is filled with the liquid or the gas, and a sucking unit that sucks up the semiconductor chip to bring the semiconductor chip into close contact with the contact unit.

A system for determining thickness variation values of a semiconductor substrate comprises a substrate vacuumed to a pedestal that defines a reference plane for measuring the substrate. A measurement probe assembly determines substrate CTV and BTV values, and defines a substrate slope angle. A thermal bonding assembly attaches a die to the substrate at a bonding angle congruent with the substrate slope angle. A plurality of substrates are measured using the same reference plane on the pedestal. Associated methods and processes are disclosed.

A method of ultrasonically bonding semiconductor elements includes the steps of: (a) aligning surfaces of a plurality of first conductive structures of a first semiconductor element to respective surfaces of a plurality of second conductive structures of a second semiconductor element; (b) ultrasonically forming tack bonds between ones of the first conductive structures and respective ones of the second conductive structures; and (c) forming completed bonds between the first conductive structures and the second conductive structures.

Package structures and methods are provided to integrate optoelectronic and CMOS devices using SOI semiconductor substrates for photonics applications. For example, a package structure includes an integrated circuit (IC) chip, and an optoelectronics device and interposer mounted to the IC chip. The IC chip includes a SOI substrate having a buried oxide layer, an active silicon layer disposed adjacent to the buried oxide layer, and a BEOL structure formed over the active silicon layer. An optical waveguide structure is patterned from the active silicon layer of the IC chip. The optoelectronics device is mounted on the buried oxide layer in alignment with a portion of the optical waveguide structure to enable direct or adiabatic coupling between the optoelectronics device and the optical waveguide structure. The interposer is bonded to the BEOL structure, and includes at least one substrate having conductive vias and wiring to provide electrical connections to the BEOL structure.

A semiconductor device includes a substrate comprising a trench; a gate dielectric layer formed over a surface of the trench; a gate electrode positioned at a level lower than a top surface of the substrate, and comprising a lower buried portion embedded in a lower portion of the trench over the gate dielectric layer and an upper buried portion positioned over the lower buried portion; and a dielectric work function adjusting liner positioned between the lower buried portion and the gate dielectric layer; and a dipole formed between the dielectric work function adjusting liner and the gate dielectric layer.

Embodiments of the inventive concepts provide a method for manufacturing a semiconductor device. The method includes forming a stack structure including insulating layers and sacrificial layers which are alternately and repeatedly stacked on a substrate. A first photoresist pattern is formed on the stack structure. A first part of the stack structure is etched to form a stepwise structure using the first photoresist pattern as an etch mask. The first photoresist pattern includes a copolymer including a plurality of units represented by at least one of the following chemical formulas 1 to 3, wherein “R1”, “R2”, “R3”, “p”, “q” and “r” are the same as defined in the description.

A performance of a semiconductor device is improved. A film, which is made of silicon, is formed in a resistance element formation region on a semiconductor substrate, and an impurity, which is at least one type of elements selected from a group including a group 14 element and a group 18 element, is ion-implanted into the film, and a film portion which is formed of the film of a portion into which the impurity is ion-implanted is formed. Next, an insulating film with a charge storage portion therein is formed in a memory formation region on the semiconductor substrate, and a conductive film is formed on the insulating film.

A method of manufacturing a semiconductor device according to one embodiment includes forming a first film including a first metal above a processing target member. The method includes forming a second film including two or more types of element out of a second metal, carbon, and boron above the first film. The method includes forming a third film including the first metal above the second film. The method includes forming a mask film by providing an opening part to a stacked film including the first film, the second film and the third film. The method includes processing the processing target member by performing etching using the mask film as a mask.

Embodiments of the inventive concept provide a method for manufacturing a semiconductor device. The method includes forming a stack structure by alternately and repeatedly stacking insulating layers and sacrificial layers on a substrate, sequentially forming a first lower layer and a first photoresist pattern on the stack structure, etching the first lower layer using the first photoresist pattern as an etch mask to form a first lower pattern. A first part of the stack structure is etched to form a stepwise structure using the first lower pattern as an etch mask. The first lower layer includes a novolac-based organic polymer, and the first photoresist pattern includes a polymer including silicon.

A method of forming a semiconductor device is provided such that a trench is formed in a semiconductor body at a first surface of the semiconductor body. Dopants are introduced into a first region at a bottom side of the trench by ion implantation. A filling material is formed in the trench. Dopants are introduced into a second region at a top side of the filling material. Thermal processing of the semiconductor body is carried out and is configured to intermix dopants from the first and the second regions by a diffusion process along a vertical direction perpendicular to the first surface.

A semiconductor device is provided that includes an n-type field effect transistor including a plurality of vertically stacked silicon-containing nanowires located in one region of a semiconductor substrate, and a p-type field effect transistor including a plurality of vertically stacked silicon germanium alloy nanowires located in another region of a semiconductor substrate. Each vertically stacked silicon-containing nanowire of the n-type field effect transistor has a different shape than the shape of each vertically stacked silicon germanium alloy nanowire of the p-type field effect transistor.

To provide a semiconductor device having improved reliability. After formation of an n+ type semiconductor region for source/drain, a first insulating film is formed on a semiconductor substrate so as to cover a gate electrode and a sidewall spacer. After heat treatment, a second insulating film is formed on the first insulating film and a resist pattern is formed on the second insulating film. Then, these insulating films are etched with the resist pattern as an etching mask. The resist pattern is removed, followed by wet washing treatment. A metal silicide layer is then formed by the salicide process.

A method of fabricating a semiconductor device includes forming a gate strip including a dummy electrode and a TiN layer. The method includes removing a first portion of the dummy electrode to form a first opening over a P-active region and an isolation region. The method includes performing an oxygen-containing plasma treatment on a first portion of the TiN layer; and filling the first opening with a first metal material. The method includes removing a second portion of the dummy electrode to form a second opening over an N-active region and the isolation region. The method includes performing a nitrogen-containing plasma treatment on a second portion of the TiN layer; and filling the second opening with a second metal material. The second portion of the TiN layer connects to the first portion of the TiN layer over the isolation region.

A method for forming a semiconductor structure includes forming a strained silicon germanium layer on top of a substrate. At least one patterned hard mask layer is formed on and in contact with at least a first portion of the strained silicon germanium layer. At least a first exposed portion and a second exposed portion of the strained silicon germanium layer are oxidized. The oxidizing process forms a first oxide region and a second oxide region within the first and second exposed portions, respectively, of the strained silicon germanium.

The on-state characteristics of a transistor are improved and thus, a semiconductor device capable of high-speed response and high-speed operation is provided. A highly reliable semiconductor device showing stable electric characteristics is made. The semiconductor device includes a transistor including a first oxide layer; an oxide semiconductor layer over the first oxide layer; a source electrode layer and a drain electrode layer in contact with the oxide semiconductor layer; a second oxide layer over the oxide semiconductor layer; a gate insulating layer over the second oxide layer; and a gate electrode layer over the gate insulating layer. An end portion of the second oxide layer and an end portion of the gate insulating layer overlap with the source electrode layer and the drain electrode layer.

A semiconductor structure is disclosed. The semiconductor structure includes a source trench in a drift region, the source trench having a source trench dielectric liner and a source trench conductive filler surrounded by the source trench dielectric liner, a source region in a body region over the drift region. The semiconductor structure also includes a patterned source trench dielectric cap forming an insulated portion and an exposed portion of the source trench conductive filler, and a source contact layer coupling the source region to the exposed portion of the source trench conductive filler, the insulated portion of the source trench conductive filler increasing resistance between the source contact layer and the source trench conductive filler under the patterned source trench dielectric cap. The source trench is a serpentine source trench having a plurality of parallel portions connected by a plurality of curved portions.

A semiconductor device includes a substrate comprising a channel region and a recess, wherein the recess is located at both side of the channel region; a gate structure formed over the channel region; a first SiP layer covering bottom corners of the gate structure and the recess; and a second SiP layer formed over the first SiP layer and in the recess, wherein the second SiP layer has a phosphorus concentration higher than that of the first SiP layer.

A method of production of a semiconductor device comprising a semiconductor layer forming step of forming a semiconductor layer including an inorganic oxide semiconductor on a board, a passivation film forming step of forming a passivation film comprising an organic material so as to cover the semiconductor layer, a baking step of baking the passivation film, and a cooling step of cooling the passivation film after baking, herein, in the cooling step, a cooling speed from a baking temperature at the time of baking in the baking step to a temperature 50° C. lower than the baking temperature is substantially controlled to 0.5 to 5° C./min in range is provided.

A method is provided for making smooth crystalline semiconductor thin-films and hole and electron transport films for solar cells and other electronic devices. Such semiconductor films have an average roughness of 3.4 nm thus allowing for effective deposition of additional semiconductor film layers such as perovskites for tandem solar cell structures which require extremely smooth surfaces for high quality device fabrication.

Provided are superconducting circuits and, more specifically, methods of forming such circuits. A method may involve forming a silicon-containing low loss dielectric (LLD) layer over a metal electrode such that metal carbides at the interface of the LLD layer and electrode. The LLD layer may be formed using chemical vapor deposition (CVD) at a temperature of less than about 500° C. At such a low temperature, metal silicides may not form even though silicon containing precursors may come in contact with metal of the electrode. Silicon containing precursors having silane molecules in which two silicon atoms bonded to each other (e.g., di-silane and tri-silane) may be used at these low temperatures. The LLD layer may include amorphous silicon, silicon oxide, or silicon nitride, and this layer may directly interface one or more metal electrodes. The thickness of LLD layer may be between about 1,000 Angstroms and 10,000 Angstroms.

One embodiment is a wide stripe semiconductor waveguide, which is cleaved at a Talbot length thereof, the wide stripe semiconductor waveguide having facets with mirror coatings. A system provides for selective pumping the wide stripe semiconductor waveguide to create and support a Talbot mode. In embodiments according to the present method and apparatus the gain is patterned so that a single unique pattern actually has the highest gain and hence it is the distribution that oscillates.

The present disclosure relates to an apparatus for fastening a power semiconductor using an integral springy (elastic) clip, capable of fixing a power semiconductor, such as a diode and a MOSFET, using elasticity of a U-shaped clip by integrally molding the clip onto a housing of a plastic module. The apparatus includes an elastic (springy) clip integrally molded onto a lower surface of the housing and downwardly curved into a U-like shape in a bridge module in which a bridge of the power semiconductor protrudes through a through hole of the housing to be connected to a printed circuit board, whereby the power semiconductor is fixed by a force that the housing presses the power semiconductor.

An abrasive article includes a body having abrasive particles contained within a bond material. The abrasive particles can include a majority content of silicon nitride and a minority content of sintering material including at least two rare-earth oxide materials. In an embodiment, the rare-earth oxide materials can include Nd2O3 and Y2O3. In a particular embodiment, the abrasive particles comprise a content (wt %) of Nd2O3 that is greater than a content of Y2O3 (wt %).

A method for fabricating a semiconductor device includes (a) depositing an insulating film on a semiconductor substrate; (b) forming a recess in the insulating film; (c) depositing a conductive film on the insulating film while filling the recess with the conductive film; and (d) polishing the conductive film. Step (d) includes a first polishing substep of using a first polisher pad conditioned with a first dresser and a second polishing substep of using a second polisher pad conditioned with a second dresser different from the first dresser.

Methods for preparing a silicon bonded PCD material involving a one step, double sweep process and drilling cutters made by such processes are disclosed. The PCD material includes thermally stable phases in the interstitial spaces between the sintered diamond grains. The method sweeps a diamond powder with a binder to form sintered PCD, reacts said molten binder with a temporary barrier separating said binder and said diamond from a silicon (Si) source, and sweeps said sintered PCD with said Si source to form SiC bonded PCD.

A semiconductor device configured to perform an A/D conversion of a wide range of signals is provided. A semiconductor device includes: an input voltage detection unit configured to detect an analog input voltage; a reference voltage setting unit configured to set a reference voltage based on the detected input voltage; an amplifier configured to amplify a difference between the input voltage and the reference voltage; an ADC configured to perform an A/D conversion of an amplified signal; and an arithmetic processing unit configured to calculate a digital voltage corresponding to the input voltage based on a result of the A/D conversion and the reference voltage.

A semiconductor device having an analog/digital conversion circuit converting an analog signal to a digital signal, includes a holding circuit outputting an analog signal having a value according to a value of an analog signal supplied in a first period; and a prediction circuit generating a first digital signal based on bit position information from a prediction table corresponding to the supplied analog signal.

A device for taking up a silicon melt comprises at least one block of a refractory with a capillary structure.

A semiconductor device includes a substrate, a first thin film transistor supported on the substrate and having a first active layer that primarily contains a first oxide semiconductor, and second thin film transistor supported on the substrate and having a second active layer that primarily contains a second oxide semiconductor with a higher mobility than the first oxide semiconductor. The first active layer and the second active layer are positioned on the same insulating layer and contact the same insulating layer.

A semiconductor device includes first and second semiconductor chips mounted on one package. In the first semiconductor chip, a current generation circuit generates a sense current in accordance with a load current and a fault current indicating that an abnormality detection circuit has detected an abnormality, and allows either one of the currents to flow through a current detecting resistor in accordance with presence or absence of detection of the abnormality. In the second semiconductor chip, a storage circuit stores a current value of the fault current obtained in an inspection process of the semiconductor device as a determination reference value. An arithmetic processing circuit sets a standard range based on the determination reference value, and determines presence or absence of detection of the abnormality based on whether or not a current value indicated by a digital signal of an analog-digital conversion circuit is included within the standard range.

Provided is a method for simply evaluating defects caused in interface states in oxide semiconductor thin films and protective films in TFTs having protective films formed on the surface of oxide semiconductor thin films without actually measuring the characteristics of the same. This evaluation method evaluates defects caused in the interface states by measuring electron states in the oxide semiconductor thin film by a contact method or noncontact method. The defects caused in the interface states are any of the following (1)-(3). (1) Threshold value voltage (Vth,) when a positive bias is applied to the thin-film transistor(2) Difference in threshold value voltage (ΔVth) before and after applying the positive bias to the thin-film transistor(3) Threshold value during the first measurement when a plurality of measurements is made of the threshold value voltage when a positive bias is applied to the thin-film transistor.

The present disclosure provides a semiconductor device including: a power supply input section to which a first voltage from a battery cell is input; a boosting section including one end to which the first voltage from the power supply input section is input, and another end that, based on a control signal from a controller, outputs the first voltage or a second voltage boosted from the first voltage from as a power supply voltage; and a comparison section including an output section, a first input section connected to the power supply input section and the one end of the boosting section, and a second input section connected to the another end of the boosting section, the comparison section outputting a voltage from the output section that corresponds to a difference between voltages input to the first input section and the second input section.

A semiconductor device for measuring a voltage of a battery cell, including first and second nodes, and first and second battery voltage measurement units. The first node is configured to receive a first voltage, the first voltage being a voltage of a capacitor that accumulates an electric charge based on the voltage of the battery cell. The first battery voltage measurement unit measures the first voltage through a first path. The second node is configured to receive a second voltage based on the voltage of the battery cell, the second node being different from the first node. The second battery voltage measurement unit measures the second voltage through a second path that is different from the first path.

A semiconductor detector includes a plate-shaped semiconductor part, a signal output electrode for outputting a signal provided at one surface of the semiconductor part, a plurality of curved electrodes provided at the one surface of the semiconductor part and which have distances from the signal output electrode that are different from each other, and an arc-shaped collection electrode for collecting an electric charge generated at the semiconductor part. The plurality of curved electrodes are applied with voltage to generate in the semiconductor part a potential gradient in which a potential varies toward the signal output electrode. The collection electrode is located at a part of the semiconductor part between an adjacent pair of curved electrodes. The collection electrode is connected to a curved electrode located a distance from the signal output electrode shorter than a distance between the collection electrode and the signal output electrode among the curved electrodes.

A semiconductor detector for detecting radiation comprises a first semiconductor part in which an electron and a hole are generated by incident radiation; a signal output electrode outputting a signal base on the electron or the hole; and a gettering part gettering impurities in the first semiconductor part. In addition, the semiconductor detector further comprises a second semiconductor part doped with a type of dopant impurities and having dopant impurity concentration higher than that of the first semiconductor part. The second semiconductor part is in contact with the first semiconductor part. The gettering part is in contact with the second semiconductor part and not in contact with the first semiconductor part.

Embodiments are directed to an electromagnetic memory device having a memory cell and an encapsulation layer formed over the memory cell. The memory cell may include a magnetic tunnel junction (MTJ), and the encapsulation layer may be formed from a layer of hydrogenated amorphous silicon. Amorphous silicon improves the coercivity of the MTJ but by itself is conductive. Adding hydrogen to amorphous silicon passivates dangling bonds of the amorphous silicon, thereby reducing the ability of the resulting hydrogenated amorphous silicon layer to provide a parasitic current path to the MTJ. The hydrogenated amorphous silicon layer may be formed using a plasma-enhanced chemical vapor deposition, which can be tuned to enable a hydrogen level of approximately 10 to approximately 20 percent. By keeping subsequent processing operations at or below about 400 Celsius, the resulting layer of hydrogenated amorphous silicon can maintain its hydrogen level of approximately 10 to 20 percent.

The semiconductor device according to the present invention has an upper electrode, a first lower layer wiring that also functions as a lower electrode, an electrical resistance-changing film interposed between the upper electrode and the first lower layer wiring, a second lower layer wiring, and a contact plug, the contact plug connecting to the upper electrode and to the second lower layer wiring. The present invention yields a semiconductor device with which it is possible to dispose elements in high density while maintaining the reliability and manufacturing yield of the electrical resistance-changing element.

A polymer compound comprising a structural unit represented by the formula (1): wherein R1, R2, R3 and R4 each independently represent an alkyl group, an aryl group or a monovalent heterocyclic group, and these groups optionally have a substituent, two rings A may be the same or different, and represent a thiophene ring, a benzothiophene ring or a thienothiophene ring, n represents 1 or 2, and X represents a halogen atom, an alkyl group, an alkoxy group, an alkylthio group, an amino group, an aryl group, a monovalent heterocyclic group, an alkenyl group or an alkynyl group, and these groups optionally have a substituent, and when n is 2, two groups X may be the same or different.

BE prepared for a Whole Lotta Shakin’ Goin’ On…