The present invention relates to a process for heat integration in the preparation of saturated C3-C20-alcohols, in which a hydrogenation feed comprising at least one C3-C20-aldehyde is hydrogenated in the presence of a hydrogen-comprising gas in a hydrogenation zone and a discharge is taken off from the hydrogenation zone and subjected to distillation in at least one distillation column to give a fraction enriched in saturated C3-C20-alcohols.

A filtration method is disclosed for recovering purified polyether polyol comprising the steps of providing an aqueous solution of a polyether polyol containing an alkali metal catalyst residual formed from a transesterification process utilizing an alkali metal catalyst, contacting the aqueous solution with a stoichiometric excess of magnesium sulfate, magnesium sulfite or a combination thereof to form a second aqueous solution, wherein said stoichiometric excess is based on the amount of said alkali metal catalyst residual. Water is removed from the second aqueous solution at a temperature above a set limit of said polyether polyol to produce a dehydrated slurry containing a polyether polyol phase substantially free of residual alkali metal and a precipitated solid phase comprising sulfate and/or sulfite salts of the alkali metal catalyst, magnesium hydroxide, and excess magnesium sulfate and/or sulfite, wherein the particle size distribution of said precipitated solid phase is controlled to minimize the amount of particles therein that are smaller than 3 microns. The dehydrated slurry is then passed through a filtration system to separate the polyether polyol phase from the precipitated solid phase.

An improved method for recovering a purified polyether polyol comprising the steps of providing an aqueous solution of a polyether polyol containing an alkali metal catalyst residual formed from a transesterification process, contacting the aqueous solution with a stoichiometric excess of magnesium sulfate to form a second aqueous solution, removing water from said second aqueous solution at a temperature above the melt temperature of said polyether polyol to produce a dehydrated slurry containing a molten polyether polyol phase essentially free of residual alkali metal and a precipitated solid phase comprising sulfate and/or sulfite salts of the alkali metal catalyst, magnesium hydroxide, and excess magnesium sulfate and/or sulfide, passing the dehydrated slurry of through a filtration system comprising a filtration press to separate the molten polyether polyol phase from the precipitated solid phase, wherein the filtration press is treated with a filter aid that is essentially free of transition metal oxide content, separating the molten polyether polyol phase substantially free of water, residual alkali metal catalyst and transition metal contaminants from the precipitated solid phase and recovering polyether polyol from the separated polyether polyol phase.

A process for preparation of 2-phenyl ethanol by catalytic hydrogenation of styrene oxide using a catalyst consisting of Pd (II) on basic inorganic support is investigated. The present invention comprises development of new Pd based catalysts. The present method yields 2-phenyl ethanol in 98% selectivity at total conversion of styrene oxide. The present process represents an environment friendly alternative to conventionally used methods in industry and eliminates the reduction step for catalyst preparation. In the present invention the active catalyst is generated in situ during the hydrogenation of styrene oxide. In addition, Pd (II) supported catalysts do not catch fire (non pyrophoric), can be stored under ambient conditions and produce very less or no dust which makes said catalysts suitable for industrial application.

A method for operating an internal combustion engine in which a speed-based feature of the internal combustion engine, which is correlated with an indicated mean effective pressure of the fuel, is determined during the warm-up of the internal combustion engine and an ideal fuel quantity, which is to be injected into at least one combustion chamber of the internal combustion engine during the warm-up, is ascertained therefrom.

Apparatus for orientating a user in a space wherein the space comprises a plurality of zones of which only certain zones constitute functional zones wherein each functional zone includes a first type device containing information relating to the position of the zone in the space and wherein the first type device is reactive to the presence of a second type device associated with the user to provide the user with the information to determine the orientation of the user in the space. A method of orientating the user within the space and guiding the user toward one or more features in the space is also disclosed.

Disclosed is a feature for a vehicle that enables taking precautionary actions in response to conditions on the road network around or ahead of the vehicle, in particular, a blind intersection along a section of road. A database that represents the road network is used to determine locations where a blind intersection is located along a section of road. Then, precautionary action data is added to the database to indicate a location at which a precautionary action is to be taken about the blind intersection located along the section of road. A precautionary action system installed in a vehicle uses this database, or a database derived therefrom, in combination with a positioning system to determine when the vehicle is at a location that corresponds to the location of a precautionary action. When the vehicle is at such a location, a precautionary action is taken by a vehicle system as the vehicle is approaching a blind intersection.

Dive computers in accordance with embodiments of the invention are disclosed that store information concerning a dive site. The stored information can be accessed during the dive to provide information concerning such things as points of interest and/or hazards. One embodiment of the invention includes a processor, memory connected to the processor, a pressure transducer connected to the processor and configured to measure depth, and a display connected to the processor. In addition, the memory contains factual information concerning a dive site, and the processor is configured to display at least a portion of the stored factual information concerning the dive site via the display.

Navigation systems and associated methods for providing navigation services are provided. Information associated with a desired route for a vehicle, such as a route between a current location and a desired destination, may be determined. Additionally, contextual information associated with the vehicle may be identified. Based upon the desired route and the contextual information, a direction may be generated for presentation to one or more users, and the generated direction may be output for presentation.

A method for illustrating an aircraft flight plan comprising at least one waypoint on a flight display of a flight deck of an aircraft, where the method may include displaying on the flight display of the flight deck some type of display indicia that indicates the suitability of locations for future waypoints.

According to a map display device, from current location information acquired by a current location acquiring unit 6 and boundary coordinate information in time zone information acquired by a time zone information acquiring unit 22, it is determined whether or not a vehicle 9 is located within a set area which is provided in the range of a predetermined distance from a boundary of a time zone to which a current location of the vehicle 9 belongs, and if it is determined that the vehicle 9 is located within the set area, a display unit 3 displays distinctively the time zone to which the current location of the vehicle 9 belongs and a time zone which is adjacent to the corresponding time zone through the set area.

Traffic information readings corresponding to a vehicle are received, the readings including at least a location. The traffic information readings are compared to information already within a map database, and are used to derive additional map information augmenting or correcting that already within the database, the additional map information subsequently being stored in the database. Additional information that is derived includes the presence of stop signs and traffic lights at intersections, the legality of turns at certain times of day, and the connectedness or non-connectedness of road segments.

A navigation system having a central device which uses a link shape compression unit to compress information of altitude changes of a road link obtained from a three-dimensional road map, and calculates a geometry parameter based on variation of energy of a vehicle travelling on the road link. An on-board terminal device estimates the vehicle's average travelling pattern by using a travel-pattern-estimation unit based on the geometry parameter calculated by the central device, a link-travelling time estimated from statistically-stored traffic information, and a link length. The on-board terminal device further calculates fuel consumption of the vehicle travelling on each road link based on the estimated travelling pattern and parameters of the vehicle by using a fuel-consumption calculation unit, and then, searches a fuel-efficient route by using the fuel consumption as a link cost. The on-board terminal device has a vehicle-type selector for selecting a type of the vehicle.

A navigation system may calculate a route to a destination and output guidance information with an output device to guide a user of the navigation system along the calculated route. If it is determined that a navigation device has left the calculated route, the navigation system may prompt the user asking whether output of guidance information should be suspended. If the output of guidance information should be suspended, the navigation system may suspend the output of guidance information and calculate a new route to the destination while the output of guidance information is suspended. The navigation system may calculate an estimated arrival time at the destination based on the calculated new route and output the estimated arrival time while the output of guidance information is suspended.

The invention relates to compressed data transmission in wireless data communication. Disclosed are methods and apparatuses for transporting residue of vehicle position data via a wireless network. A disclosed method for transporting residue of vehicle position data via a wireless network, includes the steps of: receiving data for updating residue encoding schema from a monitoring server; constructing a residue encoding schema based on the data, thereby producing a constructed residue encoding schema; and storing the constructed residue encoding schema such that the constructed residue encoding schema will become the current residue encoding schema; where: the constructed residue encoding schema is constructed such that each residue of the constructed residue encoding schema corresponds to a code; and the constructed residue encoding schema is constructed such that a residue having a relatively high probability of occurrence corresponds to a code of relatively short length.

An automated process uses a local positioning system to acquire location (i.e., position and orientation) data for one or more movable target objects. In cases where the target objects have the capability to move under computer control, this automated process can use the measured location data to control the position and orientation of such target objects. The system leverages the measurement and image capture capability of the local positioning system, and integrates controllable marker lights, image processing, and coordinate transformation computation to provide tracking information for vehicle location control. The resulting system enables position and orientation tracking of objects in a reference coordinate system.

A method of operation of a navigation system includes: receiving an origin and a destination; receiving a route keyword for routing between the origin and the destination; identifying a via point matching the route keyword; calculating a keyword group locale based on the via point within a group distance threshold from a keyword group center; and calculating a travel route from the origin to the destination traversing the keyword group locale for displaying on a device.

A navigation system and various methods of using the system are described herein. Search query results are refined by the system and are prioritized based at least in part upon sub-search categories selected during the searching process. Sub-searches can be represented by graphical icons displayed on the user interface.

Some embodiments provide a mapping application that provides routing information to third-party applications on a device. The mapping application receives route data that includes first and second locations. Based on the route data, the mapping application provides a set of routing applications that provide navigation information. The mapping application receives a selection of a routing application in the set of routing applications. The mapping application passes the route data to the selected routing application in order for the routing application to provide navigation information.

Provided are an apparatus and method of providing path information based on a status of a path and/or a purpose of the use of the path. A path information providing server collects environmental information from a sensing device. The path information providing server receives a path information request including a departure and a destination from a terminal device, and provides path information generated by mapping environmental data to a searched path.

Various methods, apparatuses and/or articles of manufacture are provided which may be implemented to estimate a trajectory of a mobile device within an indoor environment. In some embodiments, the trajectory may be estimated without the use of any signal-based positioning information. For example, a mobile device may estimate such a trajectory based, at least in part, on one or more sensor measurements obtained at the mobile device, and further affect the estimated trajectory based, at least in part, on one or more objects identified in an electronic map of the indoor environment.

A vehicle notification sound emitting apparatus is basically provided with a first sound emitting device, a second sound emitting device and a notification sound control device. The first sound emitting device emits a first intermittent notification sound inside a cabin interior of a vehicle. The second sound emitting device emits a second intermittent notification sound outside of the cabin interior of the vehicle. The notification sound control device operates the first and second sound emitting devices to separately emit the first and second intermittent notification sounds in at least a partially overlapping pattern in response to occurrence of a vehicle condition to convey a same type of vehicle information to both inside and outside of the cabin interior of the vehicle. The notification sound control device includes a cabin interior-exterior notification sound synchronizing section that is configured to synchronize the first and second intermittent notification sounds.

Vehicle event recorder systems are arranged to be in constant communication with remote servers and administrators via mobile wireless cellular networks. Vehicle event recorders equipped with video cameras capture video and other data records of important events relating to vehicle use. These data are then transmitted over special communications networks having very high coverage space but limited bandwidth. A vehicle may be operated over very large region while maintaining continuous communications connections with a remote fixed server. As such, systems of these inventions may be characterized as including a mobile unit having: a video camera; a microprocessor; memory; an event trigger; and mobile wireless transceivers, and a fixed network portion including: mobile wireless cellular network, a protocol translation gateway, the Internet and an application-specific server.

A traction control system in vehicle comprises a detector for detecting a monitored value which changes according to a degree of a drive wheel slip; a condition determiner for determining whether or not the monitored value meets a control start condition and whether or not the monitored value meets a control termination condition; and a controller for executing traction control to reduce a driving power of the drive wheel during a period of time from when the condition determiner determines that the monitored value meets the control start condition until the condition determiner determines that the monitored value meets the control termination condition; the condition determiner being configured to set at least the control start condition variably based on a slip determination factor which changes according to a vehicle state and such that the control start condition changes more greatly according to the vehicle state than the control termination condition.

A method of patterning a plurality of layers of a work piece in a series of writing cycles in one or a plurality of write machines, the workpiece being deviced to have a number of N layers and layers of the workpiece having one or a plurality of boundary condition(s) for pattern position, the method comprising the steps of: determining the boundary conditions of layers 1 to N, calculating deviations due to the boundary conditions and calculating a compensation for the deviation of the first transformation added with the assigned part of the deviation due to the boundary conditions.

This disclosure relates generally to field-programmable gate arrays (FPGAs). Some implementations relate to methods and systems for transmitting and integrating an intellectual property (IP) block with another user's design. The IP developer can design the IP block to include both a secret portion and a public portion. The IP block developer can send or otherwise provide the IP block to another IP user without disclosing the functional description of the secret portion of the IP block. In some implementations, the IP developer provides the public portion to the IP user at the register-transfer-level (RTL) level, as a hardware description language (HDL)-implemented design, or as a synthesizable netlist. In some implementations, the IP developer provides the secret portion of the IP block to the user in the form of programming bits without providing an HDL, RTL, or netlist implementation of the secret portion.

A plurality of Field Programmable Gate Arrays (FPGA), high performance transceivers, and memory devices provide a verification module for timing and state debugging of electronic circuit designs. Signal value compression circuits and gigabit transceivers embedded in each FPGA increase the fanout of each FPGA. Ethernet communication ports enable remote software debugging of processor instructions.

A method, a system and a computer readable medium for providing information relating to a verification of a digital circuit. The verification may be formal verification and comprise formally verifying that a plurality of formal properties is valid for a representation of the digital circuit. The method comprises replacing at least a first input value relating to the representation of the digital circuit by a first free variable, determining if at least one of the plurality of formal properties is valid or invalid after replacing the first input value by the first variable and indicating if the at least one of the plurality of formal property is valid or invalid. The use of a free or open variable that has not determined value can be directly in the description or representation of the digital circuit. It is not necessary to insert errors or to apply an error model.

Methods are provided to facilitate automated creation and management of design rule checking or DRC waiver descriptions. Embodiments include receiving a plurality of first checksums corresponding to respective first geometric element violations waived in association with a block of an integrated circuit design, the first checksums being based on a first version of at least one design verification rule and/or of the block, receiving a second checksum corresponding to a second geometric element violation associated with the block, the second checksum being based on a second version of the design verification rule and/or of the block, determining whether the second checksum corresponds to at least one of the first checksums, and, if the second checksum does not correspond to at least one first checksum, generating a waiver request for the second geometric element error.

A system, method, and computer program product for automatically generating equivalent assertions in different forms for different verification tools, which may be analog or digital. A user submits a set of logic assertions that, if unclocked, are converted to clocked assertions by generating and skewing clocks to ensure simulator uniformity. A stimulus is generated, perhaps at random, or input. A test bench is either input or synthesized. For each verification tool, the test bench is simulated and simulation results are captured. An assertion status difference engine evaluates result differences between the verification tools, and identifies and outputs differences indicating a significant inconsistency. Errors in verification tool implementation and user assertion coding can be detected. The simulators used may include SPICE and Verilog, or any other simulators that differ in type, simulation algorithm, input format, or vendor implementation.

A method of asymmetric asynchronous decoupling of capacitors in an integrated circuit design is provided for faster simulation by circuit simulators, e.g. FastSPICE circuit simulators. This method includes removing a coupling capacitor from a list, which includes coupling capacitors that capacitively couple two nets in the design. The two nets have capacitances C1 and C2, and at least one of capacitances C1 and C2 exceeds a threshold. The coupling capacitor has capacitance Cc. When coupling capacitance Cc is low and only one of capacitances C1 and C2 has a low capacitance, then a forward capacitance can be used at whichever of the two nets has the low capacitance and a lump capacitance can be used at the other net for simulation. When coupling capacitance Cc is low and both of capacitances C1 and C2 have high capacitances, then lump capacitances can be used at the two nets for the simulation.

A method includes providing a design of a semiconductor device such as a stacked CMOS device comprising a plurality of circuit elements to be assigned into a layout of a plurality of tiers, and identifying at least one first type of circuit element within the plurality of circuit elements based on at least one predetermined criterion. Each respective one of the at least one first type of circuit element is to be assigned to a respective designated one of the plurality of tiers. The method further includes dividing the remainder of the plurality of circuit elements into at least two groups of circuit elements based on circuit density, and assigning the at least one first type of circuit element and the at least two groups of circuit elements to respectively different ones of the plurality of tiers of the semiconductor device.

A leakage power control vector is loaded into existing test scan chain elements for application to circuit elements of a circuit in which the leakage currents are to be controlled. The vector is designed to configure the circuit elements into states in which leakage currents are reduced. A multiplexer selects the power control vector for loading into the scan chain elements, and a clock generator clocks the configuration vector into the scan chain elements. A sleep mode detector may be provided to configure the multiplexer to select the power control vector and to operate the clock generator to clock the power control vector into the scan chain elements when a sleep mode of the circuit is detected.

A method for designing a transformer in an integrated circuit includes receiving one or more desired characteristics of the transformer from user input and iteratively determining a design solution for the transformer through one or more simulations and modifications using a rule-set. The method combines the one or more desired characteristics with other preset characteristics of the transformer or the integrated circuit. A first model of the transformer is defined with typical load impedances and simulated having the combined characteristics to determine performance. Results of the simulation are processed to calculate performance with the load impedances specified by the user. The results are further processed to obtain a mathematical model that includes tuning capacitors. The first and subsequent models are modified by drawing on a rule-set of expert knowledge relating to general dependency of at least one design criterion, such as a physical, geometrical or performance characteristic, with another design criterion.

An integrated circuit includes core logic and a plurality of interface blocks disposed about a periphery of the core logic. A plurality of input or output (I/O) circuits is assigned to one of the plurality of interface blocks. The I/O circuits include external I/O circuits coupled to a device other than the integrated circuit and internal I/O circuits coupled to the integrated circuit. Each interface block includes a first plurality of I/O circuits disposed on a first side of the interface block and a second plurality of I/O circuits disposed on a second side of the interface block. Each interface block also includes interface logic for the interface block between the first plurality of I/O circuits and the second plurality of I/O circuits, and a logic hub that includes a clock distribution of minimal length that drives launch logic and capture logic to form the I/O circuits of the interface block.

A via disposition information acquiring unit acquires via disposition information indicating a disposition of the plurality of first vias (212). A second conductor information acquiring unit acquires second conductor information indicating disposition positions of a plurality of second conductors (232) repeatedly disposed in the second conductor layer (230). A via extracting unit extracts an extraction via with respect to each of the plurality of second conductors (232). The extraction via is each of the first vias (212) overlapping the second conductor (232). A via selecting unit selects a selection via with respect to each of the plurality of second conductors (232). The selection via is each of first vias (212) selected in a predetermined number from the extraction vias. An opening introducing unit introduces a first opening (234) to each of the plurality of second conductors (232). The first opening (234) overlaps the extraction via not selected by the via selecting unit in plan view.

A method and apparatus for partitioning of the input design into repeating patterns called template cores for the application of reticle enhancement methods, design verification for manufacturability and design corrections for optical and process effects is accomplished by hierarchy analysis to extract cell overlap information. Also hierarchy analysis is performed to extract hierarchy statistics. Finally template core candidates are identified. This allows to the design to be made amenable for design corrections or other analyses or modifications that are able to leverage the hierarchy of the design since the cell hierarchy could otherwise be very deep or cells could have significant overlap with each other.

A method for mask data preparation or mask process correction is disclosed in which a set of charged particle beam shots is determined which is capable of forming a pattern on a surface, wherein critical dimension uniformity (CDU) of the pattern is optimized. In some embodiments the CDU is optimized by varying at least two factors. In other embodiments, model-based techniques are used. In yet other embodiments, the surface is a reticle to be used in an optical lithographic process to form a pattern on a wafer, and CDU on the wafer is optimized.

A method of creating a datasheet includes obtaining integrated circuit data from at least one data source, creating a data structure including the integrated circuit data obtained from the at least one data source, and creating a datasheet using data contained in the data structure. The datasheet is created in a human-readable format.

A method for accurately determining the shape of currents in a current spectrum for a circuit design is provided. The method includes determining timing and power consumption characteristics. In one embodiment, timing characteristics are provided through a electronic design automation tool. The timing characteristics yield a current pulse time width. In another embodiment, power consumption characteristics are provided by an EDA tool. The power consumption characteristics yield a current pulse amplitude. The shape of the current pulse is obtained by incrementally processing a power analyzer tool over relatively small time increments over one or more clock cycles while capturing the switching nodes of a simulation of the circuit design for each time increment. In one embodiment, the time increments are one nanosecond or less.

A system, method, and computer program product for containing analog verification IP for circuit simulation. Embodiments introduce analog verification units (“vunits”), and corresponding analog verification files to contain them. Vunits allow circuit design verification requirement specification via text file. No editing of netlist files containing design IP is required to implement static and dynamic circuit checks, PSL assertions, clock statements, or legacy assertions. Vunits reference a top-level circuit or subcircuits (by name or by specific instance), and the simulator automatically binds vunit contents appropriately during circuit hierarchy expansion. Vunits may be re-used for other design cells, and may be easily processed by text-based design tools. Vunits may be provided via vunit_include statements in a control netlist file, command line arguments, or by directly placing a vunit block into a netlist. Vunits may also contain instance statements to monitor or process signals, such as those needed by assertions.

Some example embodiments include a computer-implemented method for designing an integrated circuit. The computer-implemented method includes receiving a hierarchical network design for the integrated circuit, wherein the hierarchical design comprises a number of components that are coupled together. The computer-implemented method includes detecting that a component of the number of components has at least one of failed timing and incomplete timing based on a problem that comprises at least one of a missing assertion, one or more missing latches, a source driver having an input source slew that is greater than a source slew limit threshold, and a sink having an input sink slew that is greater than a sink slew limit threshold. The computer-implemented method includes replacing the component with a different component that is independent of the problem and testing others components of the number of components based on the different component.

A method, an apparatus, and a computer program product for wireless communication are provided. The apparatus generates a plurality of interconnect patterns for a set of longitudinal channels that are occupied by horizontal interconnects. Each interconnect pattern may be different from the other interconnect patterns. Each interconnect pattern may define relative locations for the set of horizontal interconnects and gap channels. Highest crosstalk is determined for each of the interconnect patterns and the interconnect pattern with the minimum highest crosstalk is selected as a preferred pattern. The highest crosstalk may comprise far-end crosstalk or near-end crosstalk and may be calculated for a range of frequencies or for a plurality of frequencies. The crosstalk may be calculated by modeling the interconnects as transmission lines.

Methods and systems for managing data loads on a cluster of processors that implement an iterative procedure through parallel processing of data for the procedure are disclosed. One method includes monitoring, for at least one iteration of the procedure, completion times of a plurality of different processing phases that are undergone by each of the processors in a given iteration. The method further includes determining whether a load imbalance factor threshold is exceeded in the given iteration based on the completion times for the given iteration. In addition, the data is repartitioned by reassigning the data to the processors based on predicted dependencies between assigned data units of the data and completion times of a plurality of the processers for at least two of the phases. Further, the parallel processing is implemented on the cluster of processors in accordance with the reassignment.

A method of forming a magnetic tunnel junction (MTJ) device includes forming a first MTJ cap layer on a MTJ structure. The first MTJ cap layer includes a first non-nitrified metal. The method also includes forming a second MTJ cap layer over the first MTJ cap layer. The second MTJ cap layer includes a second non-nitrified metal. The method further includes forming a top electrode layer over the second MTJ cap layer. The second MTJ cap layer is conductive and configured to reduce or prevent oxidation.

In one embodiment of the invention, an integrated circuit (IC) design tool is provided for synthesizing logic, including one or more software modules to synthesize a gate-level netlist of a squarer functional block. The software modules include a bitvector generator, a bitvector reducer, and a hybrid multibit adder generator. The bitvector generator multiplies bits of a vector together to generate partial products for a plurality of bitvectors and then optimizes a plurality of least significant bitvectors. The bitvector reducer reduces the partial products in the bitvectors of the squarer functional block down to a pair of final vectors. The hybrid multibit adder generator generates a hybrid multibit adder including a first adder and a second adder coupled together by a carry bit with bit widths being responsive to a dividerbit. The hybrid multibit adder adds the pair of final vectors together to generate a final result for the squarer functional block.

A technique for determining whether an integrated circuit design is susceptible to glitches includes identifying storage elements in an original register-transfer level (RTL) file of the integrated circuit design and identifying clock signals for each of the storage elements in the original RTL file. The technique also includes generating respective assertions for each of the identified clock signals and identifying potential glitchy logic in respective clock paths for each of the identified clock signals. Finally, the technique includes inserting, at the potential glitchy logic, glitches in each of the respective clock paths of the original RTL file to provide a modified RTL file and executing an RTL simulation using the modified RTL file and the respective assertions.

A datapath extraction tool uses machine-learning models to selectively classify clusters of cells in an integrated circuit design as either datapath logic or non-datapath logic based on cluster features. A support vector machine and a neural network can be used to build compact and run-time efficient models. A cluster is classified as datapath if both the support vector machine and the neural network indicate that it is datapath-like. The cluster features may include automorphism generators for the cell clusters, or physical information based on the cell locations from a previous (e.g., global) placement, such as a ratio of a total cell area for a given cluster to a half-perimeter of a bounding box for the given cluster.

Methods and systems are described for placing arithmetic operators on a programmable integrated circuit device (e.g., a PLD). Placement of arithmetic operators of a data flow graph in one of multiple regions (e.g., a region of DSP circuitry blocks or a region of logic fabric circuitry) on the programmable integrated circuitry device may be determined (e.g., randomly). A score related to the performance of the graph (e.g., a score related to data flow graph routing delays or area consumed by the data flow graph) may be determined and this process may be repeated after one of the arithmetic operators of the data flow graph is moved. The placement of arithmetic operators that corresponds to the best value for the score related to the performance of the data flow graph may be stored. Accordingly, more arithmetic operators may be included on a programmable integrated device than in conventional devices.

A magnetic tunneling junction device and fabrication method is disclosed. In a particular embodiment, a non-transitory computer-readable medium includes processor executable instructions. The instructions, when executed by a processor, cause the processor to initiate deposition of a capping material on a free layer of a magnetic tunneling junction structure to form a capping layer. The instructions, when executed by the processor, cause the processor to initiate oxidization of a first layer of the capping material to form a first oxidized layer of oxidized material.