Newport --

DelDOT announces to motorists that their contractor will be closing Route 141 Northbound at Exit 3A and Ramps on Friday, May 15, 2020 and Saturday, May 16, 2020 for the installation of the waterline and repairs to the ramps. In the event of inclement weather on Friday, the closures will start on Saturday, May 16, 2020 at 8:00 p.m. until 9:00 p.m. on Sunday, May 17, 2020.

The following closures will occur at 8:00 p.m. on Friday, May 15, 2020 until 9:00 p.m. on Saturday, May 16, 2020

Route 141 Northbound at Exit 3A/I-95 Northbound

Exit 5B/I-95 Northbound to Route 141 Northbound

Exit 3B/Route 141 Northbound to I-95 Southbound

Exit 5B/I-95 Southbound to Route 141 Northbound

Exit 5/I-295 Southbound to Route 141 Northbound

Detour Routes:

Detour Route for Route 141 Northbound to Exit 3A/I-95 Northbound

Motorists will take the ramp from Route 141 northbound to I-95 northbound and take the ramp to Route 4 and continue straight onto Adams Street. [More]

Wilmington --

The Delaware Department of Transportation (DelDOT) announces to motorists that this project will begin on Monday, May 18, 2020. Motorists can anticipate daytime lane and shoulder closure on weekdays from 7:00 a.m. until 4:00 p.m. on Route 48/Lancaster Pike and Lancaster Avenue.

This project will improve the Pedestrian Accessible Route (PAR) and sidewalk connections along Lancaster Pike from West Court Drive to DuPont Road. [More]

DOVER, Del. – The Polly Drummond Hill yard waste drop-off site near Newark, which opened for the season on Saturday, April 18, was closed to further drop-offs about noon on Sunday because of material capacity and traffic issues. DNREC will work this week to have its contractor shred and remove all the material that was dropped off until the closure, and create a traffic plan with the goal of reopening the site on Saturday, April 25. The site operates Saturdays and Sundays.

A group of Superior Court judgments issued on April 22 impose a total of $6.79 million in civil penalties against a Middletown pawn shop and its operators for violations of Delaware’s racketeering statute. The Department of Justice’s Civil Division secured the judgment as the outcome of a 2017 civil racketeering complaint filed against Gold Fever […]

January serves as National Slavery and Human Trafficking Awareness Month, culminating in the annual observation of National Freedom Day on February 1. For many, this month presents an opportunity to refocus efforts to slow, and ultimately stop, human trafficking around the globe, but especially here in the United States. The [...]

The post Analytics can help combat the horrors of human trafficking appeared first on Government Data Connection.

An internet diversion that rerouted data traffic through Russia and China disrupted several Google services on Monday, including search and cloud-hosting services.

It has been over 16 year since Harold D'Souza arrived in the United States. He wanted to build a better life for himself and his family in the land of opportunities. Instead, Mr D'Souza ended up...

A bridge in China was temporarily closed to public after it was filmed swaying up and down because of strong winds.

Modern systems-on-a-chip (SoCs) continue to increase in complexity, adding more components and calculation power to accommodate new performance-hungry applications such as machine learning and autonomous driving.  With increased number of SoC components, such as CPUs, GPUs, accelerators and I/O devices, comes increased demand to correctly model interoperability of various components. Traditional simulation of complex systems requires accurate models of all components comprising the system and normally results in very long simulation times. A better way is to create a set of typical traffic profiles which describe behavior of system’s masters and slaves. Such profiles should be abstract to be applied to various protocols and interfaces and be portable to be applied throughout different SoC design and verification cycles.

To address the challenges outlined above, Arm has recently announced availability of the AMBA® Adaptive Traffic Profiles (AMBA ATP) specification which lays foundation of a new synthetic traffic framework. The AMBA ATP specification includes detailed information of various transaction types and timing characteristics of those transactions. The traffic profiles defined in the specification are abstract in nature and thus could be used to generate stimuli for various standard AMBA protocols and in various environments such as RTL-based simulation, FPGA prototyping and final SoC verification. The traffic profiles outlined in the specification include a set of parameters to define timing relationships between transactions as well as timing relationships within individual transactions. Even though the traffic profile represents the behavior of a single agent it could be applied either in a concurrent manner (e.g. write and read traffic profiles running in parallel) or in a sequential manner (e.g. when one traffic completes before the next one start). Moreover, when simulating a reasonably complex system, it is possible to coordinate traffic profiles generated by multiple components. While providing abstract definition of traffic profiles, the AMBA ATP specification focuses on the use of traffic profiles with an AMBA AXI interface, outlining signaling, timing relationships between different transaction phases and between different transactions. The same application principles could be used to map the abstract traffic profiles to other AMBA protocols such as AMBA5 CHI protocol.  

To facilitate adoption of the AMBA Adaptive Traffic Profiles, Cadence has recently announced availability of SystemVerilog UVM ATP Sequence Layer which automatically implements mapping of an abstract ATP traffic to AMBA protocol specific traffic, generated by Cadence AMBA Verification IP. The ATP layer is implemented as a SystemVerilog UVM virtual sequence with the sequence item including all ATP transaction parameters as defined in the specification.

Using the provided sequence infrastructure, users can write tests to define and coordinate traffic profiles for various components in the system. The ATP Layer automatically converts the abstract traffic profile into AMBA protocol-specific traffic, e.g., AMBA5 CHI protocol traffic.

 A sample code below, shows an example of a read profile translated by Cadence ACE Verification IP in ACE protocol traffic.

   `uvm_do_with(ace_atp_vseq,                                            

                       {ace_atp_vseq.agentId == agent_id;                                // ATP agent id

                        ace_atp_vseq.atpDirection == ATP_READ;                    // direction of bursts issued by virtual sequence

                        ace_atp_vseq.startAddress == start_address;                // start of address range being accessed

                        ace_atp_vseq.endAddress == end_address;                  // end of address range being accessed

                        ace_atp_vseq.atpDomain == atp_domain;                      // domain to use for transactions

                        ace_atp_vseq.addressPattern == ATP_SEQUENTIAL;  // address pattern

                        ace_atp_vseq.transactionSize == 64;                             // number of bytes in each burst

                        ace_atp_vseq.dataSize == 4;                                          // number of bytes in each transfer

                        ace_atp_vseq.rate == 150.0/(50.0);                                // requestedBandwidth / clkFrequency

                        ace_atp_vseq.start == ATP_EMPTY;                              // start condition of the ATP FIFO

                        ace_atp_vseq.full == 128;                                               // full level of the ATP FIFO

                        ace_atp_vseq.numOfTransactions == 500;                    // number of bursts issued by this sequence

                        ace_atp_vseq.ARTV == 2;                                              // sub-transaction delay

                        ace_atp_vseq.RBR == 3;                                                // sub-transaction delay

                       });

In addition to the ATP Layer for Cadence Simulation-Based AMBA Verification IP, Cadence supports the ATP functionality in Acceleration-Based AMBA Verification IP. For detailed information about ATP support in Cadence Simulation-Based and Acceleration-Based Verification IP, visit ip.cadence.com.

USB4 can simultaneously tunnel USB3, PCIe and DisplayPort native protocol traffic through a hierarchy of USB4 routers. The key to tunneling of these protocols is routing table programmed at each ingress adapter. An entry of a routing table maps an incoming HopID, called Input/Ingress HopID to a corresponding pair of Output/Egress Adapter and Egress/Output HopID.

The responsibility of programming routing tables lies with the Connection Manager. Connection Manager, having the complete view of the hierarchy of the routers, programs the routing tables at all relevant adapter ports. Accordingly, the USB3, PCIe and DisplayPort protocol tunneled packets are routed, and reach their respective intended destinations.

The diagrammatic representation below is an example of tunneling of USB3 protocol traffic from USB4 Host Router to USB4 Peripheral Device Router through a USB4 Hub Router. The path from USB3 Host to USB3 Device is depicted by routing tables indicated at A -> B -> C -> D, and the one from USB3 Device to USB3 Host by routing tables indicated at E -> F -> G -> H . Note that the Input HopID from and Output HopID to all three protocol adapters for USB3, PCIe and DisplayPort Aux traffic, are fixed as 8, and for DisplayPort Main Link traffic are fixed as 9.

Once the native protocol traffic come into the transport layer of a USB4 router, the transport layer of it does not know to which native protocol a tunneled packet belongs to. The only way a transport layer tunneled packet is routed through the hierarchy of the routers is using the HopID values and the information programmed in the routing tables.

The figure below shows an example of tunneling of all the three USB3, PCIe and DisplayPort protocol traffic together. The transport layer tunneled packets of each of these native protocols are transported simultaneously through the routers hierarchy.

 Cadence has a mature Verification IP solution for the verification of USB3, PCIe and DisplayPort tunneling. This solution also employs the industry proven VIPs of each of these native protocols for native USB3, PCIe and DisplayPort traffic.

Estimated traffic fatalities decreased in 2019 despite an increase in driving, according to a report from the NHTSA released on Wednesday. There were projected to be 36,120 traffic fatalities in 2019, which is a 1.2% decrease from 2018. It marks the third consecutive year of declines from a post-recession high point of 37,806 traffic fatalities in...

New law requiring vehicles to have license plates led to traffic fine bonanza.