A system and method for controlling a load on an agricultural harvester (100) comprising a first sensor (124, 126, 128, 130) to sense a first load, a second sensor (132, 134, 136, 138) to sense a second load, an electronic control unit (200) coupled to the first sensor and the second sensor, the electronic control unit (200) being configured to determine a difference between the first load and the second load, and to either (a) raise a harvesting head (102) or (b) stop the agricultural harvester (100), or (c) both, when the difference exceeds a threshold load.

A harvesting system and method providing a row insensitive plant cutting and gathering capability, suitable for harvesting tall, stalky plants such as sweet sorghum, cane, and the like, in high volume, which also billet cuts the harvested plants. Multiple plants are cut simultaneously on a continuous basis at any locations across a header of the system, and the cut plants are gathered into a continuous overlapping flow having a vertical extent or thickness of several stalks or canes and their associated foliage. The flow is then vertically compacted into a mat of reduced thickness while being conveyed into a billet cutter, which cuts the stalks or canes into billets of a desired length and discharges the billets to a desired location, all while the harvester is moving through a field harvesting. The system can be incorporated into a conventional sugarcane harvester in place of conventional base cutters and row dividers.

The present invention provides a method for measuring reflective intensity of display surface, including: obtaining a luminance value of a first display and a luminance value of a second display when displaying, the first display and the second display having the same observed luminance, the peripheral of the surface of the first display being surrounded by light-shielding object, the first display and the second display being placed side by side; and obtaining the reflective intensity of the display surface in the ambient based on the luminance value of the first display and the luminance values of the second display when displaying. As such, the present invention provides convenient and accurate means to measure the reflective intensity of display surface.

A combine harvester is provided that separates grain material from material other than grain using multiple processing areas, including a harvesting area, a feederhouse area, a threshing area, a cleaning area, and a grain delivery area. In a location at or prior to entering one of the processing areas, the material may be collected and held until a collection threshold is reached. Once it is determined that the collection threshold is reached, the material forming a first group of material may be transported from the location to the processing area or a subsequent processing area. The first group of material is transported from the location to the processing area or the subsequent processing area substantially simultaneously and thus simulates the gathering of a large amount of crop material even when small plots are involved. In this way, reduced cycle times may be achieved, and the efficiency benefits of large-plot harvesting may be extended to small-plot applications.

A corn header has a row unit frame and an auger sweeping ears of corn toward a center of the corn header. A corn row divider assembly has a snout and gatherer hood hingeably coupled to, and aft of, the snout. An aft end of the gatherer hood is located beneath and to the rear of the fore end of the auger in an operational configuration of the divider assembly. The divider assembly further has a four-point hinge assembly coupling the aft end of the gatherer hood to the row unit frame. The four-point hinge assembly is configured to pivot the gatherer hood between the operational configuration and a non-operational configuration in which the gatherer hood is in a raised condition. The four-point hinge assembly moves the aft end of the gatherer hood forward so that the gatherer hood clears the auger when pivoting to the non-operational configuration.

A rotary implement includes a metallic body that is rotatable around an axis. The metallic body includes a tapered leading edge having an interface surface and an opposite, free surface. The metallic body has a first composition. A metallic layer has a first side surface that is attached to the interface surface and a free, second side surface opposite from the first side surface. The metallic layer has a second, different composition from the first composition. A rotary machine can include an actuator and the rotary implement operably coupled to the actuator. A method for making a rotary implement includes providing the metallic body that has the tapered leading edge having the interface surface and the opposite, free surface. The metallic layer is then attached to the interface surface of the metallic body.

Disclosed herein is a wafer processing method including a processed position measuring step of imaging an area including a beam plasma generated by applying a pulsed laser beam to a wafer, by using an imaging unit during the formation of a laser processed groove on the wafer, and next measuring the positional relation between the position of the beam plasma and a preset processing position. Accordingly, it is possible to check whether or not the laser processed groove is formed at a desired position, in real time during laser processing. If the position of the laser processed groove is deviated, the processed position can be immediately corrected.

A semiconductor device has a plurality of semiconductor die. A first prefabricated insulating film is disposed over the semiconductor die. A conductive layer is formed over the first prefabricated insulating film. An interconnect structure is formed over the semiconductor die and first prefabricated insulating film. The first prefabricated insulating film is laminated over the semiconductor die. The first prefabricated insulating film includes glass cloth, glass fiber, or glass fillers. The semiconductor die is embedded within the first prefabricated insulating film with the first prefabricated insulating film covering first and side surfaces of the semiconductor die. The interconnect structure is formed over a second surface of the semiconductor die opposite the first surface. A portion of the first prefabricated insulating film is removed after disposing the first prefabricated insulating film over the semiconductor die. A second prefabricated insulating film is disposed over the first prefabricated insulating film.

A method of making a semiconductor device can include providing a wafer comprising a plurality of semiconductor die, wherein each semiconductor die comprises an active surface and a backside opposite the active surface. A photosensitive layer can be formed over the wafer and on a backside of each of the plurality of semiconductor die within the wafer with a coating machine. An identifying mark can be formed within the photosensitive layer for each of the plurality of semiconductor die with a digital exposure machine and a developer, wherein a thickness of the identifying mark is less than or equal to 50 percent of a thickness of the photosensitive layer. The photosensitive layer can be cured. The wafer can be singulated into a plurality of semiconductor devices.

A semiconductor package is provided, including: an insulating base body having a first surface with an opening and a second surface opposite to the first surface; an insulating extending body extending outward from an edge of the first surface of the insulating base body, wherein the insulating extending body is less in thickness than the insulating base body; an electronic element having opposite active and inactive surfaces and disposed in the opening with its inactive surface facing the insulating base body; a dielectric layer formed in the opening of the insulating base body and on the first surface of the insulating base body, the insulating extending body and the active surface of the electronic element; and a circuit layer formed on the dielectric layer and electrically connected to the electronic element. The configuration of the insulating layer of the invention facilitates to enhance the overall structural rigidity of the package.

A semiconductor device includes a first moisture-resistant ring disposed in a peripheral region surrounding a circuit region on a semiconductor substrate in such a way as to surround the circuit region and a second moisture-resistant ring disposed in the peripheral region in such a way as to surround the first moisture-resistant ring.

A manufacturing method of a package substrate is provided. The method includes forming a first circuit layer on a carrier. A passive component is disposed on the first circuit layer and the carrier. A dielectric layer is formed on the carrier to embed the passive component and the first circuit layer in the dielectric layer. A second circuit layer is formed on the dielectric layer. The carrier is removed from the dielectric layer. A manufacturing method of a chip package is also provided.

Presented herein are an interconnect structure and method for forming the same. The interconnect structure includes a contact pad disposed over a substrate and a connector disposed over the substrate and spaced apart from the contact pad. A passivation layer is disposed over the contact pad and over connector, the passivation layer having a contact pad opening, a connector opening, and a mounting pad opening. A post passivation layer including a trace and a mounting pad is disposed over the passivation layer. The trace may be disposed in the contact pad opening and contacting the mounting pad, and further disposed in the connector opening and contacting the connector. The mounting pad may be disposed in the mounting pad opening and contacting the opening. The mounting pad may be separated from the trace by a trace gap, which may optionally be at least 10 μm.

A method for wafer-level packaging includes providing a substrate having a conductive metal pad formed on the surface of the substrate; forming a metal core on the top of the conductive metal pad with the metal core protruding from the surface of the substrate; then, forming an under bump metal layer on the top surface and the side surface of the metal core; and finally, forming a bump structure on the top of the under bump metal layer.

A semiconductor mounting apparatus includes a storing unit that stores a liquid or a gas, a contact unit that comes into contact with a semiconductor chip when the storing unit is filled with the liquid or the gas, and a sucking unit that sucks up the semiconductor chip to bring the semiconductor chip into close contact with the contact unit.

A method of ultrasonically bonding semiconductor elements includes the steps of: (a) aligning surfaces of a plurality of first conductive structures of a first semiconductor element to respective surfaces of a plurality of second conductive structures of a second semiconductor element; (b) ultrasonically forming tack bonds between ones of the first conductive structures and respective ones of the second conductive structures; and (c) forming completed bonds between the first conductive structures and the second conductive structures.

A semiconductor device includes a substrate comprising a trench; a gate dielectric layer formed over a surface of the trench; a gate electrode positioned at a level lower than a top surface of the substrate, and comprising a lower buried portion embedded in a lower portion of the trench over the gate dielectric layer and an upper buried portion positioned over the lower buried portion; and a dielectric work function adjusting liner positioned between the lower buried portion and the gate dielectric layer; and a dipole formed between the dielectric work function adjusting liner and the gate dielectric layer.

A method of forming a ferroelectric memory cell. The method comprises forming an electrode material exhibiting a desired dominant crystallographic orientation. A hafnium-based material is formed over the electrode material and the hafnium-based material is crystallized to induce formation of a ferroelectric material having a desired crystallographic orientation. Additional methods are also described, as are semiconductor device structures including the ferroelectric material.

Embodiments of the inventive concepts provide a method for manufacturing a semiconductor device. The method includes forming a stack structure including insulating layers and sacrificial layers which are alternately and repeatedly stacked on a substrate. A first photoresist pattern is formed on the stack structure. A first part of the stack structure is etched to form a stepwise structure using the first photoresist pattern as an etch mask. The first photoresist pattern includes a copolymer including a plurality of units represented by at least one of the following chemical formulas 1 to 3, wherein “R1”, “R2”, “R3”, “p”, “q” and “r” are the same as defined in the description.

A performance of a semiconductor device is improved. A film, which is made of silicon, is formed in a resistance element formation region on a semiconductor substrate, and an impurity, which is at least one type of elements selected from a group including a group 14 element and a group 18 element, is ion-implanted into the film, and a film portion which is formed of the film of a portion into which the impurity is ion-implanted is formed. Next, an insulating film with a charge storage portion therein is formed in a memory formation region on the semiconductor substrate, and a conductive film is formed on the insulating film.

A method of manufacturing a semiconductor device according to one embodiment includes forming a first film including a first metal above a processing target member. The method includes forming a second film including two or more types of element out of a second metal, carbon, and boron above the first film. The method includes forming a third film including the first metal above the second film. The method includes forming a mask film by providing an opening part to a stacked film including the first film, the second film and the third film. The method includes processing the processing target member by performing etching using the mask film as a mask.

Embodiments of the inventive concept provide a method for manufacturing a semiconductor device. The method includes forming a stack structure by alternately and repeatedly stacking insulating layers and sacrificial layers on a substrate, sequentially forming a first lower layer and a first photoresist pattern on the stack structure, etching the first lower layer using the first photoresist pattern as an etch mask to form a first lower pattern. A first part of the stack structure is etched to form a stepwise structure using the first lower pattern as an etch mask. The first lower layer includes a novolac-based organic polymer, and the first photoresist pattern includes a polymer including silicon.

The present invention provides a method for manufacturing the N-type TFT, which includes subjecting a light shielding layer to a grating like patternization treatment for controlling different zones of a poly-silicon layer to induce difference of crystallization so as to have different zones of the poly-silicon layer forming crystalline grains having different sizes, whereby through just one operation of ion doping, different zones of the poly-silicon layer have differences in electrical resistivity due to difference of grain size generated under the condition of identical doping concentration to provide an effect equivalent to an LDD structure for providing the TFT with a relatively low leakage current and improved reliability. Further, since only one operation of ion injection is involved, the manufacturing time and manufacturing cost can be saved, damages of the poly-silicon layer can be reduced, the activation time can be shortened, thereby facilitating the manufacture of flexible display devices.

A method of manufacturing a thin film transistor is disclosed. The method of manufacturing the thin film transistor includes: manufacturing a substrate; forming an oxide semiconductor layer on the substrate; forming a pattern including an active layer through a patterning process; forming a source and drain metal layer on the active layer; and forming a pattern including a source electrode and a drain electrode through a patterning process, an opening being formed between the source electrode and the drain electrode at a position corresponding to a region of the active layer used as a channel, wherein the step of forming the pattern including the source electrode and the drain electrode through a patterning process includes: removing a portion of the source and drain metal layer corresponding to the position of the opening through dry etching. The method may also be used to manufacturing a thin film transistor.

A method of forming image sensor packages may include performing a molding process. Mold material may be formed either on a transparent substrate in between image sensor dies, or on a removable panel in between transparent substrates attached to image sensor dies. Redistribution layers may be formed before or after the molding process. Mold material may be formed after forming redistribution layers so that the mold material covers the redistribution layers. In these cases, holes may be formed in the mold material to expose solder pads on the redistribution layers. Alternatively, redistribution layers may be formed after the molding process and the redistribution layers may extend over the mold material. Image sensor dies may be attached to a glass or notched glass substrate with dam structures. The methods of forming image sensor packages may result in hermetic image sensor packages that prevent exterior materials from reaching the image sensor.

A first photoresist pattern and a second photoresist pattern are formed over a substrate. The first photoresist pattern is separated from the second photoresist pattern by a gap. A chemical mixture is coated on the first and second photoresist patterns. The chemical mixture contains a chemical material and surfactant particles mixed into the chemical material. The chemical mixture fills the gap. A baking process is performed on the first and second photoresist patterns, the baking process causing the gap to shrink. At least some surfactant particles are disposed at sidewall boundaries of the gap. A developing process is performed on the first and second photoresist patterns. The developing process removes the chemical mixture in the gap and over the photoresist patterns. The surfactant particles disposed at sidewall boundaries of the gap reduce a capillary effect during the developing process.

A TFT and manufacturing method thereof, an array substrate and manufacturing method thereof, an X-ray detector and a display device are disclosed. The manufacturing method includes: forming a gate-insulating-layer thin film (3'), a semiconductor-layer thin film (4') and a passivation-shielding-layer thin film (5') successively; forming a pattern (5') that includes a passivation shielding layer through one patterning process, so that a portion, sheltered by the passivation shielding layer, of the semiconductor-layer thin film forms a pattern of an active layer (4a'); and performing an ion doping process to a portion, not sheltered by the passivation shielding layer, of the semiconductor-layer thin film to form a pattern comprising a source electrode (4c') and a drain electrode (4b'). The source electrode (4c') and the drain electrode (4b') are disposed on two sides of the active layer (4a') respectively and in a same layer as the active layer (4a'). The manufacturing method can reduce the number of patterning processes and improve the performance of the thin film transistor in the array substrate.

Manufacturing methods of JFET-type compact three-dimensional memory (3D-MC) are disclosed. In a memory level stacked above the substrate, an x-line extends from a memory array to an above-substrate decoding stage. A JFET-type transistor is formed on the x-line as a decoding device for the above-substrate decoding stage, where the overlap portion of the x-line with the control-line (c-line) is semi-conductive.

A method of forming a semiconductor device is provided such that a trench is formed in a semiconductor body at a first surface of the semiconductor body. Dopants are introduced into a first region at a bottom side of the trench by ion implantation. A filling material is formed in the trench. Dopants are introduced into a second region at a top side of the filling material. Thermal processing of the semiconductor body is carried out and is configured to intermix dopants from the first and the second regions by a diffusion process along a vertical direction perpendicular to the first surface.

To provide a semiconductor device having improved reliability. After formation of an n+ type semiconductor region for source/drain, a first insulating film is formed on a semiconductor substrate so as to cover a gate electrode and a sidewall spacer. After heat treatment, a second insulating film is formed on the first insulating film and a resist pattern is formed on the second insulating film. Then, these insulating films are etched with the resist pattern as an etching mask. The resist pattern is removed, followed by wet washing treatment. A metal silicide layer is then formed by the salicide process.

A method of fabricating a semiconductor device includes forming a gate strip including a dummy electrode and a TiN layer. The method includes removing a first portion of the dummy electrode to form a first opening over a P-active region and an isolation region. The method includes performing an oxygen-containing plasma treatment on a first portion of the TiN layer; and filling the first opening with a first metal material. The method includes removing a second portion of the dummy electrode to form a second opening over an N-active region and the isolation region. The method includes performing a nitrogen-containing plasma treatment on a second portion of the TiN layer; and filling the second opening with a second metal material. The second portion of the TiN layer connects to the first portion of the TiN layer over the isolation region.

A method for manufacturing an LDMOS device includes: providing a semiconductor substrate (200), forming a drift region (201) in the semiconductor substrate (200), forming a gate material layer on the semiconductor substrate (200), and forming a negative photoresist layer (204) on the gate material layer; patterning the negative photoresist layer (204), and etching the gate material layer by using the patterned negative photoresist layer (204) as a mask so as to form a gate (203); forming a photoresist layer having an opening on the semiconductor substrate (200) and the patterned negative photoresist layer (204), the opening corresponding to a predetermined position for forming a body region (206); and injecting the body region (206) by using the gate (203) and the negative photoresist layer (204) located above the gate (203) as a self-alignment layer, so as to form a channel region.

The on-state characteristics of a transistor are improved and thus, a semiconductor device capable of high-speed response and high-speed operation is provided. A highly reliable semiconductor device showing stable electric characteristics is made. The semiconductor device includes a transistor including a first oxide layer; an oxide semiconductor layer over the first oxide layer; a source electrode layer and a drain electrode layer in contact with the oxide semiconductor layer; a second oxide layer over the oxide semiconductor layer; a gate insulating layer over the second oxide layer; and a gate electrode layer over the gate insulating layer. An end portion of the second oxide layer and an end portion of the gate insulating layer overlap with the source electrode layer and the drain electrode layer.

A semiconductor structure is disclosed. The semiconductor structure includes a source trench in a drift region, the source trench having a source trench dielectric liner and a source trench conductive filler surrounded by the source trench dielectric liner, a source region in a body region over the drift region. The semiconductor structure also includes a patterned source trench dielectric cap forming an insulated portion and an exposed portion of the source trench conductive filler, and a source contact layer coupling the source region to the exposed portion of the source trench conductive filler, the insulated portion of the source trench conductive filler increasing resistance between the source contact layer and the source trench conductive filler under the patterned source trench dielectric cap. The source trench is a serpentine source trench having a plurality of parallel portions connected by a plurality of curved portions.

A method for producing an integrated power transistor circuit includes forming at least one transistor cell in a cell array, each transistor cell having a doped region formed in a semiconductor substrate and adjoining a first surface of the semiconductor substrate on a first side of the semiconductor substrate, depositing a contact layer on the first side, structuring the contact layer to form a contact structure from the contact layer, the contact structure having, in a projection of the cell array orthogonal to the first surface, a first section and, outside the cell array, a second section which connects the first section to an interface structure, and forming an electrode structure on and in direct contact with the first section in the orthogonal projection of the cell array, the electrode structure being absent outside the cell array.

A semiconductor device includes a substrate comprising a channel region and a recess, wherein the recess is located at both side of the channel region; a gate structure formed over the channel region; a first SiP layer covering bottom corners of the gate structure and the recess; and a second SiP layer formed over the first SiP layer and in the recess, wherein the second SiP layer has a phosphorus concentration higher than that of the first SiP layer.

A method of production of a semiconductor device comprising a semiconductor layer forming step of forming a semiconductor layer including an inorganic oxide semiconductor on a board, a passivation film forming step of forming a passivation film comprising an organic material so as to cover the semiconductor layer, a baking step of baking the passivation film, and a cooling step of cooling the passivation film after baking, herein, in the cooling step, a cooling speed from a baking temperature at the time of baking in the baking step to a temperature 50° C. lower than the baking temperature is substantially controlled to 0.5 to 5° C./min in range is provided.

Provided is a method for fabricating an electronic device, the method including: preparing a carrier substrate including an element region and a wiring region; forming a sacrificial layer on the carrier substrate; forming an electronic element on the sacrificial layer of the element region; forming a first elastic layer having a corrugated surface on the first elastic layer of the wiring region; forming a metal wirings electrically connecting the electronic element thereto, on the first elastic layer of the wiring region; forming a second elastic layer covering the metal wirings, on the first elastic layer; forming a high rigidity pattern filling in a recess of the second elastic layer above the electronic element so as to overlap the electronic element, and having a corrugated surface; forming a third elastic layer on the second elastic layer and the high rigidity pattern; and separating the carrier substrate.

A method is provided for making smooth crystalline semiconductor thin-films and hole and electron transport films for solar cells and other electronic devices. Such semiconductor films have an average roughness of 3.4 nm thus allowing for effective deposition of additional semiconductor film layers such as perovskites for tandem solar cell structures which require extremely smooth surfaces for high quality device fabrication.

A magnetoresistive random access memory (MRAM) structure includes a bottom electrode structure. A magnetic tunnel junction (MTJ) element is over the bottom electrode structure. The MTJ element includes an anti-ferromagnetic material layer. A ferromagnetic pinned layer is over the anti-ferromagnetic material layer. A tunneling layer is over the ferromagnetic pinned layer. A ferromagnetic free layer is over the tunneling layer. The ferromagnetic free layer has a first portion and a demagnetized second portion. The MRAM also includes a top electrode structure over the first portion.

An organic layer deposition assembly for depositing a deposition material on a substrate includes a deposition source configured to spray the deposition material, a deposition source nozzle arranged in one side of the deposition source and including deposition source nozzles arranged in a first direction, a patterning slit sheet arranged to face the deposition source nozzle and having patterning slits in a second direction that crosses the first direction, and a correction sheet arranged between the deposition source nozzle and the patterning slit sheet and configured to block at least a part of the deposition material sprayed from the deposition source.

An array substrate of organic light-emitting diodes and a method for fabricating the same are provided to narrow an edge frame of product device of organic light-emitting diodes, to shorten the package process time, and to improve the substrate utilization and the production efficiency. The array substrate of organic light-emitting diodes includes a plurality of display panels disposed in an array of rows and columns, wherein at least two adjacent display panels are connected through a frame adhesive, and there is no cutting headroom between at least one side of the at least two adjacent display panels.

One embodiment is a wide stripe semiconductor waveguide, which is cleaved at a Talbot length thereof, the wide stripe semiconductor waveguide having facets with mirror coatings. A system provides for selective pumping the wide stripe semiconductor waveguide to create and support a Talbot mode. In embodiments according to the present method and apparatus the gain is patterned so that a single unique pattern actually has the highest gain and hence it is the distribution that oscillates.

A tensioning device comprises an elongate member, preferably a band, and a frame having first and second sides. The band has a first end that is attachable to the first side of the frame and a second end that is releasably securable to the second side of the frame. A movable clamping member on the frame secures the second end of the band to the second side of the frame by cinching the second end of the band between an engagement surface on the band and a mating engagement surface on the second side of the frame. A restraining member is provided for restraining the clamping member to a first position spaced from the mating locking surface on the second side of the frame, when the restraining member is in a restraining orientation. The restraining member is movable out of the restraining orientation after the band is tensioned to a predetermined level using the second end. The band is tensioned to the aforementioned predetermined level and is secured to the second side of the frame, so that the band establishes a path of tension along its length that extends linearly between the two ends of the band.

An apparatus and method for carrying and storing a portion of rope is claimed. A portion of rope is braided and wound about two complementary loops. Attached to one complementary loop is a flexible fastener. The flexible fastener can be passed through the second complementary loop and attached to itself. The apparatus can then be worn as a bracelet. When the rope is needed, the person can unwind the rope. After using the rope, the rope can be rewound and then bound with the flexible fastener.

A mountable cable tie with fine adjustment with an elongated strap having a first strap end and a second strap end, the elongated strap having one or more rows of teeth or cross-bars formed crosswise on the elongated strap, and a plurality of holes positioned linear along the median between the one or more rows of teeth, at least one locking buckle positioned proximate the second strap end, the at least one locking buckle having at least one channel and at least one locking tang or pawl positioned within the locking buckle, wherein increased insertion of the first strap end into the locking head decreases the size of the loop of the elongated strap to secure the bundle.

A fastening strap and a manufacturing method thereof are provided. The fastening strap includes a first band and a second band. The first band has a first surface and a second surface. The first surface has a plurality of hooks of special configuration. The second band has a third surface and a fourth surface. The third surface is directly adhered to the second surface of the first band, and the fourth surface has a plurality of loops for being mechanically latched by the hooks on the first surface. The second surface and/or the third surface is printed with at least one pattern. After the first band and the second band are adhered together, the pattern can be seen from the first surface of the first band.

Embodiments of a loop clip used with a golf bag and methods to manufacture a golf bag are generally described herein. Other embodiments of the loop clip may be described and claimed.

A method is used to prepare a body for burial. The method includes placing the body inside a vessel. The body includes bones and tissue. The method further includes subjecting the body to a flow of steam until the bones are free of tissue. In one implementation, the flow of steam has a temperature of about 212 degrees Fahrenheit and a mass flow rate of at least 1000 pounds per hour. The method may further include removing the bones from the vessel.

A method of forming a sheet metal casket comprises providing a sheet metal casket shell having at least a portion of an end wall and at least a portion of a side wall and a round corner between the portion of the end wall and the portion of the side wall, and forming a generally planar corner oriented at about a 45° angle relative to the portion of the end wall and the portion of the side wall.