Method, apparatus, and program means for performing a conversion. In one embodiment, a disclosed apparatus includes a destination storage location corresponding to a first architectural register. A functional unit operates responsive to a control signal, to convert a first packed first format value selected from a set of packed first format values into a plurality of second format values. Each of the first format values has a plurality of sub elements having a first number of bits The second format values have a greater number of bits. The functional unit stores the plurality of second format values into an architectural register.

Method, apparatus, and program means for performing a conversion. In one embodiment, a disclosed apparatus includes a destination storage location corresponding to a first architectural register. A functional unit operates responsive to a control signal, to convert a first packed first format value selected from a set of packed first format values into a plurality of second format values. Each of the first format values has a plurality of sub elements having a first number of bits The second format values have a greater number of bits. The functional unit stores the plurality of second format values into an architectural register.

Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes a data detector circuit. The data detector circuit includes an anti-causal noise predictive filter circuit and a data detection circuit. In some cases, the anti-causal noise predictive filter circuit is operable to apply noise predictive filtering to a detector input to yield a filtered output, and the data detection circuit is operable to apply a data detection algorithm to the filtered output derived from the anti-causal noise predictive filter circuit.

Solving computational problems may include generating a logic circuit representation of the computational problem, encoding the logic circuit representation as a discrete optimization problem, and solving the discrete optimization problem using a quantum processor. Output(s) of the logic circuit representation may be clamped such that the solving involves effectively executing the logic circuit representation in reverse to determine input(s) that corresponds to the clamped output(s). The representation may be of a multiplication circuit. The discrete optimization problem may be composed of a set of miniature optimization problems, where each miniature optimization problem encodes a respective logic gate from the logic circuit representation. A multiplication circuit may employ binary representations of factors, and these binary representations may be decomposed to reduce the total number of variables required to represent the multiplication circuit.

Method, apparatus, and program means for performing a conversion. In one embodiment, a disclosed apparatus includes a destination storage location corresponding to a first architectural register. A functional unit operates responsive to a control signal, to convert a first packed first format value selected from a set of packed first format values into a plurality of second format values. Each of the first format values has a plurality of sub elements having a first number of bits The second format values have a greater number of bits. The functional unit stores the plurality of second format values into an architectural register.

Method, apparatus, and program means for performing a conversion. In one embodiment, a disclosed apparatus includes a destination storage location corresponding to a first architectural register. A functional unit operates responsive to a control signal, to convert a first packed first format value selected from a set of packed first format values into a plurality of second format values. Each of the first format values has a plurality of sub elements having a first number of bits The second format values have a greater number of bits. The functional unit stores the plurality of second format values into an architectural register.

A random number generation method and apparatus using a low-power microprocessor is provided. In the random number generation method, a low-power microprocessor determines whether external power is supplied to a random number generator. The low-power microprocessor updates an internal state of the random number generator based on a first scheme if it is determined that the external power is supplied to the random number generator. The low-power microprocessor updates the internal state of the random number generator based on a second scheme different from the first scheme if it is determined that the external power is not supplied to the random number generator.

Distributed processing system and method for discrete logarithm calculation. The speed and resource efficiency of discrete logarithm calculation may be improved by allowing a plurality of operation agents to distributively process an operation of generating a modulo multiplication auxiliary table, an operation of generating a pre-calculation table, and an operation of searching for an answer by applying an iterated function for discrete logarithm calculation in a discrete logarithm calculation operation using the pre-calculation table.

A communication device includes a storage unit to store quotients and remainders associated with multiplication values obtained by multiplying a specified integer number, which is expressed in a form of (2β+α) where β is a positive integer number and α is a positive integer number other than integral multiples of 2, respectively, the quotients and the remainders being obtained by dividing the multiplication values by 2β, respectively, a first unit to divide a dividend by 2βand calculate a quotient and a remainder, a second unit to obtain a quotient, which corresponds to the remainder from the storage unit, and a third unit to determine that the data length of the packet data is normal, when a combination of the quotient and the remainder calculated by the first unit is in the storage unit.

Techniques for medium access control. Some techniques include receiving, at a first computing device, a solicitation for at least a first medium access request that specifies at least one time period for transmitting the first medium access request to the second computing device; encoding the first medium access request at least in part by using a compressive sensing encoding technique to obtain a first encoded medium access request; and transmitting the first encoded medium access request to the second computing device during the at least one time period specified in the received solicitation.

A function f(x) is calculated with a calculating apparatus that makes a correct calculation with a low probability. Provided that G and H are cyclic groups, f is a function that maps an element x of the group H into the group G, X1 and X2 are random variables whose values are elements of the group G, x1 is a realized value of the random variable X1, and x2 is a realized value of the random variable X2, an integer calculation part calculates integers a' and b' that satisfy a relation a'a+b'b=1 using two natural numbers a and b that are relatively prime. A first randomizable sampler is capable of calculating f(x)bx1 and designates the calculation result as u. A first exponentiation part calculates u'=ua. A second randomizable sampler is capable of calculating f(x)ax2 and designates the calculation result as v. A second exponentiation part calculates v'=vb. A determining part determines whether u'=v' or not. A final calculation part calculates ub'va' in a case where it is determined that u'=v'.

A method and apparatus for including in a processor instructions for performing logical-comparison and branch support operations on packed or unpacked data. In one embodiment, instruction decode logic decodes instructions for an execution unit to operate on packed data elements including logical comparisons. A register file including 128-bit packed data registers stores packed single-precision floating point (SPFP) and packed integer data elements. The logical comparisons may include comparison of SPFP data elements and comparison of integer data elements and setting at least one bit to indicate the results. Based on these comparisons, branch support actions are taken. Such branch support actions may include setting the at least one bit, which in turn may be utilized by a branching unit in response to a branch instruction. Alternatively, the branch support actions may include branching to an indicated target code location.

A method and apparatus for including in a processor instructions for performing logical-comparison and branch support operations on packed or unpacked data. In one embodiment, instruction decode logic decodes instructions for an execution unit to operate on packed data elements including logical comparisons. A register file including 128-bit packed data registers stores packed single-precision floating point (SPFP) and packed integer data elements. The logical comparisons may include comparison of SPFP data elements and comparison of integer data elements and setting at least one bit to indicate the results. Based on these comparisons, branch support actions are taken. Such branch support actions may include setting the at least one bit, which in turn may be utilized by a branching unit in response to a branch instruction. Alternatively, the branch support actions may include branching to an indicated target code location.

A system (200) and a method (100) of operating a computing device to perform memoization are disclosed. The method includes determining whether a result of a function is stored in a cache and, if so, retrieving the result from the cache and, if not, calculating the result and storing it in the cache. The method (100) includes transforming (104) by the computing device at least one selected from the input parameters and the output parameters of the function, the transforming being based on an analysis of the function and its input arguments to establish whether or not there is a possible relationship reflecting redundancy among the input parameters and output parameters of the function. The transforming may include at least one of: use of symmetry, scaling, linear shift, interchanging of variables, inversion, polynomial and/or trigonometric transformations, spectral or logical transformations, fuzzy transformations, and systematic arrangement of parameters.

A method of generating a code sequence in a wireless communication system is disclosed. More specifically, the method includes recognizing a desired length of the code sequence, generating a code sequence having a length different from the desired length, and modifying the length of the generated code sequence to equal the desired length. Here, the step of modifying includes discarding at least one element of the generated code sequence or inserting at least one null element to the generated code sequence.

A method for generating multi-level (or multi-bit) pseudo-random sequences is disclosed. This embodiment relates to communication systems, and more particularly to generating multi-level pseudo random symbol sequence. Present day systems do not employ effective mechanisms for generation of multi level PRBS in order to increase the data communication rates. Further, these systems do not cover all the possible transitions for the outputs of the system. The proposed system employs mechanisms in order to generate PRBS signals for producing multi levels signals to the electronic components. The mechanism employs alternate bit tapping techniques. In the alternate bit tapping technique, bits are tapped alternatively to determine the current state and the next state of the system. In addition, the mechanism also covers all the possible states of the output vector with transitions between the output states. This ensures that high data rates are obtained for a given bandwidth of operation.

A Montgomery inverse calculation device includes a plurality of registers each storing a value of a variable, a modulus register storing a modulus, a multiplier performing multiplication on the modulus. A comparator compares the value of the variable stored in each of the registers with an output value of the multiplier and generates a plurality of control signals. A plurality of shifters shifts bits of a value of a variable stored in a corresponding register among the registers in response to at least one first control signal, and a quotient generation block calculates a quotient of mod 2m with respect to values output from some of the shifters in response to a second control signal. A calculation block calculates an updated value of an output value of each of the shifters using the quotient in response to at least one third control signal.

A method and apparatus for including in a processor instructions for performing logical-comparison and branch support operations on packed or unpacked data. In one embodiment, instruction decode logic decodes instructions for an execution unit to operate on packed data elements including logical comparisons. A register file including 128-bit packed data registers stores packed single-precision floating point (SPFP) and packed integer data elements. The logical comparisons may include comparison of SPFP data elements and comparison of integer data elements and setting at least one bit to indicate the results. Based on these comparisons, branch support actions are taken. Such branch support actions may include setting the at least one bit, which in turn may be utilized by a branching unit in response to a branch instruction. Alternatively, the branch support actions may include branching to an indicated target code location.

The present invention provides a polymerization reactor for producing a super absorbent polymer comprising: a reaction unit; a monomer composition supply unit being connected to the reaction unit and supplying a monomer composition solution containing a monomer, a photoinitiator, and a solvent; an agitating shaft extended in the reaction unit from one end of the reaction unit connected to the monomer composition supply unit to the other end of the reaction unit; a plurality of agitating blades installed around the agitating shaft; and a light irradiation unit providing light to the monomer composition solution furnished from the monomer composition supply unit, and a method of producing super absorbent polymers by using the same.

The present invention relates to methods for preparing a degradable polymer network. The methods for preparing a degradable polymer network comprise a) preparing a polymer composition comprising monomers of cyclic carbonates and/or cyclic esters and/or linear carbonates and/or linear esters and/or cyclic ethers and/or linear hydroxycarboxylic acids at a temperature between 20° C. and 200° C.; b) adding a cross-linking reagent comprising at least one double or triple C—C bond and/or a cross-linking radical initiator; c) processing the polymer composition (that contains the crosslinking reagent into a desired shape; d) Crosslinking by irradiating the mixture. Further, the present invention relates to a degradable polymer network. Furthermore, the present invention relates to the use of the degradable polymer network.

An active ray curable composition, including: a photobase generator; a polymerizable compound; and an acid, wherein the photobase generator is a salt of a carboxylic acid and a basic compound, wherein a ratio by mole of a carboxyl group of the carboxylic acid:a basic functional group of the basic compound is 1:1, and wherein the acid is an acid that loses a function thereof as acid by light or heat.

Described is a radiation-crosslinkable hotmelt adhesive comprising at least one radiation-crosslinkable poly(meth)acrylate formed to an extent of at least 60% by weight of C1 to C10 alkyl(meth)acrylates and at least one oligo(meth)acrylate which comprises nonacrylic C C double bonds and has a K value of less than or equal to 20. The hotmelt adhesive comprises a photoinitiator which may be present in the form of an additive not attached to the poly(meth)acrylate and/or not attached to the oligo(meth)acrylate, may be incorporated by copolymerization into the poly(meth)acrylate, and/or may be attached to the oligo(meth)acrylate. The hotmelt adhesive can be used for producing adhesive tapes.

The active ray-curable inkjet ink comprises a gelling agent, photopolymerizable compounds and a photoinitiator, and reversibly transitions into a sol-gel phase according to the temperature. Therein: (1) a (meth)acrylate compound having a molecular weight of 300-1,500 and having 3-14 (—CH2—CH2—O—) structural units within a molecule is included as the first photopolymerizable compound at a proportion of 30-70 mass % relative to the total mass of the ink; (2) a (meth)acrylate compound having a molecular weight of 300-1,500 and a C log P value of 4.0-7.0 is included as the second photopolymerizable compound at a proportion of 10-40 mass % relative to the total mass of the ink; and (3) the gelling agent has a total of at least 12 carbon atoms, and has a straight or branched alkyl chain including at least three carbon atoms.

A durable ambient light curable waterproof liquid rubber coating with volatile organic compound (VOC) content of less than 450 grams per liter made from ethylene propylene diene terpolymer (EPDM) in a solvent, a photoinitiator, an additive, pigments, and fillers, and a co-agent and a method for making the formulation, wherein the formulation is devoid of thermally activated accelerators.

A crosslinkable curing super-branched polyester and the cured product and the preparation method thereof are disclosed. The super-branched polyester has high refractive index and comprises a compound represented by the following structural formula (I). In the formula (I), HBP is the backbone of the super-branched polyester; both a and b are positive integers; the sum of a and b is less than or equal to n; n is more than or equal to 10 and less than 80. In the super-branched polyester, A is represented by formula (II) and N is represented by formula (III), wherein R is methyl or hydrogen atom; the mole ratio of N relative to the total mole of A and N is more than 30 mol %, and the ratio of the total mole of A and N relative to the product of the total mole of HBP backbone and n is more than 0.5 and less than or equal to 1.

A photocurable material for sealing including (A) an oligomer having a weight average molecular weight of 10,000 to 30,000 and having (meth)acryloyl group(s), (B) a (meth)acrylate monomer, (C) a polythiol compound, and optionally (D) a carbodiimide compound enables the provision of a sealing material that has high compression recovery performance, high tensile strength and excellent flexibility, can have low hardness if required, and therefore has excellent sealing properties including air-tightness performance and water-proof performance and undergoes the formation of little surface tacks and the like.

The present invention is a method for producing a composite including a matrix and a dispersed material dispersed in the matrix. The method includes introducing a raw material for dispersed material which constitutes a dispersed material into a fluid including a melt of a raw material for matrix which constitutes a matrix or a solution containing a raw material for matrix by a vapor deposition method, to obtain a composite.

The invention relates to an acrylate-based UV-curable ink, in particular ink jet ink, having a content of pigments, radical photoinitiators, dispersing agent(s)and optionally additional additives, characterized in that said ink contains at least two radical photoinitiators of the Norrish type I and at least one radically curable monomer in the form of a polyfunctional alkoxylated and/or polyalkoxylated acrylate monomer, which comprises one or more diacrylates and/or triacrylates, wherein the mol ratio of all acrylates to all initiators is approximately 5:1 to 19:1. The invention further relates to a method for producing a UV-curable ink, in particular an ink jet ink of the aforementioned type, wherein 1) a ground product or an ink base is produced by grinding one or more radically curable monomers in the form of a polyfunctional alkoxylated and/or polyalkoxylated acryl monomer, which comprise one or more diacrylate(s) and/or triacrylate(s), with one or more pigments and dispersing agents, in particular optionally additionally with synergists, stabilizers and further additives, in a high-performance mill, in particular in a pearl mill, until a constant viscosity and/or constant particle size develops, and 2) the resulting ground product is mixed with further acrylate monomers and the radical photoinitiators in the form of the Norrish type I, and optionally other additives. Said ground product exhibits advantageous physical properties at elevated temperatures and in long-term storage.

An optical component and an electrical board that have a low coefficient of linear expansion and small mold shrinkage, a method for producing the optical component, and a method for producing the electronic board are provided. An optical component includes a polymer having a repeating structural unit represented by general formula (1) where R1 and R2 each independently represent —H or —CH3; m and n each independently represent an integer in the range of 0 to 3; asterisk denotes a dangling bond that bonds to one of Xa and Xb; and —H bonds to the other one of Xa and Xb.

A UV curable silicone rubber composition is provided. The composition does not undergo curing failure, foaming, and other undesirable conditions even if a water-containing inorganic filler such as zeolite were added. A UV curable silicone rubber composition comprising (A) 100 parts by weight of an organopolysiloxane having at least 2 alkenyl groups per molecule represented by the average compositional formula (I): R1aSiO(4-a)/2 (I) (wherein R1 is independently a substituted or unsubstituted monovalent hydrocarbon group, and a is a positive number of 1.95 to 2.05); (B) 1 to 300 parts by weight of an inorganic filler having a water content of at least 0.5% by weight; (C) 0.1 to 50 parts by weight of an organohydrogenpolysiloxane having at least 2 silicon-bonded hydrogen atoms per molecule; and (D) a catalytic amount of a photoactive platinum complex curing catalyst.

A heat-resistant cured product is efficiently produced by obtaining a semi-cured product where a curable resin composition containing a (meth)acrylate monomer, a non-conjugated vinylidene group-containing compound and a thermal radical-polymerization initiator is processed by at least one of photoirradiation and heating to give a semi-cured product having a complex viscosity of from 105 to 108 mPa·s at 25° C. and at a frequency of 10 Hz; and putting the semi-cured product in a forming die for pressure formation therein, and heating it therein for thermal polymerization to give a cured product.

The present invention aims to provide a surface modification method for a rubber vulcanizate or a thermoplastic elastomer, which can impart excellent sliding properties and excellent durability against repeated sliding motion and can allow the surface to maintain the sealing properties, without using expensive self-lubricating plastics. The present invention relates to a surface modification method for modifying a rubber vulcanizate or a thermoplastic elastomer as an object to be modified, the method including: step 1 of forming polymerization initiation points on the object to be modified; step 2 of radically polymerizing a monomer, starting from the polymerization initiation points, by irradiation with LED light at 300 nm to 400 nm to grow polymer chains on a surface of the object to be modified; and step 3 of esterifying, transesterifying or amidating side chains of the polymer chains.

The present invention is directed to a coating composition including a (meth)acrylate binder resin, a UV initiator, an organic solvent, and silica particles surface-treated with a (meth)acrylate compound, a coating film including a cured product of the coating composition, and a method of producing the coating film. The present invention makes it possible to provide a coating material having high transmittance and a low level of haze, and excellent scratch resistance and self-healing capabilities.

An electronic device, including: one or more hardware interfaces each for connecting to a signal source to receive at least one type of application resources; a control chip electrically connected to the one or more hardware interfaces, the control chip being configured to classify and integrate one or more types of application resources received through the one or more hardware interfaces, and generate a display signal for a main interface including a number of areas arranged according to a predetermined layout, wherein each area is configured to display information regarding a same type of the classified and integrated application resources, and different areas are configured to display information regarding different types of the classified and integrated application resources; and a display screen electrically connected to the control chip to display the main interface according to the display signal.

Embodiments of the present invention relate to a method and an apparatus for obtaining equipment identification information, where the method includes: detecting, by using a first GPIO port, a first discharging duration for a capacitor to discharge through a resistor to be tested; detecting, by using a second GPIO port, a second discharging duration for the capacitor to discharge through a fixed value resistor; and obtaining a resistance of the resistor to be tested according to the first discharging duration, the second discharging duration, and a resistance of the fixed value resistor. The embodiments of the present invention are capable of increasing identification efficiency of the GPIO port.

An electronic data tablet has a controller and transition manager. The controller is to store in a memory of the tablet virtual configuration space information for a peripheral device of a computer, and the transition manager is to control the controller to operate in a first mode and a second mode. The virtual configuration space information is stored in the tablet memory when the first mode is to be switched to the second mode. When the second mode is switched to the first mode, the virtual configuration space information is accessed to control recognition of the peripheral device of the computer without performing a re-scanning operation.

A method of interacting with data at a wireless communication device is provided. The wireless communication device has access to a first set of capabilities. Data is received at the wireless communication device via a wireless transmission. The data represents visual content that is viewable via a display device. A graphical user interface, including a delayed action selector, is provided via the display device. An input is received within a limited period of time after displaying the delayed action selector. The input is associated with a command to delay execution of an action with respect to the data until the wireless communication device has access to a second set of capabilities. The action is not supported by the first set of capabilities but is supported by the second set of capabilities. An indication of receipt of the input is provided at the wireless communication device.

A semiconductor memory device includes a selection signal generation unit configured to generate a plurality of selection signals that are sequentially activated, a path selection unit configured to select a transmission path of sequentially input information data in response to the plurality of selection signals, a plurality of first storage units, each configured to have a first storage completion time and store an output signal of the path selection unit, and a plurality of second storage units, each configured to have a second storage completion time, which is longer than the first storage completion time, and store a respective output signal of the plurality of first storage units.

Systems, mediums, and methods are provided for scheduling input/output requests to a storage system. The input output requests may be received, categorized based on their priority, and scheduled for retrieval from the storage system. Lower priority requests may be divided into smaller sub-requests, and the sub-requests may be scheduled for retrieval only when there are no pending higher priority requests, and/or when higher priority requests are not predicted to arrive for a certain period of time. By servicing the small sub-requests rather than the entire lower priority request, the retrieval of the lower priority request may be paused in the event that a high priority request arrives while the lower priority request is being serviced.

A memory system includes a CPU that communicates commands and addresses to a main-memory module. The module includes a buffer circuit that relays commands and data between the CPU and the main memory. The memory module additionally includes an embedded processor that shares access to main memory in support of peripheral functionality, such as graphics processing, for improved overall system performance. The buffer circuit facilitates the communication of instructions and data between CPU and the peripheral processor in a manner that minimizes or eliminates the need to modify CPU, and consequently reduces practical barriers to the adoption of main-memory modules with integrated processing power.

A transfer control circuit stores data in a FIFO memory, outputs data in the FIFO memory in response to a data request signal, and outputs a state signal in accordance with an amount of stored data in the FIFO memory. An output data generating unit outputs image data having a horizontal image size in accordance with a horizontal count value and a horizontal synchronizing signal, and thereafter, outputs blank data. When the state signal indicates that the FIFO memory is in a “EMPTY” or “MODERATE” storage state, a blank control unit outputs a blank addition signal until the FIFO memory changes to a “FULL” storage state.

A data storage device includes a first memory device configured to store data having a first property, a second memory device configured to store data having a second property, and a controller. The controller selects data stored in the first memory device, and transfers the selected data to the second memory device or stores the selected data in another physical location of the first memory device selectively depending on an update count (UC) of an address at which the selected data is stored.

Apparatuses and methods of calibrating a memory interface are described. Calibrating a memory interface can include loading and outputting units of a first data pattern into and from at least a portion of a register to generate a first read capture window. Units of a second data pattern can be loaded into and output from at least the portion of the register to generate a second read capture window. One of the first read capture window and the second read capture window can be selected and a data capture point for the memory interface can be calibrated according to the selected read capture window.

Method and system for an adapter is provided. The adapter includes a plurality of function hierarchies, with each function hierarchy including a plurality of functions and each function being associated with an event. The adapter also includes a plurality of processors for processing one or more events generated by the plurality of functions. The adapter further includes a first set of arbitration modules, where each arbitration module is associated with a function hierarchy and receives interrupt signals from the functions within the associated function hierarchy and selects one of the interrupt signals. The adapter also includes a second set of arbitration modules, where each arbitration module receives processor specific interrupt signals and selects one of the interrupt signals for processing an event associated with the selected interrupt signal.

In an interrupt control method of a multicore processor system including cores, a cache coherency mechanism, and a device, a first core detecting an interrupt signal from the device writes into an area prescribing an interrupt flag in the cache memory of the first core, first data indicating detection of the interrupt signal, and notifies the other cores of an execution request for interrupt processing corresponding to the interrupt signal, consequent to the cache coherency mechanism establishing coherency among at least cache memories of the other cores when the first data is written; and a second core different from the first core, maintaining the first data written as the interrupt flag, and notified of the execution request executes the interrupt processing, and writes over the area prescribing the interrupt flag written in the cache memory of the second core, with second data indicating no-detection of the interrupt signal.

A universal serial bus (USB) dongle device includes a USB interface that receives selection data from a host device that indicates a selection of a first video format from a plurality of available formats. The USB interface also receives an input video signal from the host device in the first video format and a power signal from the host device. An encoding module generates a processed video signal in a second video format based on the input video signal, wherein the first video format differs from the second video format. The USB interface transfers the processed video signal to the host device.

An information processing apparatus includes a plurality of modules connected in a ring shape via a bus, and each module processes a packet flowing in a single direction on the ring in a predetermined order. The module includes a communication unit for transmitting a packet received from a first direction in the ring via the bus to a second direction, a discrimination unit for discriminating a packet from among the packets received from the first direction as a processing packet to be processed by the module, and a processing unit which is connected with the communication unit one by one and configured to process the processing packet. The communication unit transmits the packet processed by the processing unit at an interval equivalent to processing time or more for a processing packet processed by a module in a latter stage in the predetermined order among packets transmitted by the communication unit to the second direction.

A method, apparatus, and system for switching from an existing target end device to a next target end device in a multi-expander storage topology by using Fast Context Switching. The method enhances Fast Context Switching by allowing Fast Context Switching to reuse or extend part of an existing connection path to an end device directly attached to a remote expander. The method can include reusing or extending at least a partial path of an established connection between an initiator and the existing target end device for a connection between the initiator and the next target end device, whereby the existing target end device and the next target end device are locally attached to different expanders.

A detection device for detecting the manner in which a peripheral device is removed from an electronic device is proposed. The detection device can be on the peripheral device or the electronic device and detects whether the peripheral device was removed in a manner that indicates the removal was intentional or unintentional.

A data transfer control apparatus includes a transferring unit that transfers data from a transfer source memory to a transfer destination memory, according to an instruction from a first processor; and a first processor configured to detect a process execute by the first processor, determine whether transfer of the data is urgent, based on the type of the detected process, and control the transferring unit or the first processor to transfer the data, based on a determination result.