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Pyrroline-5-carboxylate reductase 1 (PYCR1) catalyzes the biosynthetic half-reaction of the proline cycle by reducing Δ1-pyrroline-5-carboxylate (P5C) to proline through the oxidation of NAD(P)H. Many cancers alter their proline metabolism by up-regulating the proline cycle and proline biosynthesis, and knockdowns of PYCR1 lead to decreased cell proliferation. Thus, evidence is growing for PYCR1 as a potential cancer therapy target. Inhibitors of cancer targets are useful as chemical probes for studying cancer mechanisms and starting compounds for drug discovery; however, there is a notable lack of validated inhibitors for PYCR1. To fill this gap, we performed a small-scale focused screen of proline analogs using X-ray crystallography. Five inhibitors of human PYCR1 were discovered: l-tetrahydro-2-furoic acid, cyclopentanecarboxylate, l-thiazolidine-4-carboxylate, l-thiazolidine-2-carboxylate, and N-formyl l-proline (NFLP). The most potent inhibitor was NFLP, which had a competitive (with P5C) inhibition constant of 100 μm. The structure of PYCR1 complexed with NFLP shows that inhibitor binding is accompanied by conformational changes in the active site, including the translation of an α-helix by 1 Å. These changes are unique to NFLP and enable additional hydrogen bonds with the enzyme. NFLP was also shown to phenocopy the PYCR1 knockdown in MCF10A H-RASV12 breast cancer cells by inhibiting de novo proline biosynthesis and impairing spheroidal growth. In summary, we generated the first validated chemical probe of PYCR1 and demonstrated proof-of-concept for screening proline analogs to discover inhibitors of the proline cycle.

Simultaneous sampling of 4 channels with sampling times down to 5 μs(NX-HAD[][][])

Analog input units for CK3M Controller(CK3W-AD[]100)

Disclosed is an apparatus for protecting an analog input module from overvoltage, the apparatus including an analog input module and a stabilization unit. The analog input module converts one of a plurality of positive/negative analog signals inputted from the outside thereof into a digital signal and insulates the converted digital signal. The stabilization unit supplies voltages of the positive/negative analog signals to the analog input module when the voltage levels of the plurality of positive/negative analog signals are higher than the levels of positive/negative operating voltages in the analog input module.

Hi GuysI have just set up my own Travel Bog and will update this whilst we are away and hopefully attach photo's.I have added you guys so every time I make an entry you will get an email.Just adding this now to test I have set it up correctly

Hello,

I am trying to import multiple verilog modules defined in a single file with "`define" directive in the top using Verilog In. The code below is an example of what my file contains.

When I use the settings below to import the modules into a library, it imports it correctly but completely ignores all `define directive; hence when I simulate using any of the modules below the simulator errors out requesting these variables.

My question: Is there a way to make Verilog In consider `define directives in every module cell created? 

Code to be imported by Cadence Verilog In:

--------------------------------------------------------

`timescale 1ns/1ps
`define PROP_DELAY 1.1
`define INVALID_DELAY 1.3

`define PERIOD 1.1
`define WIDTH 1.6
`define SETUP_TIME 2.0
`define HOLD_TIME 0.5
`define RECOVERY_TIME 3.0
`define REMOVAL_TIME 0.5
`define WIDTH_THD 0.0

`celldefine
module MY_FF (QN, VDD, VSS, A, B, CK);

inout VDD, VSS;
output QN;
input A, B, CK;
reg NOTIFIER;
supply1 xSN,xRN;
buf IC (clk, CK);
and IA (n1, A, B);
udp_dff_PWR I0 (n0, n1, clk, xRN, xSN, VDD, VSS, NOTIFIER);
not I2 (QN, n0);

wire ENABLE_B ;
wire ENABLE_A ;
assign ENABLE_B = (B) ? 1'b1:1'b0;
assign ENABLE_A = (A) ? 1'b1:1'b0;

specify
$setuphold(posedge CK &&& (ENABLE_B == 1'b1), posedge A,  `SETUP_TIME, `HOLD_TIME, NOTIFIER);
$setuphold(posedge CK &&& (ENABLE_B == 1'b1), negedge A, `SETUP_TIME, `HOLD_TIME, NOTIFIER);
$setuphold(posedge CK &&& (ENABLE_A == 1'b1), posedge B, `SETUP_TIME, `HOLD_TIME, NOTIFIER);
$setuphold(posedge CK &&& (ENABLE_A == 1'b1), negedge B, `SETUP_TIME, `HOLD_TIME, NOTIFIER);
$width(posedge CK,1.0,0.0,NOTIFIER);
$width(negedge CK,1.0,0.0,NOTIFIER);
if (A==1'b0 && B==1'b0)
(posedge CK => (QN:1'bx)) = (1.0, 1.0);
if (A==1'b1 && B==1'b0)
(posedge CK => (QN:1'bx)) = (1.0, 1.0);
if (B==1'b1)
(posedge CK => (QN:1'bx)) = (1.0,1.0);

endspecify

endmodule // MY_FF
`endcelldefine

`timescale 1ns/1ps
`celldefine
module MY_FF2 (QN, VDD, VSS, A, B, CK);

inout VDD, VSS;
output QN;
input A, B, CK;
reg NOTIFIER;
supply1 xSN,xRN;
buf IC (clk, CK);
and IA (n1, A, B);
udp_dff_PWR I0 (n0, n1, clk, xRN, xSN, VDD, VSS, NOTIFIER);
not I2 (QN, n0);

wire ENABLE_B ;
wire ENABLE_A ;
assign ENABLE_B = (B) ? 1'b1:1'b0;
assign ENABLE_A = (A) ? 1'b1:1'b0;

specify
$setuphold(posedge CK &&& (ENABLE_B == 1'b1), posedge A,  `SETUP_TIME, `HOLD_TIME, NOTIFIER);
$setuphold(posedge CK &&& (ENABLE_B == 1'b1), negedge A,  `SETUP_TIME, `HOLD_TIME, NOTIFIER);
$setuphold(posedge CK &&& (ENABLE_A == 1'b1), posedge B,  `SETUP_TIME, `HOLD_TIME, NOTIFIER);
$setuphold(posedge CK &&& (ENABLE_A == 1'b1), negedge B,  `SETUP_TIME, `HOLD_TIME, NOTIFIER);
$width(posedge CK,1.0,0.0,NOTIFIER);
$width(negedge CK,1.0,0.0,NOTIFIER);
if (A==1'b0 && B==1'b0)
(posedge CK => (QN:1'bx)) = (1.0, 1.0);
if (A==1'b1 && B==1'b0)
(posedge CK => (QN:1'bx)) = (1.0, 1.0);
if (B==1'b1)
(posedge CK => (QN:1'bx)) = (1.0,1.0);

endspecify

endmodule // MY_FF2
`endcelldefine

--------------------------------------------------------

I am using the following Cadence versions:

MMSIM Version: 13.1.1.660.isr18

Virtuoso Version: IC6.1.8-64b.500.1

irun Version: 14.10-s039

Spectre Version: 18.1.0.421.isr9