A parking assist system includes: an actuator that drives a back door of a vehicle; an opening degree control unit that controls an opening degree of the back door by controlling the actuator; a storage device that stores an allowable opening degree of the back door at a park position of the vehicle in association with the park position; and a position information acquisition unit that acquires position information of the vehicle. When a position of the vehicle corresponds to the park position stored in the storage device, the opening degree control unit limits the opening degree of the back door on the basis of the allowable opening degree of the back door, stored in the storage device in association with the park position.

This disclosure relates generally to field-programmable gate arrays (FPGAs). Some implementations relate to methods and systems for transmitting and integrating an intellectual property (IP) block with another user's design. The IP developer can design the IP block to include both a secret portion and a public portion. The IP block developer can send or otherwise provide the IP block to another IP user without disclosing the functional description of the secret portion of the IP block. In some implementations, the IP developer provides the public portion to the IP user at the register-transfer-level (RTL) level, as a hardware description language (HDL)-implemented design, or as a synthesizable netlist. In some implementations, the IP developer provides the secret portion of the IP block to the user in the form of programming bits without providing an HDL, RTL, or netlist implementation of the secret portion.

A plurality of Field Programmable Gate Arrays (FPGA), high performance transceivers, and memory devices provide a verification module for timing and state debugging of electronic circuit designs. Signal value compression circuits and gigabit transceivers embedded in each FPGA increase the fanout of each FPGA. Ethernet communication ports enable remote software debugging of processor instructions.

Methods are provided to facilitate automated creation and management of design rule checking or DRC waiver descriptions. Embodiments include receiving a plurality of first checksums corresponding to respective first geometric element violations waived in association with a block of an integrated circuit design, the first checksums being based on a first version of at least one design verification rule and/or of the block, receiving a second checksum corresponding to a second geometric element violation associated with the block, the second checksum being based on a second version of the design verification rule and/or of the block, determining whether the second checksum corresponds to at least one of the first checksums, and, if the second checksum does not correspond to at least one first checksum, generating a waiver request for the second geometric element error.

A system, method, and computer program product for automatically generating equivalent assertions in different forms for different verification tools, which may be analog or digital. A user submits a set of logic assertions that, if unclocked, are converted to clocked assertions by generating and skewing clocks to ensure simulator uniformity. A stimulus is generated, perhaps at random, or input. A test bench is either input or synthesized. For each verification tool, the test bench is simulated and simulation results are captured. An assertion status difference engine evaluates result differences between the verification tools, and identifies and outputs differences indicating a significant inconsistency. Errors in verification tool implementation and user assertion coding can be detected. The simulators used may include SPICE and Verilog, or any other simulators that differ in type, simulation algorithm, input format, or vendor implementation.

This disclosure relates generally to systems and methods for simulating physical active semiconductor components using in silico active semiconductor components. To simulate charge degradation effect(s) in a circuit simulation, a simulated defect signal level is produced. More specifically, the simulated defect signal level simulates at least one charge degradation effect in the in silico active semiconductor component as a function of simulation time and a simulated input signal level of a simulated input signal. As such, the charge degradation effect(s) are simulated externally with respect to the in silico active semiconductor component. In this manner, the in silico active semiconductor component does not need to be reprogrammed in order to simulate charge degradation effects.

One implementation of the disclosure provides a crosstalk analysis method executed by a computer. The method includes steps of: executing a layout program; executing a crosstalk analysis program; acquiring, by the crosstalk analysis program, a plurality of parameters from a layout result generated by the layout program; estimating a crosstalk value according to the parameters; determining whether the crosstalk value is larger than a predetermined value; providing a layout suggestion table when the crosstalk value is larger than the predetermined value.

A relationship between distance from a back bias control section which outputs a control signal for controlling a back bias of a transistor and an amount of noise in the control signal outputted from the back bias control section is found. An increase of jitter corresponding to the amount of the noise in a clock transmitted on a clock path connected to a circuit section (IP macro) is found on the basis of the relationship between the distance from the back bias control section and the amount of the noise. The circuit section and the clock path are placed on the basis of the increase of the jitter and an allowable jitter value for the circuit section.

A method of asymmetric asynchronous decoupling of capacitors in an integrated circuit design is provided for faster simulation by circuit simulators, e.g. FastSPICE circuit simulators. This method includes removing a coupling capacitor from a list, which includes coupling capacitors that capacitively couple two nets in the design. The two nets have capacitances C1 and C2, and at least one of capacitances C1 and C2 exceeds a threshold. The coupling capacitor has capacitance Cc. When coupling capacitance Cc is low and only one of capacitances C1 and C2 has a low capacitance, then a forward capacitance can be used at whichever of the two nets has the low capacitance and a lump capacitance can be used at the other net for simulation. When coupling capacitance Cc is low and both of capacitances C1 and C2 have high capacitances, then lump capacitances can be used at the two nets for the simulation.

A method includes providing a design of a semiconductor device such as a stacked CMOS device comprising a plurality of circuit elements to be assigned into a layout of a plurality of tiers, and identifying at least one first type of circuit element within the plurality of circuit elements based on at least one predetermined criterion. Each respective one of the at least one first type of circuit element is to be assigned to a respective designated one of the plurality of tiers. The method further includes dividing the remainder of the plurality of circuit elements into at least two groups of circuit elements based on circuit density, and assigning the at least one first type of circuit element and the at least two groups of circuit elements to respectively different ones of the plurality of tiers of the semiconductor device.

A method for designing a transformer in an integrated circuit includes receiving one or more desired characteristics of the transformer from user input and iteratively determining a design solution for the transformer through one or more simulations and modifications using a rule-set. The method combines the one or more desired characteristics with other preset characteristics of the transformer or the integrated circuit. A first model of the transformer is defined with typical load impedances and simulated having the combined characteristics to determine performance. Results of the simulation are processed to calculate performance with the load impedances specified by the user. The results are further processed to obtain a mathematical model that includes tuning capacitors. The first and subsequent models are modified by drawing on a rule-set of expert knowledge relating to general dependency of at least one design criterion, such as a physical, geometrical or performance characteristic, with another design criterion.

A via disposition information acquiring unit acquires via disposition information indicating a disposition of the plurality of first vias (212). A second conductor information acquiring unit acquires second conductor information indicating disposition positions of a plurality of second conductors (232) repeatedly disposed in the second conductor layer (230). A via extracting unit extracts an extraction via with respect to each of the plurality of second conductors (232). The extraction via is each of the first vias (212) overlapping the second conductor (232). A via selecting unit selects a selection via with respect to each of the plurality of second conductors (232). The selection via is each of first vias (212) selected in a predetermined number from the extraction vias. An opening introducing unit introduces a first opening (234) to each of the plurality of second conductors (232). The first opening (234) overlaps the extraction via not selected by the via selecting unit in plan view.

A method and apparatus for partitioning of the input design into repeating patterns called template cores for the application of reticle enhancement methods, design verification for manufacturability and design corrections for optical and process effects is accomplished by hierarchy analysis to extract cell overlap information. Also hierarchy analysis is performed to extract hierarchy statistics. Finally template core candidates are identified. This allows to the design to be made amenable for design corrections or other analyses or modifications that are able to leverage the hierarchy of the design since the cell hierarchy could otherwise be very deep or cells could have significant overlap with each other.

A method for mask data preparation or mask process correction is disclosed in which a set of charged particle beam shots is determined which is capable of forming a pattern on a surface, wherein critical dimension uniformity (CDU) of the pattern is optimized. In some embodiments the CDU is optimized by varying at least two factors. In other embodiments, model-based techniques are used. In yet other embodiments, the surface is a reticle to be used in an optical lithographic process to form a pattern on a wafer, and CDU on the wafer is optimized.

A method of creating a datasheet includes obtaining integrated circuit data from at least one data source, creating a data structure including the integrated circuit data obtained from the at least one data source, and creating a datasheet using data contained in the data structure. The datasheet is created in a human-readable format.

Methods for the design of microwave filters comprises comprising preferably the steps of inputting a first set of filter requirements, inputting a selection of circuit element types, inputting a selection of lossless circuit response variables, calculating normalized circuit element values based on the input parameters, and generate a first circuit, insert parasitic effects to the normalized circuit element values of the first circuit, and output at least the first circuit including the post-parasitic effect circuit values. Additional optional steps include: requirements to a normalized design space, performing an equivalent circuit transformation, unmapping the circuit to a real design space, performing a survey, and element removal optimization. Computer implement software, systems, and microwave filters designed in accordance with the method are included.

A mechanism for generating gate-level activity data for use in clock gating efficiency analysis of an integrated circuit (IC) design is provided. Generating the gate-level activity data includes generating a signal behaviour description for inter-register signals, generating a gate-level netlist for the IC design, generating gate-level stimuli based at least partly on the generated signal behaviour description, and performing gate-level simulation using the generated gate-level stimuli to generate gate-level activity data for the IC design. In one embodiment, generating the signal behaviour description includes performing Register Transfer Level (RTL) simulation of the IC design, and generating the gate-level netlist includes performing RTL synthesis. The RTL simulation and RTL synthesis are performed on RTL data for the IC design.

Some example embodiments include a computer-implemented method for designing an integrated circuit. The computer-implemented method includes receiving a hierarchical network design for the integrated circuit, wherein the hierarchical design comprises a number of components that are coupled together. The computer-implemented method includes detecting that a component of the number of components has at least one of failed timing and incomplete timing based on a problem that comprises at least one of a missing assertion, one or more missing latches, a source driver having an input source slew that is greater than a source slew limit threshold, and a sink having an input sink slew that is greater than a sink slew limit threshold. The computer-implemented method includes replacing the component with a different component that is independent of the problem and testing others components of the number of components based on the different component.

The present disclosure relates a method of performing a design rule checking (DRC) procedure on a multi-tiered integrated chip. In some embodiments, the method is performed by defining layer databases for a plurality of tiers within a multi-tiered integrated chip. The layer databases respectively identify design layers within an associated tier. A DRC (design rule checking) deck is then generated, which defines one or more individual design layer definitions as a function of a plurality of layer databases, so that the one or more individual design layer definitions are defined for a plurality of tiers. One or more design rules for the one or more individual design layer definitions are defined within the DRC deck. Since the individual design layer definitions are defined as functions of the plurality of layer databases, the design rules apply to the plurality of tiers.

Methods and systems for managing data loads on a cluster of processors that implement an iterative procedure through parallel processing of data for the procedure are disclosed. One method includes monitoring, for at least one iteration of the procedure, completion times of a plurality of different processing phases that are undergone by each of the processors in a given iteration. The method further includes determining whether a load imbalance factor threshold is exceeded in the given iteration based on the completion times for the given iteration. In addition, the data is repartitioned by reassigning the data to the processors based on predicted dependencies between assigned data units of the data and completion times of a plurality of the processers for at least two of the phases. Further, the parallel processing is implemented on the cluster of processors in accordance with the reassignment.

A method and system for optical proximity correction (OPC) is disclosed in which a set of shaped beam shots is determined which, when used in a shaped beam charged particle beam writer, will form a pattern on a reticle, where some of the shots overlap, where the pattern on the reticle is an OPC-corrected version of an input pattern, and where the sensitivity of the pattern on the reticle to manufacturing variation is reduced. A method for fracturing or mask data preparation is also disclosed.

In one embodiment of the invention, an integrated circuit (IC) design tool is provided for synthesizing logic, including one or more software modules to synthesize a gate-level netlist of a squarer functional block. The software modules include a bitvector generator, a bitvector reducer, and a hybrid multibit adder generator. The bitvector generator multiplies bits of a vector together to generate partial products for a plurality of bitvectors and then optimizes a plurality of least significant bitvectors. The bitvector reducer reduces the partial products in the bitvectors of the squarer functional block down to a pair of final vectors. The hybrid multibit adder generator generates a hybrid multibit adder including a first adder and a second adder coupled together by a carry bit with bit widths being responsive to a dividerbit. The hybrid multibit adder adds the pair of final vectors together to generate a final result for the squarer functional block.

A circuit-design support method includes obtaining information for a circuit having a logic circuit in which signal lines are connected to input terminals, signals of the signal lines being output via the logic circuit; obtaining information concerning a control circuit that has a first flip-flop for scanning and that can control a value of a given signal line by a value set by the first flip-flop; selecting, based on the circuit information, a second flip-flop at an output destination of a signal from the logic circuit, among second flip-flops of the circuit; and generating, based on the control circuit information, information indicating a serial connection of the control circuit between an output source of the signal of the given signal line and the given signal line and a connection of a data input terminal of the first flip-flop and an output terminal of the selected second flip-flop.

A technique for determining whether an integrated circuit design is susceptible to glitches includes identifying storage elements in an original register-transfer level (RTL) file of the integrated circuit design and identifying clock signals for each of the storage elements in the original RTL file. The technique also includes generating respective assertions for each of the identified clock signals and identifying potential glitchy logic in respective clock paths for each of the identified clock signals. Finally, the technique includes inserting, at the potential glitchy logic, glitches in each of the respective clock paths of the original RTL file to provide a modified RTL file and executing an RTL simulation using the modified RTL file and the respective assertions.

Disclosed are methods, systems, and articles of manufactures for implementing physical designs by using multiple force models to iteratively morph a layout decomposition. In addition to attractive force model(s) or repulsive force model(s), the physical implementation also uses a containment force model for grouping multiple design blocks or for confining a node of a cell within the boundary of a container. Another aspect is directed at deriving a first force model at the first hierarchical level from a second force model at the second hierarchical level by directly modifying the second model based at least in part on characteristic(s) of the first hierarchical level and of the second hierarchical level. In a design with multiple hierarchies, a cell-based force model is also used to ensure child nodes of a parent cell stay within a close proximity of the parent node of the parent cell.

Routing methods for an integrated circuit design layout are disclosed. The layout can include design netlists and library cells. A multiple-level global routing can generate topological wire for each net. An area oriented graph-based detail routing on the design can be performed. A post route optimization after the detail routing can be performed to further improve the routing quality. Some methods can be single threaded all or some of the time, and/or multi-threaded some or all of the time.

The disclosed technology is related to adjusting an integrated circuit design while accounting for a local density of the design. In particular exemplary embodiments, a local density value for a layout design that defines a plurality of geometric shapes is derived. Subsequently, one or more of the geometric shapes are adjusted such that the local density value is preserved. With some implementations, the local density value is preserved if the adjusted local density value is within a threshold amount of the derived local density value.

Aspects of the invention relate to techniques of defect injection for transistor-level fault simulation. A circuit element in a circuit netlist of a circuit is first selected for defect injection. Next, a defect is determined based on whether the selected circuit element is a design-intent circuit element or a parasitic circuit element. After the defect is determined, the defect is injected into the circuit netlist and then the circuit is simulated.

The present invention is directed to provide a resist remover composition for semiconductor substrate which enables to remove a resist simply and easily in the photolithography process in the semiconductor field, and a method for removing a resist comprising that the composition is used. The present invention relates to a resist remover composition for semiconductor substrate, comprising [I] a carbon radical generating agent, [II] an acid, [III] a reducing agent, and [IV] an organic solvent, and having pH of lower than 7, and a method for removing a resist, comprising that the composition is used.

A cleaning composition for sanitizing and/or disinfecting hard surfaces, comprising: a cationic biocide, surfactant and low levels of VOC solvents. The cleaning composition is adapted to clean a variety of hard surfaces without leaving behind a visible residue and creates low levels of streaking and filming on the treated surface. The cleaning composition contains less than 5% by weight of VOCs. The cleaning composition may be used alone as a liquid or spray formulation or in combination with a substrate, for example, a pre-loaded cleaning wipe.

A composition is described containing a branched nonionic surfactant of Formula (I): (I) wherein x is a real number from 1 to 11, y is a real number from 1 to 20, R 1 is an alkyl group having 1 to 3 carbon atoms, R 2 is an alkyl group having 4 to 6 carbon atoms, and a primary 5 alcohol ethoxylate.

Provided is an aqueous cleaning composition comprising at least one surfactant, xanthan gum, and a carbonate salt, wherein the composition has a turbidity of less than 16 NTU. Also provided is a method of cleaning a substrate by applying the cleaning composition to the substrate.

The present invention provides personal care compositions comprising a carrier and a mixture of essential oil components having specific levels of eucalyptol, terpene materials and auxiliary fragrance materials. The compositions herein gentle to skin and have a fragrance and activity similar if the composition were made using the pure extracted essential oil.

A gel surfactant composition suitable for hard surface cleaning, washing clothes and dishes, and which can be employed for household, institutional and/or industrial applications, composed by water and a) nonionic surfactants in the range of 1 to 50%, b) a cationic surfactant or association of cationic surfactants in the range of 20 to 50% and c) optionally amphoteric surfactants.

The invention relates to compositions and methods of treatment employing compositions comprising polyelectrolyte complexes. The compositions include a water-soluble first polyelectrolyte bearing a net cationic charge or capable of developing a net cationic charge and a water-soluble second polyelectrolyte bearing a net anionic charge or capable of developing a net anionic charge. The total polyelectrolyte concentration of the first solution is at least 110 millimolar. The composition is free of coacervates, precipitates, latex particles, synthetic block copolymers, silicone copolymers, cross-linked poly(acrylic) and cross-linked water-soluble polyelectrolyte. The composition may be a concentrate, to be diluted prior to use to treat a surface.

Surfactants (e.g., fluorosurfactants) for stabilizing aqueous or hydrocarbon droplets in a fluorophilic continuous phase are presented. In some embodiments, fluorosurfactants include a fluorophilic tail soluble in a fluorophilic (e.g., fluorocarbon) continuous phase, and a headgroup soluble in either an aqueous phase or a lipophilic (e.g., hydrocarbon) phase. The combination of a fluorophilic tail and a headgroup may be chosen so as to create a surfactant with a suitable geometry for forming stabilized reverse emulsion droplets having a disperse aqueous or lipophilic phase in a continuous, fluorophilic phase. In some embodiments, the headgroup is preferably non-ionic and can prevent or limit the adsorption of molecules at the interface between the surfactant and the discontinuous phase. This configuration can allow the droplet to serve, for example, as a reaction site for certain chemical and/or biological reactions. In another embodiment, aqueous droplets are stabilized in a fluorocarbon phase at least in part by the electrostatic attraction of two oppositely charged or polar components, one of which is at least partially soluble in the dispersed phase, the other at least partially soluble in the continuous phase. One component may provide collodial stability of the emulsion, and the other may prevent the adsorption of biomolecules at the interface between a component and the discontinous phase. Advantageously, surfactants and surfactant combinations of the invention may provide sufficient stabilization against coalescence of droplets, without interfering with processes that can be carried out inside the droplets.

A new general purpose foaming agent having application as drilling fluid foaming agents or as any foaming agent needed an a wide variety of applications is disclosed, where the agent includes at least one anionic surfactant, at least one cationic surfactant, and mixtures thereof and one or more zwitterionic compounds. A method for using the foaming agent in capillary coiled tubing application is also disclosed. The foaming agents can also include additive to augment the properties of the foaming agent for a given application.

Disclosed is a cleansing composition containing from about 6% to about 20% of at least one nonionic surfactant; from about 3% to about 10% of at least one amphoteric surfactant; from about 2% to about 8% of at least one anionic surfactant; and from about 0.1% to about 5% of at least one cationic conditioning surfactant, cationic conditioning amine, or a mixture thereof; wherein the amount of nonionic surfactant present in the final composition is greater than the amount of the amphoteric surfactant, and the ratio of the nonionic surfactant (a) to anionic surfactant (c) is at least about 1.9 as much as the anionic surfactant, based on the weight percent of each surfactant in the final composition.

A liquid detergent composition containing (A) 10 to 70 mass % of a nonionic surfactant, (B) 1 to 15 mass % of an anionic surfactant, (C) 0.01 to 2 mass % of a protease, and (D) 0.001 to 0.1 mass % of at least one compound selected from the group consisting of thiazole-based compounds and sulfur-containing amino acids.

The invention relates to compositions including a hypohalite or hypochlorous acid and a soluble salt of 2,4,6 mesitylene sulfonate. The compositions may include a surfactant, a buffer, or combinations thereof. Other adjuvants may also be present. Such compositions do not require the inclusion of high concentrations of sodium hydroxide or other soluble hydroxide salts to drastically increase pH (and thus stability), although such hydroxides may be present if desired.

A method for softening laundry employs a softening composition, which includes at least one thickener containing a cationic polymer obtained by polymerization: of a cationic monomer;of a monomer with a hydrophobic nature, of formula (I): wherein R1=H or CH3 R2=alkyl chain having at least 16 carbon atomsX═O, m≧5, y=z=0, orX═NH, m≧z≧5, y=0, orX═NH, m≧y≧5, z=0, of a nonionic monomer.

Disclosed are topical skin compositions and corresponding methods of their use that include an extract from Artabotrys hexapetalus, an extract from Sassafras tzumu, and an extract from Prunus salicina.

A rinse-off composition, such as a shampoo, hair conditioner or shower gel, comprising a rinse-off composition base, lactoyl ethanolamine and at least one compound selected from the group consisting of N-(4-cyanomethylphenyl) p-menthanecarboxamide and N-(2-pyridin-2-ylethyl) p-menthanecarboxamide. The compositions provide a pleasant, long-lasting cooling sensation.

A process for preparing a particle defoamer. The particle defoamer of 55%-75% of a carrier, 15%-35% of a silicone emulsion, 3%-10% of a texturing agent and 2%-10% of a solvent, based on the total weight of the particle defoamer; the process for preparing the particle defoamer is: (1)first adding a carrier A1 into a mixer, and then adding thereto a silicone emulsion B1, and stirring uniformly; (2)adding a carrier component A2 to the mixture obtained in (1), and stirring uniformly; (3)adding a silicone emulsion B2 to the mixture obtained in (2), and, after uniformly stirring, adding the solvent thereto and stirring uniformly; and (4)pelleting and drying by baking the mixture obtained in(3), so as to produce the product.

The invention relates to a non-corrosive degreasing concentrate and ready to use formulation. In particular, non-corrosive compositions capable of removing polymerized grease as effectively as some alkali metal hydroxide (i.e. caustic) based degreasers without requiring the use of personal protective equipment are disclosed.

Methods employing detergent compositions effective for reducing soil redeposition and accumulation on hard surfaces are disclosed. The detergent compositions employ phosphinosuccinic acid adducts in combination with an alkalinity source and gluconic acid or salts thereof, copolymers of acrylic acid and maleic acids or salts thereof, sodium hypochlorite, sodium dichloroisocyanurate or combinations thereof.

Gemini surfactants of bis-N-alkyl polyether, bis-N-alkenyl polyether, bis-N-cycloalkyl polyether, bis-N-aryl polyether bis-beta or alpha-amino acids or their salts, are produced for use as multifunctional corrosion inhibitors, which protect and prevent corrosion of ferrous metals exposed to acidic, basic and neutral liquids when transporting or storing crude oil and liquid fuels. The surfactants are also used to inhibit corrosion of equipment and pipes used in cooling systems in petroleum and petrochemical equipment. The Gemini surfactants have the structural formula:

The present invention relates to an enzyme composition comprising enzyme containing polymer particles, which is useful for detergent compositions, in particular for liquid detergent compositions. In these enzyme containing particles, the particles comprise i) at least one enzyme, and ii) at least one polymer P, which is selected from homo- and copolymers having a C—C-backbone, wherein the C—C-backbone carries carboxylgroups, which may be present in the acidic form or in the neutralized form, and wherein the C—C-backbone comprises hydrophobic repeating units.

A non-aqueous liquid cleaning composition for applicators used for applying non-aqueous hair removal compositions to the skin. The composition includes a solubilizing oil effective for solubilizing the non-aqueous hair removal composition, e.g., mineral oil, and an effective antibacterial amount of an antibacterial agent, e.g., triclosan. The composition may also include fragrances and additional bacteriocides, e.g., phenoxyethanol. When the applicator is contacted with the heated cleaning composition any hair removal composition and bacteria on the applicator are removed therefrom and the applicator is ready for reuse. It is preferred to use surgical stainless steel applicators. Also provided are methods of using these compositions and kits containing, among other items, such compositions and applicators.

Acidic viscoelastic cleaning compositions are disclosed which use non polymer thickening agents. According to the invention, cleaning compositions have been developed using viscoelastic surfactants in acidic cleaning formulations. These provide the dual benefit of thickening as well as an additional cleaning, thereby improving performance. Applicants have also identified several pseudo linking agents which when, used with viscoelastic surfactants provide enhanced viscoelasticity and cleaning.