There is a provided a method for car navigating using traffic signal data. The method for car navigating is characterized of providing an optimized route for the earliest arrival to destinations by using signal system data of one or more traffic signals existing on a certain route.

An automated process uses a local positioning system to acquire location (i.e., position and orientation) data for one or more movable target objects. In cases where the target objects have the capability to move under computer control, this automated process can use the measured location data to control the position and orientation of such target objects. The system leverages the measurement and image capture capability of the local positioning system, and integrates controllable marker lights, image processing, and coordinate transformation computation to provide tracking information for vehicle location control. The resulting system enables position and orientation tracking of objects in a reference coordinate system.

A method of operation of a navigation system includes: receiving an origin and a destination; receiving a route keyword for routing between the origin and the destination; identifying a via point matching the route keyword; calculating a keyword group locale based on the via point within a group distance threshold from a keyword group center; and calculating a travel route from the origin to the destination traversing the keyword group locale for displaying on a device.

A navigation system and various methods of using the system are described herein. Search query results are refined by the system and are prioritized based at least in part upon sub-search categories selected during the searching process. Sub-searches can be represented by graphical icons displayed on the user interface.

Provided are an apparatus and method of providing path information based on a status of a path and/or a purpose of the use of the path. A path information providing server collects environmental information from a sensing device. The path information providing server receives a path information request including a departure and a destination from a terminal device, and provides path information generated by mapping environmental data to a searched path.

An apparatus and method for determining an Absolute Location of an indoor stationary object, the method comprising: receiving a distance between an indoor stationary object and one or more predetermined spots; determining a location of stationary object relative to one of the predetermined spots; receiving an Absolute Location of one of the predetermined spots; determining an Absolute Location of the stationary object; and storing the Absolute Location of the stationary object with description information of the stationary object.

The present invention relates to a control system and a method for a hybrid vehicle which may optimally control the operating point of a vehicle. A control method for a hybrid vehicle includes detecting driving requests and a state of charge (SOC) of a battery when the vehicle is driving in HEV mode, determining a motor operating point and an engine operating point when the battery is in low SOC state, and compensating the motor operating point and the engine operating point by applying a climbing degree of the vehicle and the atmospheric pressure.

A parking assist system includes: an actuator that drives a back door of a vehicle; an opening degree control unit that controls an opening degree of the back door by controlling the actuator; a storage device that stores an allowable opening degree of the back door at a park position of the vehicle in association with the park position; and a position information acquisition unit that acquires position information of the vehicle. When a position of the vehicle corresponds to the park position stored in the storage device, the opening degree control unit limits the opening degree of the back door on the basis of the allowable opening degree of the back door, stored in the storage device in association with the park position.

In an electric powered vehicle in which vehicle driving force for reverse running is produced by a traction motor, vehicle driving force is set by a product of a base value set at least based on an accelerator opening and an amplification factor. The amplification factor is set at k1=1.0 during reverse running (V1.0 at the start of reverse running (V≧0) depending on the vehicular speed. The vehicle driving force at the start of reverse running can thereby be made larger than the vehicle driving force after the start of reverse running at the same accelerator opening.

A method of monitoring an engine coolant system includes modeling the total energy stored within an engine coolant. If an actual temperature of the engine coolant is below a minimum target temperature, the modeled total energy stored within the energy coolant is compared to a maximum stored energy limit to determine if sufficient energy exists within the engine coolant to heat the engine coolant to a temperature equal to or greater than the minimum target temperature. The engine coolant system fails the diagnostic check when the modeled total energy stored within the energy coolant is greater than the maximum stored energy limit, and the minimum target temperature has not been reached.

A traction control system in vehicle comprises a detector for detecting a monitored value which changes according to a degree of a drive wheel slip; a condition determiner for determining whether or not the monitored value meets a control start condition and whether or not the monitored value meets a control termination condition; and a controller for executing traction control to reduce a driving power of the drive wheel during a period of time from when the condition determiner determines that the monitored value meets the control start condition until the condition determiner determines that the monitored value meets the control termination condition; the condition determiner being configured to set at least the control start condition variably based on a slip determination factor which changes according to a vehicle state and such that the control start condition changes more greatly according to the vehicle state than the control termination condition.

A method of patterning a plurality of layers of a work piece in a series of writing cycles in one or a plurality of write machines, the workpiece being deviced to have a number of N layers and layers of the workpiece having one or a plurality of boundary condition(s) for pattern position, the method comprising the steps of: determining the boundary conditions of layers 1 to N, calculating deviations due to the boundary conditions and calculating a compensation for the deviation of the first transformation added with the assigned part of the deviation due to the boundary conditions.

Methods are provided to facilitate automated creation and management of design rule checking or DRC waiver descriptions. Embodiments include receiving a plurality of first checksums corresponding to respective first geometric element violations waived in association with a block of an integrated circuit design, the first checksums being based on a first version of at least one design verification rule and/or of the block, receiving a second checksum corresponding to a second geometric element violation associated with the block, the second checksum being based on a second version of the design verification rule and/or of the block, determining whether the second checksum corresponds to at least one of the first checksums, and, if the second checksum does not correspond to at least one first checksum, generating a waiver request for the second geometric element error.

A system, method, and computer program product for automatically generating equivalent assertions in different forms for different verification tools, which may be analog or digital. A user submits a set of logic assertions that, if unclocked, are converted to clocked assertions by generating and skewing clocks to ensure simulator uniformity. A stimulus is generated, perhaps at random, or input. A test bench is either input or synthesized. For each verification tool, the test bench is simulated and simulation results are captured. An assertion status difference engine evaluates result differences between the verification tools, and identifies and outputs differences indicating a significant inconsistency. Errors in verification tool implementation and user assertion coding can be detected. The simulators used may include SPICE and Verilog, or any other simulators that differ in type, simulation algorithm, input format, or vendor implementation.

One implementation of the disclosure provides a crosstalk analysis method executed by a computer. The method includes steps of: executing a layout program; executing a crosstalk analysis program; acquiring, by the crosstalk analysis program, a plurality of parameters from a layout result generated by the layout program; estimating a crosstalk value according to the parameters; determining whether the crosstalk value is larger than a predetermined value; providing a layout suggestion table when the crosstalk value is larger than the predetermined value.

A relationship between distance from a back bias control section which outputs a control signal for controlling a back bias of a transistor and an amount of noise in the control signal outputted from the back bias control section is found. An increase of jitter corresponding to the amount of the noise in a clock transmitted on a clock path connected to a circuit section (IP macro) is found on the basis of the relationship between the distance from the back bias control section and the amount of the noise. The circuit section and the clock path are placed on the basis of the increase of the jitter and an allowable jitter value for the circuit section.

A method of asymmetric asynchronous decoupling of capacitors in an integrated circuit design is provided for faster simulation by circuit simulators, e.g. FastSPICE circuit simulators. This method includes removing a coupling capacitor from a list, which includes coupling capacitors that capacitively couple two nets in the design. The two nets have capacitances C1 and C2, and at least one of capacitances C1 and C2 exceeds a threshold. The coupling capacitor has capacitance Cc. When coupling capacitance Cc is low and only one of capacitances C1 and C2 has a low capacitance, then a forward capacitance can be used at whichever of the two nets has the low capacitance and a lump capacitance can be used at the other net for simulation. When coupling capacitance Cc is low and both of capacitances C1 and C2 have high capacitances, then lump capacitances can be used at the two nets for the simulation.

A method includes providing a design of a semiconductor device such as a stacked CMOS device comprising a plurality of circuit elements to be assigned into a layout of a plurality of tiers, and identifying at least one first type of circuit element within the plurality of circuit elements based on at least one predetermined criterion. Each respective one of the at least one first type of circuit element is to be assigned to a respective designated one of the plurality of tiers. The method further includes dividing the remainder of the plurality of circuit elements into at least two groups of circuit elements based on circuit density, and assigning the at least one first type of circuit element and the at least two groups of circuit elements to respectively different ones of the plurality of tiers of the semiconductor device.

A method for designing a transformer in an integrated circuit includes receiving one or more desired characteristics of the transformer from user input and iteratively determining a design solution for the transformer through one or more simulations and modifications using a rule-set. The method combines the one or more desired characteristics with other preset characteristics of the transformer or the integrated circuit. A first model of the transformer is defined with typical load impedances and simulated having the combined characteristics to determine performance. Results of the simulation are processed to calculate performance with the load impedances specified by the user. The results are further processed to obtain a mathematical model that includes tuning capacitors. The first and subsequent models are modified by drawing on a rule-set of expert knowledge relating to general dependency of at least one design criterion, such as a physical, geometrical or performance characteristic, with another design criterion.

In a method for fracturing or mask data preparation or mask process correction for charged particle beam lithography, a plurality of shots are determined that will form a pattern on a surface, where shots are determined so as to reduce sensitivity of the resulting pattern to changes in beam blur (βf). In some embodiments, the sensitivity to changes in βf is reduced by varying the charged particle surface dosage for a portion of the pattern. Methods for forming patterns on a surface, and for manufacturing an integrated circuit are also disclosed, in which pattern sensitivity to changes in βf is reduced.

A via disposition information acquiring unit acquires via disposition information indicating a disposition of the plurality of first vias (212). A second conductor information acquiring unit acquires second conductor information indicating disposition positions of a plurality of second conductors (232) repeatedly disposed in the second conductor layer (230). A via extracting unit extracts an extraction via with respect to each of the plurality of second conductors (232). The extraction via is each of the first vias (212) overlapping the second conductor (232). A via selecting unit selects a selection via with respect to each of the plurality of second conductors (232). The selection via is each of first vias (212) selected in a predetermined number from the extraction vias. An opening introducing unit introduces a first opening (234) to each of the plurality of second conductors (232). The first opening (234) overlaps the extraction via not selected by the via selecting unit in plan view.

A method and apparatus for partitioning of the input design into repeating patterns called template cores for the application of reticle enhancement methods, design verification for manufacturability and design corrections for optical and process effects is accomplished by hierarchy analysis to extract cell overlap information. Also hierarchy analysis is performed to extract hierarchy statistics. Finally template core candidates are identified. This allows to the design to be made amenable for design corrections or other analyses or modifications that are able to leverage the hierarchy of the design since the cell hierarchy could otherwise be very deep or cells could have significant overlap with each other.

A method for mask data preparation or mask process correction is disclosed in which a set of charged particle beam shots is determined which is capable of forming a pattern on a surface, wherein critical dimension uniformity (CDU) of the pattern is optimized. In some embodiments the CDU is optimized by varying at least two factors. In other embodiments, model-based techniques are used. In yet other embodiments, the surface is a reticle to be used in an optical lithographic process to form a pattern on a wafer, and CDU on the wafer is optimized.

A mechanism for generating gate-level activity data for use in clock gating efficiency analysis of an integrated circuit (IC) design is provided. Generating the gate-level activity data includes generating a signal behaviour description for inter-register signals, generating a gate-level netlist for the IC design, generating gate-level stimuli based at least partly on the generated signal behaviour description, and performing gate-level simulation using the generated gate-level stimuli to generate gate-level activity data for the IC design. In one embodiment, generating the signal behaviour description includes performing Register Transfer Level (RTL) simulation of the IC design, and generating the gate-level netlist includes performing RTL synthesis. The RTL simulation and RTL synthesis are performed on RTL data for the IC design.

A system, method, and computer program product for containing analog verification IP for circuit simulation. Embodiments introduce analog verification units (“vunits”), and corresponding analog verification files to contain them. Vunits allow circuit design verification requirement specification via text file. No editing of netlist files containing design IP is required to implement static and dynamic circuit checks, PSL assertions, clock statements, or legacy assertions. Vunits reference a top-level circuit or subcircuits (by name or by specific instance), and the simulator automatically binds vunit contents appropriately during circuit hierarchy expansion. Vunits may be re-used for other design cells, and may be easily processed by text-based design tools. Vunits may be provided via vunit_include statements in a control netlist file, command line arguments, or by directly placing a vunit block into a netlist. Vunits may also contain instance statements to monitor or process signals, such as those needed by assertions.

A method and system for optical proximity correction (OPC) is disclosed in which a set of shaped beam shots is determined which, when used in a shaped beam charged particle beam writer, will form a pattern on a reticle, where some of the shots overlap, where the pattern on the reticle is an OPC-corrected version of an input pattern, and where the sensitivity of the pattern on the reticle to manufacturing variation is reduced. A method for fracturing or mask data preparation is also disclosed.

A circuit-design support method includes obtaining information for a circuit having a logic circuit in which signal lines are connected to input terminals, signals of the signal lines being output via the logic circuit; obtaining information concerning a control circuit that has a first flip-flop for scanning and that can control a value of a given signal line by a value set by the first flip-flop; selecting, based on the circuit information, a second flip-flop at an output destination of a signal from the logic circuit, among second flip-flops of the circuit; and generating, based on the control circuit information, information indicating a serial connection of the control circuit between an output source of the signal of the given signal line and the given signal line and a connection of a data input terminal of the first flip-flop and an output terminal of the selected second flip-flop.

Methods and systems are described for placing arithmetic operators on a programmable integrated circuit device (e.g., a PLD). Placement of arithmetic operators of a data flow graph in one of multiple regions (e.g., a region of DSP circuitry blocks or a region of logic fabric circuitry) on the programmable integrated circuitry device may be determined (e.g., randomly). A score related to the performance of the graph (e.g., a score related to data flow graph routing delays or area consumed by the data flow graph) may be determined and this process may be repeated after one of the arithmetic operators of the data flow graph is moved. The placement of arithmetic operators that corresponds to the best value for the score related to the performance of the data flow graph may be stored. Accordingly, more arithmetic operators may be included on a programmable integrated device than in conventional devices.

Disclosed are methods, systems, and articles of manufactures for implementing physical designs by using multiple force models to iteratively morph a layout decomposition. In addition to attractive force model(s) or repulsive force model(s), the physical implementation also uses a containment force model for grouping multiple design blocks or for confining a node of a cell within the boundary of a container. Another aspect is directed at deriving a first force model at the first hierarchical level from a second force model at the second hierarchical level by directly modifying the second model based at least in part on characteristic(s) of the first hierarchical level and of the second hierarchical level. In a design with multiple hierarchies, a cell-based force model is also used to ensure child nodes of a parent cell stay within a close proximity of the parent node of the parent cell.

The present invention is directed to provide a resist remover composition for semiconductor substrate which enables to remove a resist simply and easily in the photolithography process in the semiconductor field, and a method for removing a resist comprising that the composition is used. The present invention relates to a resist remover composition for semiconductor substrate, comprising [I] a carbon radical generating agent, [II] an acid, [III] a reducing agent, and [IV] an organic solvent, and having pH of lower than 7, and a method for removing a resist, comprising that the composition is used.

Resist stripping agents useful for fabricating circuits and/or forming electrodes on semiconductor devices for semiconductor integrated circuits and/or liquid crystals with reduced metal and metal alloy etch rates (particularly copper etch rates and TiW etch rates), are provided with methods for their use. The preferred stripping agents contain low concentrations of resorcinol or a resorcinol derivative, with or without an added copper salt, and with or without an added amine to improve solubility of the copper salt. Further provided are integrated circuit devices and electronic interconnect structures prepared according to these methods.

A new general purpose foaming agent having application as drilling fluid foaming agents or as any foaming agent needed an a wide variety of applications is disclosed, where the agent includes at least one anionic surfactant, at least one cationic surfactant, and mixtures thereof and one or more zwitterionic compounds. A method for using the foaming agent in capillary coiled tubing application is also disclosed. The foaming agents can also include additive to augment the properties of the foaming agent for a given application.

The invention relates to compositions including a hypohalite or hypochlorous acid and a soluble salt of 2,4,6 mesitylene sulfonate. The compositions may include a surfactant, a buffer, or combinations thereof. Other adjuvants may also be present. Such compositions do not require the inclusion of high concentrations of sodium hydroxide or other soluble hydroxide salts to drastically increase pH (and thus stability), although such hydroxides may be present if desired.

Methods employing detergent compositions effective for reducing soil redeposition and accumulation on hard surfaces are disclosed. The detergent compositions employ phosphinosuccinic acid adducts in combination with an alkalinity source and gluconic acid or salts thereof, copolymers of acrylic acid and maleic acids or salts thereof, sodium hypochlorite, sodium dichloroisocyanurate or combinations thereof.

This invention relates to extend the benefits of using hypochlorite compounds such as sodium hypochlorite to clean and disinfect articles while reducing or eliminating the side effects of treating an article with a strong oxidant material. The invention relates to a single step process involving mixing of precursor compositions of a suitable hypohalite or hypohalous acid with a solution of a reducing agent. Optionally a buffer may be present in either or both precursor compositions, such that at time of use such active hypohalous acid concentration in the resulting aqueous mixture remains at a sufficient activity level to effect one or more desired benefits against a target substrate for a desired period of time. The oxidant is substantially consumed by reaction with the reducing agent after the time needed for achieving the desired benefit has passed.

The present invention is directed to provide a semiconductor surface treating agent; composition which is capable of stripping an anti-reflection coating layer, a resist layer, and a cured resist layer in the production process of a semiconductor device and the like easily and in a short time, as well as a method for treating a semiconductor surface, comprising that the composition is used. The present invention relates to a semiconductor surface treating agent; composition, comprising [I] a compound generating a fluorine ion in water, [II] a carbon radical generating agent; , [III] water, [IV] an organic solvent, and [V] at least one kind of compound selected from a group consisting of hydroxylamine and a hydroxylamine derivative represented by the general formula [1], as well as a method for treating the semiconductor surface, comprising that the composition is used: (wherein R1 represents a linear, branched or cyclic C1-6 alkyl group, or a linear or branched C1-4 substituted alkyl group having 1 to 3 hydroxyl groups; R2 represents a hydrogen atom, a linear, branched or cyclic C1-6 alkyl group, or a linear or branched C1-4 substituted alkyl group having 1 to 3 hydroxyl groups).

Compositions and methods for treating biofilm formation and growth on a substrate are provided. The composition comprises 1 ppb to 1,000 ppm of at least one D-amino acid and 1 ppm to 60,000 ppm of at least one biocide. The method comprises contacting the substrate with 1 ppb to 1,000 ppm of at least one D-amino acid and 1 ppm to 60,000 ppm of at least one biocide. The compositions and methods are effective for preventing, reducing or eliminating biofilm formation or biofilm growth or both, as well as eradicating established, recalcitrant biofilms, particularly biofilms comprising sulfate reducing bacteria that are known to cause microbiologically influenced corrosion, biofouling, or both.

A cleansing composition for cleansing skin, especially for removing grease from skin. A cleaning composition of the present invention may also be used in ready-to-use (or in-use) kits, such as two component kits, suitable for cleansing skin.

The invention relates to compositions, methods of use, and methods of manufacture for an intercalated bleach compound and compositions thereof. The intercalated bleach compound has the formula Mx(OCl)y(O)m(OH)n where M is an alkaline earth metal such as magnesium, calcium or mixture thereof. The values of x and y independently equal any number greater than or equal to 1 (e.g., 1, 2, 3, 4, etc.), and m and n independently equal any number greater than or equal to 0 (e.g., 0, 1, 2, 3, 4, etc.), but m and n are not both 0. In addition, the molar ratio of the alkaline earth metal (e.g., magnesium or calcium) to hypochlorite is at least 3:1. In other words, x is ≧3y. The compounds exhibit excellent stability, little or no chlorine bleach odor, exhibit excellent pH buffering characteristics, and less reactivity with organic materials as compared to alternative chlorine bleach products.

A mixture of surfactants from alkylene oxide adducts with different degrees of alkoxylation is used in a urea solution to be added to an exhaust stream for reduction of nitrous gases.

Provided is a method of manufacturing a superconducting accelerator cavity in which a plurality of half cells having opening portions (equator portions and iris portions) at both ends thereof in an axial direction are placed one after another in the axial direction, contact portions where the corresponding opening portions come into contact with each other are joined by welding, and thus, a superconducting accelerator cavity is manufactured, the half cells to be joined are arranged so that the axial direction thereof extends in a vertical direction; and concave portions that are concave towards an outer side are also formed at inner circumferential surfaces located below the contact portions of the half cells positioned at a bottom; and the contact portions are joined from outside by penetration welding.

An apparatus and method for moving a wire along its own axis against a high resistance to its motion causing a substantial uniaxial compression stress in the wire without allowing it to buckle. The apparatus consists of a wire gripping and moving drive wheel and guide rollers for transporting the moving wire away from the drive wheel. Wire is pressed into a peripheral groove in a relatively large diameter, rotating drive wheel by a set of small diameter rollers arranged along part of the periphery causing the wire to be gripped by the groove.

The present disclosure relates to a superconducting rotating electrical machine and a manufacturing method for a high temperature superconducting film thereof. The superconducting rotating electrical machine includes a stator, and a rotor rotatable with respect to the stator, the rotor having a rotary shaft and a rotor winding. Here, the rotor winding includes tubes disposed on a circumference of the rotary shaft and each forming a passage for a cooling fluid therein, superconducting wires accommodated within the tubes, and a cooling fluid flowing through the inside of the tubes. This configuration may allow for direct heat exchange between the superconducting wires and a refrigerant, resulting in improvement of heat exchange efficiencies of the superconducting wires.

Disclosed are an oxide superconductor tape and a method of manufacturing the oxide superconductor tape capable of improving the length and characteristics of superconductor tape and obtaining stabilized characteristics across the entire length thereof. A Y-class superconductor tape (10), as an oxide superconductor tape, comprises a tape (13) further comprising a tape-shaped non-oriented metallic substrate (11), and a first buffer layer (sheet layer) (12) that is formed by IBAD upon the tape-shaped non-oriented metallic substrate (11); and a second buffer layer (gap layer) (14), further comprising a lateral face portion (14a) that is extended to the lateral faces of the first buffer layer (sheet layer) (12) upon the tape (13) by RTR RF-magnetron sputtering.

A method for manufacturing a base material 2 for a superconductive conductor which includes: a conductive bed layer forming process of forming a non-oriented bed layer 24 having conductivity on a substrate 10; and a biaxially oriented layer forming process of forming a biaxially oriented layer 26 on the bed layer 24.

A superconducting magnet device is configured to include: a refrigerant circulation flowpath in which a refrigerant (R) circulates; a refrigerator for cooling vapor of the refrigerant (R) in the refrigerant circulation flowpath; a superconducting coil cooled by the circulating refrigerant (R); a protective resistor thermally contacting the superconducting coil and having an internal space (S); a high-boiling-point refrigerant supply section for supplying a high-boiling-point refrigerant having a higher boiling point than the refrigerant (R) and frozen by the refrigerant (R) to the internal space (S) in the protective resistor; and a vacuum insulating container for at least accommodating the refrigerant circulation flowpath, the superconducting coil, and the protective resistor.

Provided are a substrate for a superconducting compound and a method for manufacturing the substrate which can realize the excellent adhesive strength simultaneously with high orientation of copper. An absorbed material on a surface of a copper foil to which rolling is applied at a draft of 90% or more is removed by applying sputter etching to the surface of the copper foil, sputter etching is applied to a nonmagnetic metal sheet, the copper foil and the metal sheet are bonded to each other by applying a pressure to the copper foil and the metal sheet using reduction rolls, crystals of the copper in the copper foil are oriented by heating a laminated body formed by such bonding, copper is diffused into the metal sheet by heating with a copper diffusion distance of 10 nm or more, and a protective layer is laminated to a surface of the copper foil of the laminated body.

Disclosed is a splicing method of two second-generation ReBCO high temperature superconductor coated conductors (2G ReBCO HTS CCs), in which, with stabilizing layers removed from the two strands of 2G ReBCO HTS CCs through chemical wet etching or plasma dry etching, surfaces of the two high temperature superconducting layers are brought into direct contact with each other and heated in a splicing furnace in a vacuum for micro-melting portions of the surfaces of the high temperature superconducting layers to permit inter-diffusion of ReBCO atoms such that the surfaces of the two superconducting layers can be spliced to each other and oxygenation annealing for recovery of superconductivity which was lost during splicing.

A tape-shaped superconducting film-forming substrate is disclosed, which includes a film-forming face for forming a laminate including a superconducting layer thereon, a rear face that is a face at a side opposite to the film-forming face, a pair of end faces connected to the film-forming face and the rear face, and a pair of side faces connected to the film-forming face, the rear face, and the pair of end faces, in which each of the pair of side faces includes a spreading face that spreads toward an outer side in an in-plane direction of the film-forming face from an edge part of the film-forming face toward the rear face side. A superconducting wire and a superconducting wire manufacturing method are also disclosed.

An electrochemical finishing system for super conducting radio frequency (SCRF) cavities including a low viscosity electrolyte solution that is free of hydrofluoric acid, an electrode in contact with the electrolyte solution, the SCRF cavity being spaced apart from the electrode and in contact with the electrolyte solution and a power source including a first electrical lead electrically coupled to the electrode and a second electrical lead electrically coupled to the cavity, the power source being configured to pass an electric current between the electrode and the workpiece, wherein the electric current includes anodic pulses and cathodic pulses, and wherein the cathodic pulses are interposed between at least some of the anodic pulses. The SCRF cavity may be vertically oriented during the finishing process.