GCVI Summit, Monterey – 29-30 January 2020

Cohen recognized for the 2019 Zero Lost Time Accident Achievement for Manufacturers Award for reaching more than 100,000 work hours without a safety incident.

Follow ISA Cybersecurity Inc. on Social Media for a Chance to Win a Pair of 2019 Toronto Maple Leafs Tickets

Summit Design & Build is happy to announce that Architectural Digest magazine is featuring their company in the February 2020 issue.

Meet the Architects and Designers Responsible for Some of San Diego's Most Enviable Homes

Mr. Kinnear lends years of expertise to commercial, institutional and residential projects throughout the United States

Translucent panels provide both daylight and insulation

Mr. Hlavac provides years of expertise in construction to his current executive position with Helm Equities LLC

Mr. Beer was the Founding Partner of Brennan Beer Gorman Architects and Brennan Beer Gorman Monk Interiors for 20 years prior to his retirement in 2015

It's been an exciting year for author and outdoorsman, Kennon Ward D.D., with several trips to Ukraine under his belt, the debut of his official website, a full-scale Times Square ad campaign, and a sure-fire bestseller that just hit Amazon.

www.chrisflach.com

This hands-on book bridges the gap between theory and practice, showing you the math of deep learning algorithms side by side with an implementation in PyTorch. You can save 40% off Math and Architectures of Deep Learning until May 13! Just enter the code nlkdarch40 at checkout when you buy from manning.com.

Daniel Libeskind, a former academic turned architect and urban designer, discusses his unorthodox career path and repeat success at high-profile, emotionally charged projects. He also talks about his unusual creative process and shares tips for collaborating and managing emotions and expectations of multiple stakeholders. Libeskind was interviewed for the July-August 2018 issue of Harvard Business Review.

Stories are everywhere. When they don’t exist we make up the narrative — we join the dots. We make cognitive leaps and fill in the bits of a story that are implied or missing. The same goes for websites. We make quick judgements based on a glimpse. Then we delve deeper. The narrative unfolds, or we create one as we browse.

Mark Bernstein penned Beyond Usability and Design: The Narrative Web for A List Apart in 2001. He wrote, ‘the reader’s journey through our site is a narrative experience’. I agreed wholeheartedly: Websites are narrative spaces where stories can be enacted, or emerge.

Henry Jenkins, Director of Comparative Media Studies, and Professor of Literature at MIT, wrote Game Design as Narrative Architecture. He suggested we think of game designers, ‘less as storytellers than as narrative architects’. I agree, and I think web designers are narrative architects, too. (Along with all the multitude of other roles we assume.) Much of what Henry Jenkins wrote applies to modern web design. In particular, he describes two kinds of narratives in game design that are relevant to us:

Enacted narratives are those where:

[…] the story itself may be structured around the character’s movement through space and the features of the environment may retard or accelerate that plot trajectory.

Sites like Amazon, New Adventures, or your portfolio are enacted narrative spaces: Shops or service brochures that want the audience to move through the site towards a specific set of actions like buying something or initiating contact.

Emergent narratives are those where:

[…] spaces are designed to be rich with narrative potential, enabling the story-constructing activity of players.

Sites like Flickr, Twitter, or Dribbble are emergent narrative spaces: Web applications that encourage their audience use the tools at their disposal to tell their own story. The audience defines how they want to use the narrative space, often with surprising results.

We often build both kinds of narrative spaces. Right now, my friends and I at Analog are working on Mapalong, a new maps-based app that’s just launched into private beta. At its heart Mapalong is about telling our stories. It’s one big map with a set of tools to view the world, add places, share them, and see the places others share. The aim is to help people tell their stories. We want to use three ideas to help you do that: Space (recording places, and annotating them), data (importing stuff we create elsewhere), and time (plotting our journeys, and recording all the places, people, and memories along the way). We know that people will find novel uses for the tools in Mapalong. In fact, we want them to because it will help us refine and build better tools. We work in an agile way because that’s the only way to design an emerging narrative space. Without realising it we’ve become architects of a narrative space, and you probably are, too.

Many projects like shops or brochure sites have fixed costs and objectives. They want to guide the audience to a specific set of actions. The site needs to be an enacted narrative space. Ideally, designers would observe behaviour and iterate. Failing that, a healthy dose of empathy can serve. Every site seeks to teach, educate, or inform. So, a bit of knowledge about people’s learning styles can be useful. I once did a course in one to one and small group training with the Chartered Institute of Personnel and Development. It introduced me to Peter Honey and Alan Mumford’s model which describes four different learning styles that are useful for us to know. I paraphrase:

1. Activists like learning as they go; getting stuck in and working it out. They enjoy the here and now, and are happy to be dominated by immediate experiences. They are open-minded, not sceptical, and this tends to make them enthusiastic about anything new.
2. Reflectors like being guided with time to take it all in and perhaps return later. They like to stand back to ponder experiences and observe them from many different perspectives. They collect data, both first hand and from others, and prefer to think about it thoroughly before coming to a conclusion.
3. Theorists to understand and make logical sense of things before they leap in. They think problems through in a vertical, step-by-step logical way. They assimilate disparate facts into coherent theories.
4. Pragmatists like practical applications of ideas, experiments, and results. They like trying out ideas, theories and techniques to see if they work in practice. They positively search out new ideas and take the first opportunity to experiment with applications.

Usually people share two or more of these qualities. The weight of each can vary depending on the context. So how might learning styles manifest themselves in web browsing behaviour?

• Activists like to explore, learn as they go, and wander the site working it out. They need good in-context navigation to keep exploring. For example, signposts to related information are optimal for activists. They can just keep going, and going, and exploring until sated.
• Reflectors are patient and thoughtful. They like to ponder, read, reflect, then decide. Guided tours to orientate them in emergent sites can be a great help. Saving shopping baskets for later, and remembering sessions in enacted sites can also help them.
• Theorists want logic. Documentation. An understanding of what the site is, and what they might get from it. Clear, detailed information helps a theorist, whatever the space they’re in.
• Pragmatists get stuck in like activists, but evaluate quickly, and test their assumptions. They are quick, and can be helped by uncluttered concise information, and contextual, logical tools.

An understanding of interactive narrative types and a bit of knowledge about learning styles can be useful concepts for us to bear in mind. I also think they warrant inclusion as part of an articulate designer’s language of web design. If Henry Jenkins is right about games designers, I think he could also be right about web designers: we are narrative architects, designing spaces where stories are told.

—∞—

Deep neural networks have exhibited promising performance in image super-resolution (SR). Most SR models follow a hierarchical architecture that contains both the cell-level design of computational blocks and the network-level design of the positions of upsampling blocks. However, designing SR models heavily relies on human expertise and is very labor-intensive. More critically, these SR models often contain a huge number of parameters and may not meet the requirements of computation resources in real-world applications. To address the above issues, we propose a Hierarchical Neural Architecture Search (HNAS) method to automatically design promising architectures with different requirements of computation cost. To this end, we design a hierarchical SR search space and propose a hierarchical controller for architecture search. Such a hierarchical controller is able to simultaneously find promising cell-level blocks and network-level positions of upsampling layers. Moreover, to design compact architectures with promising performance, we build a joint reward by considering both the performance and computation cost to guide the search process. Extensive experiments on five benchmark datasets demonstrate the superiority of our method over existing methods.

Passive optical networks (PON) can play a vital role in data centres and access fog solutions by providing scalable, cost and energy efficient architectures. This paper proposes a Mixed Integer Linear Programming (MILP) model to optimize the placement of virtual machines (VMs) over an energy efficient WDM-TDM AWGR PON based data centre architecture. In this optimization, the use of VMs and their requirements affect the optimum number of servers utilized in the data centre when minimizing the power consumption and enabling more efficient utilization of servers is considered. Two power consumption minimization objectives were examined for up to 20 VMs with different computing and networking requirements. The results indicate that considering the minimization of the processing and networking power consumption in the allocation of VMs in the WDM-TDM AWGR PON can reduce the networking power consumption by up to 70% compared to the minimization of the processing power consumption.

Sparse models require less memory for storage and enable a faster inference by reducing the necessary number of FLOPs. This is relevant both for time-critical and on-device computations using neural networks. The stabilized lottery ticket hypothesis states that networks can be pruned after none or few training iterations, using a mask computed based on the unpruned converged model. On the transformer architecture and the WMT 2014 English-to-German and English-to-French tasks, we show that stabilized lottery ticket pruning performs similar to magnitude pruning for sparsity levels of up to 85%, and propose a new combination of pruning techniques that outperforms all other techniques for even higher levels of sparsity. Furthermore, we confirm that the parameter's initial sign and not its specific value is the primary factor for successful training, and show that magnitude pruning cannot be used to find winning lottery tickets.

Efficient computation of complex multiplication results and very efficient fast Fourier transforms (FFTs) are provided. A parallel array VLIW digital signal processor is employed along with specialized complex multiplication instructions and communication operations between the processing elements which are overlapped with computation to provide very high performance operation. Successive iterations of a loop of tightly packed VLIWs are used allowing the complex multiplication pipeline hardware to be efficiently used. In addition, efficient techniques for supporting combined multiply accumulate operations are described.

An adaptable integrated circuit is disclosed having a plurality of heterogeneous computational elements coupled to an interconnection network. The interconnection network changes interconnections between the plurality of heterogeneous computational elements in response to configuration information. A first group of computational elements is allocated to form a first version of a functional unit to perform a first function by changing interconnections in the interconnection network between the first group of heterogeneous computational elements. A second group of computational elements is allocated to form a second version of a functional unit to perform the first function by changing interconnections in the interconnection network between the second group of heterogeneous computational elements. One or more of the first or second group of heterogeneous computational elements are reallocated to perform a second function by changing the interconnections between the one or more of the first or second group of heterogeneous computational elements.

A method of monitoring thread execution within a multicore processor architecture which comprises a plurality of interconnected processor elements for processing the threads, the method comprising receiving a plurality of thread parameter indicators of one or more parameters relating to the function and/or identity and/or execution location of a thread or threads, comparing at least one of the thread parameter indicators with a first plurality of predefined criteria each representative of an indicator of interest, and generating an output consequential upon thread parameter indicators which have been identified to be of interest as a result of the said comparison.

A microprocessor capable of running both x86 instruction set architecture (ISA) machine language programs and Advanced RISC Machines (ARM) ISA machine language programs. The microprocessor includes a mode indicator that indicates whether the microprocessor is currently fetching instructions of an x86 ISA or ARM ISA machine language program. The microprocessor also includes a plurality of model-specific registers (MSRs) that control aspects of the operation of the microprocessor. When the mode indicator indicates the microprocessor is currently fetching x86 ISA machine language program instructions, each of the plurality of MSRs is accessible via an x86 ISA RDMSR/WRMSR instruction that specifies an address of the MSR. When the mode indicator indicates the microprocessor is currently fetching ARM ISA machine language program instructions, each of the plurality of MSRs is accessible via an ARM ISA MRRC/MCRR instruction that specifies the address of the MSR.

A framework for implementing multitenant architecture is provided. The framework comprises a framework services module which is configured to provide framework services that facilitate abstraction of Software-as-a-Service (SaaS) services and crosscutting services for a Greenfield application and a non SaaS based web application. Further the abstraction results in a SaaS based multitenant web application. The framework further comprises a runtime module configured to automatically integrate and consume the framework services and APIs to facilitate monitoring and controlling of features associated with the SaaS based multitenant web application. The framework further comprises a metadata services module configured to provide a plurality of metadata services to facilitate abstraction of storage structure of metadata associated with the framework and act as APIs for managing the metadata. The framework further comprises a role based administration module that facilitates management of the metadata through a tenant administrator and a product administrator.

The present invention relates generally to client-server architectures for allowing generic upload and download functionality between a web application at a server and a client. One exemplary method includes sending a download/upload request to a web application at the server, where the download/upload request specifies at least one file to download/upload; receiving a transmission from the server; parsing the transmission to identify a download/upload command and an associated download/upload manifest, where the download/upload manifest includes executable code that, when executed on the client, will perform the download/upload of the at least one file.

A system and method for implementing a dynamic menu characterized by a real-time menu architecture. An example method includes determining a menu structure, with reference to a data set, for use with user interface software. A menu is then displayed, wherein the menu includes menu items arranged according to the menu structure. An initial drop-down menu list of the menu includes one or more of the menu items. Each menu item is associated with a data object of the data set. A signal is generated when a change is made to a data set corresponding to a menu item. The menu is then updated based on the signal. In an illustrative embodiment, the example method further includes employing a browser to trigger implementation of the method. The browser communicates with a web server, which communicates with an application that is adapted to analyze the data set and associated data structure and provide an update in response thereto via, the signal, to the web server. The web server includes software for enabling the browser to render an updated menu or graphical representation thereof.

The present invention provides an acrylic resin composition containing a polycrystal of colloidal particles of silicon oxide in an acrylic resin that is formed by curing an acrylic monomer liquid at room temperature and/or an acrylic oligomer liquid at room temperature, wherein a mean distance between the colloidal particles in the polycrystal is 140 to 330 nm. The size of the single crystal that constitutes the polycrystal can be controlled by adjusting the content of silicon oxide and/or the additive amount of impurities. An architectural material, a fashion accessory, and an optical material are provided that are formed by using the acrylic resin composition.

The present invention relates to methodology and constructs for modifying plant architecture and enhancing plant biomass and/or sucrose yield.

Apparatus and method for secure transactions between gaming machines and portable devices are described. The secure transactions may include a transfer of an amount of an indicia of credit with a cash value from the portable device to the gaming machine or a transfer of an amount of an indicia of credit with a cash value from the gaming machine to the portable device. A logic device, separate from a master gaming controller on the gaming machine and placed in the gaming machine, may be operable to authenticate a portable device, such as a smart card, and authorize transactions involving transfers of indicia of credit between the portable device and the gaming machine. The logic device may be operable to send authentication information relating to the portable device to a remote host where a value amount of transactions involving the portable device authorized by the logic device may be higher when the logic device and the remote host authenticate the portable device as opposed to when the portable is only authenticated by the logic device.

The architecture includes a passive radar using opportunistic transmitters and a plurality of active radars that cooperate in the form of a coalition to assure the surveillance of an area of space. The passive radar and the active radars that form the architecture include means for exchanging information and the passive radar is configured to adopt two alternate operating modes: (i) a “watching” mode in which the passive radar carries out surveillance of the area of space concerned and generates detection information, and (ii) an “on-demand data feed” mode in which the passive radar executes at the request of one or more active radars an object search in a given sector of the area under surveillance or an analysis of certain characteristics of the signal received in a given sector.

An optical gain architecture includes a pump source and a pump aperture. The architecture also includes a gain region including a gain element operable to amplify light at a laser wavelength. The gain region is characterized by a first side intersecting an optical path, a second side opposing the first side, a third side adjacent the first and second sides, and a fourth side opposing the third side. The architecture further includes a dichroic section disposed between the pump aperture and the first side of the gain region. The dichroic section is characterized by low reflectance at a pump wavelength and high reflectance at the laser wavelength. The architecture additionally includes a first cladding section proximate to the third side of the gain region and a second cladding section proximate to the fourth side of the gain region.

One of the most important RF building blocks today is the frequency synthesizer, or more particularly the programmable frequency divider (divider). Such dividers preferably would support unlimited range with continuous division without incorrect divisions or loss of PLL lock. The inventors present multi-modulus dividers (MMDs) providing extended division range against the prior art and without incorrect divisions as the division ratio is switched back and forth across the boundary between two different ranges. Accordingly, the inventors present MMD frequency dividers without the drawbacks within the prior art.

Magnetoelectronic (ME) logic circuits and methods of operating the same are disclosed. Microsystems of different circuits made from different types of ME devices can be constructed and employed in applications such as sensors, smart dust, etc.

A floorplan for a Structured ASIC chip is shown having a core region containing memory and VCLB logic cells surrounded by a plurality of IO connection fabrics that include a first IO connection fabric comprising IO sub-banks connecting the core of the chip to pins for external signals to the core, a first high-speed routing fabric disposed along the east-west vertical top of the core and connects the core to high-speed IO such as SerDes; a network-aware connection fabric connects the core to a microcontroller primarily for testing and repair of the memory in the core; and a second-high speed routing fabric is disposed on the north-south vertical sides of the core and communicates with the IO sub-banks. The VCLB Structured ASIC chip is manufactured on a 28 nm CMOS process lithographic node or smaller, having several metal layers and preferably is programmed on a single via layer.

A resonant clock distribution network architecture is proposed that enables a resonant clock network to track the impact of parameter variations on the insertion delay of a conventional clock distribution network, thus limiting clock skew between the two networks and yielding increased performance. Such a network is generally applicable to semiconductor devices with various clock frequencies, and high-performance and low-power clocking requirements such as microprocessors, ASICs, and SOCs.

A generator system includes a generator having a stationary portion and a rotating portion. The generator includes a permanent magnet based exciter with permanent magnets disposed on the stationary portion. A first channel includes a first main field winding and a first main field power converter disposed on a rotating portion. The first main field power converter selectively delivers voltage from the exciter winding to the first main field winding. A second channel includes a second main field winding and a second main field power converter disposed on the rotating portion. The second main field power converter selectively delivers voltage from the exciter winding to the second main field winding. A generator control unit is connected to the first channel and the second channel. The generator control unit monitors an output voltage at each of the first channel and the second channel and generates the first and second control signals based on the output voltage.

An electric power generation system (EPGS) employs both a wild-source generator and a variable and/or constant frequency generator. The wild-source generator is coupled to receive mechanical power from a low-pressure spool on an aircraft engine and to generate in response a wild-source output for consumption by voltage and frequency-tolerant loads. The variable and/or constant frequency generator is coupled to receive mechanical power from a high-pressure spool on the aircraft engine and to generate in response a variable and/or constant frequency output for consumption by voltage and frequency-intolerant loads.

White-pigmented and unpigmented base paints and stains are custom-tinted using an automated colorant dispenser having a minimum fluid dispensing quantity less than 0.01 fluid ounce (

A tubular fibrous architecture is disclosed. According to one aspect, the tubular fibrous architecture includes a closed tubular part in at least one of its ends or bottom. The closed tubular part includes an architecture in which a textile material, such as a thread, roving, ribbon or bundle of threads, is continuously output from the bottom. Each textile material that is output from the bottom is continuously wound about the tubular part. All of the textile materials at the junction between the bottom and the remainder of the tubular part are continuous and there is a continuous geometric transition between the bottom architecture and the architecture of the remainder of the tubular part such that the textile materials in the tubular part cross over. A method of making such a tubular fibrous architecture is also disclosed.

A gas turbine engine includes a geared architecture with a multiple of intermediate gears, and a baffle with an oil scavenge scoop adjacent to each of the multiple of intermediate gears. A geared architecture and method are also disclosed.

An interconnect switch is provided including switching logic executable to facilitate a Peripheral Component Interconnect Express (PCIe)-based interconnect, and further including a control host embedded in the switch to provide one or more enhanced routing capabilities. The control host includes a processor device, memory, and software executable by the processor device to process traffic received at one or more ports of the switch to redirect at least a portion of the traffic to provide the one or more enhanced routing capabilities.

A communication system with train bus architecture is described. The communication system with the train bus architecture comprises a coupling device for transmitting a first instruction packet string having instruction packets via first path; the controlled module for receiving the first instruction packet string via first path, wherein the controlled module selects one instruction packet from the instruction packets, replaces the selected instruction packet by first response packet for forming second instruction packet string, and processes the selected instruction packet to generate a second response packet; and a terminal device for receiving the second instruction packet string via the first path, and for transmitting the second instruction packet string back to the coupling device via the at least one controlled module along a second path from the terminal device to the coupling device wherein the first path is connected to the second path to form train bus architecture.

A method for managing avionic data between a flight management system FMS and one or more clients, the FMS comprising resources accessible through avionic services Ci (1,n); the execution of the Ci (1,n) determining an avionic functionality Fj (1,m); each of the Fj (1,m) associated with an intrusiveness parameter Ik and a criticality parameter Ck; the method comprises the steps of receiving a request specifying the call to an Fj (1,m); and determining a predefined execution right for a Ci (1,n), dependent on the predefined intrusiveness and/or criticality parameters associated with the Fj (1,m). Developments describe particularly the comparison of the execution rights, notice of a rejection, various avionic services and functionalities, the management of criticality ranges, consideration of the flight context, etc. Software and system aspects are described (e.g. equipment of EFB type).

A spring motor and drag brake for use in coverings for architectural openings.

A system for attaching a shade material to a roller having recesses in its surface includes inserting portions of the shade material into an associated elongated recess and retaining the material in the recess with an attachment member having peaks and valleys along its length for intermittent engagement with the material within the recess.

A programmable memory including a self-latching read data path. A sense amplifier senses the voltage level at a bit line, the bit line communicating the data state of a selected memory cell in its associated column. A data latch coupled to the output of the sense amplifier passes the sensed data state. Set-reset logic is provided that receives the output of the data latch in the read data path and, in response to a transition of the data state in a read cycle, latches the data latch and isolates it from the sense amplifier. The set-reset logic resets the data latch at the start of the next read cycle. In some embodiments, a timer is provided so that the latch is reset after a time-out period in a long read cycle in which no data transition occurs.

A bit line architecture for dual-port static random-access memory (DP SRAM) is provided. An array of memory cells is arranged in rows and columns, and comprises a first subarray and a second subarray. A first pair of complementary bit lines (CBLs) extends along a column, from a first side of the array, and terminates between the first and second subarrays. A second pair of CBLs extends from the first side of the array, along the column, to a second side of the array. The CBLs of the second pair of CBLs have stepped profiles between the first and second subarrays. A third pair of CBLs and a fourth pair of CBLs extend along the column. The first and third pairs of CBLs electrically couple to memory cells in the first subarray, and the second and fourth pairs of CBLs electrically couple to memory cells in the second subarray.

An apparatus includes an integrated circuit (IC). The IC includes a power controller, which includes a regulator and a controller. The regulator receives a plurality of input voltages and provides a regulated output voltage. The controller controls the regulator to generate the regulated output voltage from the plurality of input voltages. The power controller provides power to a load integrated in the IC from a set of arbitrary input voltages. The set of arbitrary input voltages includes the plurality of input voltages.

San Francisco's urban landscape has evolved significantly over the last decade. City Visions host Joseph Pace and our panel review some of the decade's most notable - and controversial - development projects.

Donald Trump began his Presidential bid, in 2015, with an infamous speech, at Trump Tower, in which he said of Mexican immigrants, “They’re bringing drugs. They’re bringing crime. They’re rapists.” But it was not until a former aide to Jeff Sessions joined Trump’s campaign that the nativist rhetoric coalesced into a policy platform—including the separation of children from their families at the border. Jonathan Blitzer, who writes about immigration for The New Yorker, has been reporting on Stephen Miller’s sway in the Trump Administration and his remarkable success in advancing an extremist agenda. “There has never been an American President who built his campaign around the issue of immigration and later won on that campaign on immigration. Trump was the first and only President really ever to do it,” Blitzer tells David Remnick. Despite this influence, Miller remains largely behind the scenes. Blitzer explains why: “He knows that the kiss of death in this Administration is to be identified as the brains behind the man. He can’t let on that he’s the one who effectively is manipulating Trump on these issues.” 

Implementing Cisco Enterprise Network Core Technologies v1.0 (ENCOR 350-401) is a 120-minute professional-level exam associated with the CCNP and CCIE Enterprise Infrastructure certifications. The exam tests a candidate's knowledge of implementing core enterprise network technologies. This course helps candidates to prepare for the first three domains of this exam: Architecture, Virtualization, and Infrastructure. Instructors Kevin Wallace and Charles Judd show how to design enterprise architecture, including planning for all the necessary services and capacity. They also cover the various types of virtualization, from virtual machines and switches to entire virtual networks, and review the infrastructure technologies you typically see in enterprise networks, such as MSTP and RSTP, IPv4 and IPV6 routing, WLANs, Dynamic NAT, and more.

This course was created by Kevin Wallace Training. We are pleased to offer this training in our library.