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Hi,

I am doing layout for a mixed-signal circuit in Innovus. I want to create a digital donut style of layout (i.e. put analog circuit in the middle, and circle analog part with digital circuits).

To do that, I need to place some pins inside the edge to connect to analog circuit (as shown in my attachment), but the problems is that I cannot place pins inside the edge by using "pin editor" within Innovus. Any suggestions to place pins inside?

Thank you so much for your time and effort.

Hi,

Is it possible to use a SystemVerilog package which is compiled into a library and then use it in a VHDL-2008 design file? Is such mixed-language flow supported?

I'm considering the latest versions of Incisive / Xcelium available today (Oct 2019).

Thank you,

Michal

The IEEE has announced the publication of the new 1801-2013 standard, also known as UPF 2.1, and immediate availability for free download through the IEEE 1801-2013 Get Program. Even though the standard is new to the whole world, for the people of the IEEE working group this standard is finally done and is in the past now.

There is a Chinese saying "好事多磨" which means "good things take time to happen." I forgot the exact time when I first joined the working group for the new standard -- about two and half years ago -- but I do remember long hours of meetings and many "lively" debates and discussions. Since the "hard time" has passed us, I would like to share some fun facts about the working group and the standard.

• The 1801 working group is the largest entity based ballot group in IEEE-SA history.
• The new standard was initially planned for 2012, but was delayed purely due to the large amount of work required.
• At one point, the group was debating on whether the new standard should be called UPF 2.1 or 3.0. It may sound weird now but we spent quite some time discussing this. Eventually we settled on 2.1 as it was the original plan.
• The 1801-2013 document has 358 pages which is 53% thicker than previous version (the sheer amount of changes in the new standard indicate that this is more than just a normal incremental update of the previous version as suggested by naming it 2.1)
• Around 300 real issues were reported over the previous version and a majority of them were fixed in the new release.
• This is the first release with constructs and semantics coming from Common Power Format (CPF), a sign of convergence of the two industry leading power formats.
• There are about 100 working group meetings in my Outlook calendar since 2011, with meeting times ranging from 2 hours to 8 hours.
• We extensively used Google Drive (which was called Google Docs when the working group started), a great tool for productivity. I cannot imagine how any standard could have been done before Google existed!

Personally, I had an enjoyable journey, especially from having the privilege to work with many industry experts who are all passionate about low power. I do have one more thing to share though. My older daughter went from middle school to high school during the period of the development of the new standard. Since most of the meetings took place in the early morning California time, she had to endure the pain of listening to all these discussions on power domain, power switches, etc. on her way to school.

I asked her if she learned anything. She told me that other than being able to recognize the voices of Erich, John and Joe on the line, she also learned that she would never want to become an electrical or computer engineer! She was so happy that the meetings stopped a couple of months ago. But what I did not tell her is that the meetings will resume after DAC! Well, I am sure this will be a big motivation for her to get her own driving license in the summer.

If you want to get some quick technical insights into the new standard, check out my recent EE Times article IEEE 1801-2013: A bold step towards power format convergence.

Qi Wang

Hello, I have a problem with a certain type of transistor,my hyrarchy has a lot components an sub components and visually inspecting them is very hard.

is there a way like in other cadence layout viewer tools , to enter the name of the component or a NET somewhere and it will focus on it visualy or give the hyrarchy path to it?

Thanks.