An anti-plastic campaign directed at the Britain's most beloved crisp company is leading to changes in packaging and recycling.

Quick and easy chocolate chip cookie recipe.

AppoTech announces dual mode Bluetooth chipset CW6691P now supports world's smallest heart rate sensing solution (ActivHearts) from WBD101 for the hearable market

Validates DeviceLab's Expertise in Electronic Medical Device Design

The ST-1803 Sports Hearable uses the World's Smallest Heart Rate Sensing Earbud Technology from WBD101

WBD101's Second Generation 2-in-1 SBS2000 chip used by Kan Tsang New Technology Development (Kan Tsang) for True Wireless Stereo (TWS300HR) Earbuds

Automotive Review Co. has conducted a randomized and unedited survey which asked over 800 randomly selected customers about the experience they have had with the Supreme Performance Chip 4.0 as well as the company Great Lakes Auto

Chip Evans said that the innovative design was focused on usability and improved client interaction.

Chip seal projects are scheduled to begin at Grand Canyon National Park on both the South and North Rims. https://www.nps.gov/grca/learn/news/17jun10_news.htm

A chip seal project that began last summer on the South Rim of Grand Canyon National Park will be completed early this summer. https://www.nps.gov/grca/learn/news/2011-05-25_ship-seal.htm

An image forming apparatus is connected to a host device including first and second power domains which are separately supplied with power and includes first and second memories to be disposed in the second power domain, a main controller disposed in the first power domain and to perform a control operation using the first memory in a normal mode, and a sub-controller disposed in the second power domain and perform a control operation using the second memory in a power-saving mode, where when the normal mode is changed to the power-saving mode a power supply to the first power domain is shut off, the first memory operates in a self-refresh mode, and the main controller copies central processing unit (CPU) context information into a context storage unit, and when the power-saving mode is changed to the normal mode, the main controller is booted using the CPU context information stored in the context storage unit.

A method for producing a resin molding die (13) for molding a first substrate (2) having a flow path (2b) and a through-hole (2a), wherein a base die (10) having a concave part (10b) corresponding to the flow path (2b) and a through-hole (10a) corresponding to through-hole (2a) and deeper than the concave part (10b) is prepared, the base die (10) is subjected to electroforming with a first material and is then subjected to electroforming with a second material which is different from the first material, and a protruding part for forming through-hole (10a) by removing the first material that was electrodeposited on through-hole (10a) is formed. The first material has a smaller electroforming stress than the second material, the first material exerts a higher adhesiveness with regard to the base die than the second material, and the second material is harder than the first material.

The invention provides optical interconnects of data-processing cores of multicore chips by means of digital planar holographic microchips. The method comprises delivering “N” laser lights to “N” data-processing cores on the host chip, coding the obtained optical signals by modulating them with the core-generated data, and then delivering the modulated and coded optical signals to a holographic microchip formed on the same substrate of the host chip as the data-processing cores, splitting the modulated and coded optical signals into (N−1)N modulated optical copy signals, delivering the copy signals to all data-processing cores except the one that generates the copy signals, and decoding the data obtained from the output signals delivered to the processing cores by the receivers. The method is efficient in that it allows replacing electrical interconnects between the cores with optical interconnects and can be matched to current semiconductor production technology.

A cutting insert has at least first and second side surfaces, with a chip-control arrangement. The chip-control arrangement includes at least one projection disposed at an intersection of a corner of the cutting insert. When the chip-control arrangement includes two projections they can be disposed symmetrically on both sides of the intersection. Each of the at least one projections is elongated and extends longitudinally along an associated side surface.

In a cutting tool for chip removing machining a holder for a cutter has a body received therein and movable with surfaces to bear against the cutter for defining the position of the cutter in the direction of an intended axis of rotation of the holder as well as a screw which may be screwed in a threaded bore in the holder. Spring members are arranged to act between the holder and the body for biasing the body against said screw portions.

A rotary cutting tool, such as a milling cutter (10) includes a central hub (12), a cutting rim (14) and a plurality of spokes (22) connecting the central hub (12) to the cutting rim (14). Each spoke (22) is separated by an opening (32) and polygonal in cross-sectional shape formed by two side walls (22a, 22b), two front walls (22c, 22d) and a rear wall (22e). One of the side walls (22a) of each spoke (22) is formed at a pitch angle (42) with respect to a central axis (11) of the cutting tool (10) that is sufficient to cause lift of chips through the opening (32), thereby providing effective chip evacuation during a material removal operation.

A cutting insert (14) is formed with an insert aperture (32) opening out to insert top and bottom surfaces (14A, 14B) of the cutting insert (14). In a plan view of the insert top surface (14A), the cutting insert (14) and the insert aperture (32) both have oblong shapes which are elongated along a common insert longitudinal axis (AIL). The aperture (32) includes first and second side surfaces (32A1, 32A2) which each extend along the insert longitudinal axis (AIL), and aperture first and second end surfaces (32B1, 32B2) which each extend transverse relative to the insert longitudinal axis (AIL). At least one of the aperture first and second end surfaces (32B1, 32B2) is formed with a clamping lip (32C1, 32C2).

A biochip for the integration of all steps in a complex process from the insertion of a sample to the generation of a result, performed without operator intervention includes microfluidic and macrofluidic features that are acted on by instrument subsystems in a series of scripted processing steps. Methods for fabricating these complex biochips of high feature density by injection molding are also provided.

A cutting tap includes a body having an axial forward end and an axial rearward end. The body has a threaded body portion with spiral flutes adjacent the axial forward end, a cylindrical shank portion adjacent the axial rearward end. The threaded body portion includes a chamfered fluted section and a constant diameter section. The threads have a chamfer relief extending radially inward from the cutting edge to a heel of a land. The amount of chamfer relief reaches a maximum value at a point between the cutting edge and the heel, and then becomes smaller between the point of maximum relief and the heel of the land to provide a clearance that reduces the propensity of the tap to chip.

A chip thermistor has a thermistor portion including a ceramic material containing respective metal oxides of Mn, Ni, and Co as major ingredients; a pair of composite portions including a composite material of Ag—Pd, and respective metal oxides of Mn, Ni, and Co and arranged on both sides of the thermistor portion so as to sandwich in the thermistor portion between the composite portions; and external electrodes connected to the pair of composite portions, respectively. In this manner, the pair of composite portions are used as bulk electrodes and, for this reason, the resistance of the chip thermistor can be adjusted mainly with consideration to the resistance in the thermistor portion without need for much consideration to the distance between the external electrodes and other factors.

A chip resistor includes an insulating substrate, top terminal electrodes formed on top surface of the substrate using silver-based cermet, bottom electrodes, resistive element that is situated between the top terminal electrodes and overlaps them partially, an optional internal protective coating that covers resistive element completely or partially, an external protective coating that covers completely the internal protection coating and partially covers top terminal electrodes, a plated layer of nickel that covers face sides of the substrate, top and bottom electrodes, and overlaps partially external protective coating, finishing plated layer that covers nickel layer. The overlap of nickel layer and external protective layer possesses a sealing property because of metallization of the edges of external protective layer prior to the nickel plating process.

A method of manufacturing a chip resistor includes forming a resistor assembly in which a conductive member including portions separated from each other in a first direction is provided in a resistance body member; and dividing the resistor assembly into chip resistors, each including a chip-shaped resistance body formed by a part of the resistance body member, a pair of main electrodes formed by a part of the conductive member and separated from each other in the first direction, and a pair of sub-electrodes formed by a part of the conductive member, separated from each other in the first direction, and adjacent to the main electrodes in a second direction perpendicular to the first direction with concave portions recessed in the first direction interposed therebetween, by punching.

The object of the invention is to provide a method and an apparatus that allow production of metal plate chip resistors having a relatively low resistance with high accuracy and yield through simple process. The object is achieved by apparatus for manufacturing metal plate chip resistors including cutting mold for cutting intermediate product strip transversely to obtain worked product chip, ohm meter for measuring the resistance of the worked product chip, control device having a calculating part for performing a calculation using the resistance measured by the ohm meter to work out a width in which the strip is to be cut transversely so as to obtain a worked product chip of a desired resistance, and cutting width adjustor for making an adjustment so that the strip is to be cut transversely in the width obtained from the calculating part.

There is provided an array type chip resistor including: a chip body, four pairs of lower electrodes disposed on both sides of a lower surface of the chip body and formed so as to be extended to edges of the chip body, side electrodes formed so that the lower electrodes are extended to sides of the chip body, and a resistor interposed between the lower electrodes on the lower surface of the chip body and electrically connected to the lower electrode through a contact portion, wherein when a width of the side electrode is defined as d1, a distance between adjacent side electrodes is defined as d2, and a height of the side electrode is defined as h, in the case in which d1/d2 is 0.5 to 1.5, a value of h is 4,300/d1 μm or above and is 0.24d2+87.26 μm or less.

A surface mount chip resistor for increasing power handling capabilities of radio frequency (RF) circuits and for minimizing parasitic capacitance and inductance effects, the chip resistor includes a ceramic substrate having a main portion and an outrigger. A resistor element is between an input contact and an output contact on a top surface of the main portion. A ground plane attachment area is on a top surface of the outrigger. The ground plane attachment area is mounted to a ground plane of a circuit board to provide a heat pathway for dissipating heat generated by the resistor element.

There are provided a chip resistor and a method of manufacturing the same. The chip resistor includes a ceramic substrate; an adhesion portion formed on a surface of the ceramic substrate; and a resistor formed on the adhesion portion, wherein the adhesion portion includes at least one of copper (Cu), nickel (Ni), and copper-nickel (Cu—Ni).

Disclosed herein is a thin film type chip device, including: a plurality of unit circuit structures laminated on a substrate; and an adhesive layer adhering the unit circuit structures to each other.

The electronic component has a resin electrode which constitutes an external electrode on a face of a ceramic base body. At least a tip portion of a resin electrode region extended around another face of the body is bonded to the ceramic base body, and further a relationship between Rz1 and Rz2 satisfies the following requirement: Rz1>Rz2, Rz1>3.3 μm, and Rz2

A wireless media player and a related system and methodology are disclosed. One aspect of the wireless media player system pertains to a virtual connector system, apparatus, and method for the automatic establishment of wireless connectivity with other electronic devices. In one embodiment, the media player device employs the use of integrated Radio Frequency Identification (RFID) technology to exchange communication settings, media capability, and other parameters with an external device that also has integrated RFID technology. The automatic exchange of settings and other information via a proximity-based RFID data exchange allows a media player to quickly establish a secure communication link with another device via a commonly supported wireless protocol such as Ultra Wideband (UWB) or Bluetooth. Another aspect of the media player system pertains to a method of using the captured media capability of the connecting device to customize certain menu options and software parameters in the media player.

Network on Chips (NoC)s with a bufferless and nonblocking architecture are described. Core processors are communicatively coupled together on a substrate with a set of routing nodes based on nonblocking process. A network component routes data packets through the routing nodes and the core processors via communication links. A bufferless cross bar switch facilitates the communication of the data packets and/or path setup packets through the communication links among source processors and destination processors. The communication links include one or more channels, in which a channel comprises a data sub-channel, an acknowledgement sub-channel and a release sub-channel.

A multi-chip package may include first and second integrated circuit dies that are each partitioned into multiple logic regions. The logic regions of the first and second dies may be coupled via interconnects. Each integrated circuit die may include at least one spare logic region. Multiple logic groups may be formed with each logic group including logic regions from the first and second integrated circuit dies and the interconnects that couple those logic regions. The logic groups may be evaluated to identify defective logic groups. In response to identifying a defective logic group, the defective logic group may be repaired by configuring the first and second integrated circuit dies to stop using the defective logic group and to use a spare logic group. The spare logic group may include spare logic regions of the first and second dies that are coupled by spare logic region interconnects.

A multi-chip package is provided. The multi-chip package includes a plurality of chips including at least one bad chip and at least one good chip that are stacked and a plurality of through electrodes each penetrating the chips. A logic circuit included in the at least one bad chip is isolated from each of the plurality of through electrodes.

In various embodiments, a chip arrangement is provided. The chip arrangement may include a chip carrier and a chip mounted on the chip carrier. The chip may include at least two chip contacts and an insulating adhesive between the chip and the chip carrier to adhere the chip to the chip carrier. The at least two chip contacts may be electrically coupled to the chip carrier.

Systems, manufactures, methods and/or techniques for a merged fiducial for chip packages are described. According to some embodiments, an integrated circuit package may include a package substrate having a first side and a second side, a plurality of conductive traces coupled to the first side and a plurality of balls disposed on the second side. The balls may be adapted to electrically connect the laminate package to a circuit board. The integrated circuit package may include a plurality of ball pads disposed on the second side, the ball pads being adapted to electrically connect the plurality of balls to the plurality of conductive traces. One or more of the ball pads may be uniquely shaped when compared to the rest of the plurality of ball pads, optionally, to serve as a fiducial to designate an A1 pin or ball of the laminate package.

The present invention discloses a tape substrate for chip on film structure of a liquid crystal panel. The tape substrate is provided with plural package units of chip on film structures arranged along its longitudinal direction, and the package unit has a driver chip, input leads and output leads. The longitudinal direction of the driver chip is parallel to the longitudinal direction of the tape substrate, and the input leads and the output leads are located at the two opposite sides of the driver chip. Each package unit is set up with a short side and a long side, and the input leads are formed at the short side, while the output leads are formed at the long side. In the package units adjacent to each other, the short side of one package unit joins the long side of a next package unit. This invention further discloses a liquid crystal panel having the tape substrate.

A method of controlling an integrated circuit chip including first and second clock sources, the first clock source being more thermally stable and having a higher power consumption, the integrated circuit chip being operable in a first mode in which the first clock source is inactive and the second clock source active and in a second mode in which the first and second clock sources are active, the method including operating the integrated circuit chip in the first mode; taking a measurement indicative of temperature; if the measurement indicates that the temperature is outside of a temperature band: activating the first clock source so as to operate the integrated circuit chip in the second mode; recalibrating the second clock source against the first clock source; and following the recalibration, deactivating the first clock source so as to return the integrated circuit chip to the first mode.

A chip and shaving collection system for a key cutting machine has a trough with a linear first trough drawer rail located on a trough first side and a linear second trough drawer rail located on a trough second side. The trough further has a linear first trough support rail having a general shape of a triangular prism located on a trough first side and a linear second trough support rail having a general shape of a triangular prism located on a trough second side. The system has a plurality of linear support beams located on the support rails. The system has a rigid planar grid member spanning the trough top located on the linear support beams. The system has a drawer that is fluidly sealed located in the trough. The system has a key cutting machine located on the grid member.

A de-noise circuit and a de-noise method for differential signals and a chip for receiving differential signals are provided. The de-noise circuit includes a filter and a register. Both the filter and the register are disposed in the chip. The chip receives a differential signal through a first input terminal and a second input terminal. The filter is coupled between the first input terminal and the second input terminal of the chip. The filter filters out noises in the differential signal. The filter includes at least one filter unit. Each filter unit has at least one resistance value or at least one capacitance value. The register is coupled to the filter. The register receives and stores a control value. The register controls the resistance value or the capacitance value of at least one of the filter units based on the control value.

A coupling structure for a multi-layered chip filter includes a resonator layer including a resonator pattern with spaced areas and a coupling layer including at least two separated overlap portion patterns overlapped with the spaced areas of the resonator pattern respectively and a connecting portion pattern having multiple linear portions connecting the separated overlap portion patterns in an area not-overlapped with the resonator pattern.

This technology is a method and apparatus for the semi-continuous measurement of the concentration of constituents of airborne particles which couples a laminar flow, water condensation particle collector to a microfluidic device for assay of particle chemical composition by electrophoresis. The technology has been used for the assay of sulfates, nitrates, chlorides, and organic acids contained in fine and submicrometer atmospheric particles. For these compounds the apparatus and method described is capable of one-minute time resolution at concentrations at the level of micrograms of analyte species per cubic meter of air. Extension to other analytes is possible.

The present invention relates to a film for flip chip type semiconductor back surface to be formed on a back surface of a semiconductor element flip chip-connected to an adherend, the film for flip chip type semiconductor back surface containing an inorganic filler in an amount within a range of 70% by weight to 95% by weight based on the whole of the film for flip chip type semiconductor back surface.

The present disclosure relates to a material reducing machine convertible between a grinding configuration and a chipping configuration. The material reducing machine includes a rotary component that is rotatable about an axis of rotation, the rotary component defining a grinding configuration boundary that extends at least partially around the axis of rotation. The material reducing machine also includes a plurality of hammers secured to the rotary component, the hammers including end portions that project outwardly beyond the grinding configuration boundary of the rotary component. Furthermore, the material reducing machine includes a boundary enlarging structure that mounts over the rotary component, the boundary enlarging structure defining a chipping configuration boundary that extends at least partially around the axis of rotation when the boundary enlarging structure is mounted over the rotary component, the chipping configuration boundary being positioned outside the grinding configuration boundary. The boundary enlarging structure is not mounted over the rotary component when the material reducing machine is in the grinding configuration and the boundary enlarging structure is mounted over the rotary component when the material reducing machine is in the chipping configuration.

A substrate of a lab-on-a-chip system has two adjacent recesses, one serving as a flow channel and the other one being filled with an elastomer compound. In a first state, the elastomer compound and the substrate delimit the flow channel in a section. In a second state, the elastomer compound takes up the space in the recess in the substrate along a cross-section of the flow channel, thereby completely closing the flow channel. The substrate and the elastomer compound may be produced by injection molding techniques.

A lathe cutter and chip fan is described in which an annular frame includes a rotary portion that is driven to rotate about an axis. The rotary portion is annular, forming a workpiece receiving opening. A cutter is mounted on the rotary portion and projects into the workpiece receiving opening. The cutter rotates with the rotary portion to cut material from a workpiece positioned within the workpiece opening. A housing forms a compartment about the rotary portion and cutter, with a central housing opening substantially aligned with the workpiece receiving opening. A chip discharge openly communicates with the compartment and is situated substantially tangentially with respect to a rotational path of the cutter. A plurality of impellers are mounted to the rotary portion for rotation therewith. The impellers are configured to produce an airflow through the housing with intake air entering through the central housing opening and discharging through the chip discharge, whereby chips of workpiece material removed from the workpiece by the cutter may be discharged in the airflow through the chip discharge.

A cutting tool for cutting a work piece and catching debris during turning operations is described herein. The cutting tool comprises a tubular cutting member having first and second ends, the first end having a sharpened edge, and a debris receiving means connected to the second end. The tubular cutting member may have a number of different cross-sections providing a number of different cutting tool configurations for use in turning operations. The debris receiving means may further include a flexible hose having a first hose end and a second hose end, wherein the first hose end is connected to the second end of said tubular cutting member. The hose may be connected to a vacuum source to more effectively collect debris generated during turning operations. The tubular cutting member could be made in a range of sizes from one quarter inch to two inches in diameter, with a nominal tube length of from three inches to twenty inches, or even larger where needed. Both ends of the tubular cutting member could be sharpened, and reversed in the holder when one end is dull.

An apparatus includes a substrate, a classical computing processor formed on the substrate, a quantum computing processor formed on the substrate, and one or more coupling components between the classical computing processor and the quantum computing processor, the one or more coupling components being formed on the substrate and being configured to allow data exchange between the classical computing processor and the quantum computing processor.

Embodiments of the present invention are directed to a microcontroller device having a microprocessor, programmable memory components, and programmable analog and digital blocks. The programmable analog and digital blocks are configurable based on programming information stored in the memory components. Programmable interconnect logic, also programmable from the memory components, is used to couple the programmable analog and digital blocks as needed. The advanced microcontroller design also includes programmable input/output blocks for coupling selected signals to external pins. The memory components also include user programs that the embedded microprocessor executes. These programs may include instructions for programming the digital and analog blocks “on-the-fly,” e.g., dynamically. In one implementation, there are a plurality of programmable digital blocks and a plurality of programmable analog blocks.

A device and method for communicating, via a memory-mapped communication path, between a host processor and a cellular-communication modem are disclosed. The method includes providing logical channels over the memory-mapped communication path and transporting data organized according to one or more cellular communication protocols over at least one of the logical channels. In addition, the method includes acknowledging when data transfer occurs between the host processor and the cellular-communication modem, issuing commands between the host processor and the cellular-communication modem, and communicating and managing a power state via one or more of the logical channels.