The present invention relates to epoxy group-terminated polymers of the formula (I). Said epoxy group-terminated polymers are suited extremely well as impact resistance modifiers, particularly in epoxy resin compositions. They are particularly suited for use in heat-curing epoxy resin adhesives. It has been found that such epoxy resin compositions not only have excellent mechanical properties and high glass transition temperatures, but also above all improved impact resistance properties, both at room temperature and at low temperatures.

Bis-Phenol A (BPA) can now be replaced in industrial processes by BPA substitutes. The BPA substitutes can have structures that are derivatives of BPA. The BPA substitutes can be used in preparing epoxy composition, polycarbonate compositions, and polysulfonate compositions or for other uses in place of BPA.

Aqueous copolymer dispersions for a variety of uses, including coating compositions or binders for plasters and paints, are disclosed. The aqueous copolymer dispersions may comprise one or more silicon containing compounds, in particular hydrolyzable silane compounds without any additional reactive group.

A facile synthesis of amphiphilic hyperbranched polymers consisting of poly(amic acid) and polyimide was developed via “A2+B3” approach from difunctional anhydride and trifunctional hydrophilic poly(oxyalkylene)triamine. Various amphiphilic hyperbranched poly(amic acid)s (HBPAAs) with terminal amine functionalities and amic acid structures were prepared through ring-opening polyaddition at room temperature, followed by thermal imidization process for the formation of hyperbranched polyimides (HBPIs), accordingly. The resulting HBPIs were analyzed by GPC, indicating the molecule weights of 5000˜7000 g/mol with a distribution of polydispersity between 2.0 and 3.8. The amine titration for HBPIs indicated the peripheral total-amine contents to be 8.32˜18.32 mequiv/g dependent on compositions.

Disclosed is an epoxy resin composition used for encapsulation of a semiconductor containing an epoxy resin (A), a curing agent (B), an inorganic filler (C) and a mold releasing agent, in which the mold releasing agent contains a compound (D) having a copolymer of an α-olefin having 28 to 60 carbon atoms and a maleic anhydride esterified with a long chain aliphatic alcohol having 10 to 25 carbon atoms.

Stone is formed from 5 to 60% by weight of polymerised, low-viscosity, transparent or low-colour-resin, 20 to 90% by weight of spherical alumina trihidrate Al2O3.3H2O containing less regular particles containing, advantageously 0 to 100% by weight of a transparent or translucent substitute of alumina trihydrate, and/or with 0 to 20% or pre-prepared particulate, filled resin of a chosen colour, and/or mineral particles and less than 2% by weight of luminophor. These individual components are mixed intensely whilst extracting included gaseous parts. Extraction is carried out whilst mixing, and/or after mixing, and/or before mixing. The mixture is initiated by introducing a starter and intensely mixing it into the mixture. The mixture is poured into a mould or onto a moving endless belt. The cured synthetic stone is removed from the mould or the hardened composite is taken off the the belt. Synthetic stone can be used in products as a light carrier.

A method, system and computer program product for intelligently responding to hardware failures so as to optimize system performance. An administrative server monitors the utilization of the hardware as well as the software components running on the hardware to assess a context of the software components running on the hardware. Upon detecting a hardware failure, the administrative server analyzes the hardware failure to determine the type of hardware failure and analyzes the properties of the workload running on the failed hardware. The administrative server then responds to the detected hardware failure based on various factors, including the type of the hardware failure, the properties of the workload running on the failed hardware and the context of the software running on the failed hardware. In this manner, by taking into consideration such factors in responding to the detected hardware failure, a more intelligent response is provided that optimizes system performance.

The invention in particular has as an object detecting incompatibility between equipment items of a on-board system. A logic interface associated with one equipment item comprises at least one input while a logic interface associated with another equipment item comprises at least one output. The input and the output are connected. After a minimal data definition level associated with the input and a data definition level associated with the output have been obtained (505), the said minimal data definition level associated with the input is compared (515) with the said data definition level associated with the output. Following this comparison, if the said minimal data definition level associated with the input is lower than the said data definition level associated with the output, an alarm indicating an incompatibility of these two equipment items is generated (545).

A system, method and computer program product for avoiding a processing flaw in a computer processor triggered by a predetermined sequence of hardware events. The system may include a detecting unit and a power-on reset unit. The detecting unit detects that the predetermined sequence of hardware events is going to occur at the computer processor. The power-on reset unit initializes the computer processor to a state stored in computer memory in response to detecting the sequence of hardware events.

A method to prevent failure on a server computer due to internally and/or externally induced shock and/or vibration. The method includes acquiring, by at least one sensor, analog acceleration data of components in a server computer. The data is then converted to digital format and stored within a motor drive assembly processor memory unit. The processor analyzes the stored data for existence of machine degradation. In response to detecting the existence of machine degradation, the motor drive assembly processor initiates remediation procedures. The remediation procedures include controlling rotating speed of moving devices or performing a complete system shut down.

A Test Wrapper and associated Test Access Mechanism (TAM) architecture for facilitating testing of IP blocks integrated on a System on a Chip (SoC). The TAM architecture includes a Test Controller and one or more Test Wrappers that are integrated on the SoC proximate to IP blocks. Test data and commands corresponding to input from an external tester are packaged by the Test Controller and sent to one or more Test Wrappers via an interconnect fabric. The Test Wrappers interface with one or more IP test ports to provide test data, control, and/or stimulus signals to the IP blocks to facilitate circuit-level testing of the IP blocks. Test results for the circuit-level tests are returned to the Test Controller via the fabric. Test Wrappers may be configured to pass through interconnect signals, enabling functional testing of IP blocks to be facilitated via test packages and test results transmitted between the Test Controller and the IP blocks via the fabric. Test wrappers may also be configured to test multiple IP blocks comprising a test partition.

A logical operations functional block for an execution unit of a processor includes a first input data link for a first operand and a second input data link for a second operand. The execution unit includes a register connected to an error correction code detection unit. The logical operations functional block includes a look-up table configured to receive an error correction code syndrome from the error correction code detection unit. The logical operations functional block also includes a multiplexer configured to receive an output signal from the look-up table at a first input and the first operand at a second input, wherein an output of the multiplexer is coupled to the first input data link of a logical functional unit.

The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for variable rate coding in a data processing system.

The present disclosure relates to a method for detecting a parity error in a sequence of DQPSK symbols of a digital transmission system, comprising determining a first demodulated symbol r1; determining a second demodulated symbol r2; determining a first parity symbol p1; determining a second parity symbol p2; determining a super-parity symbol q1; and detecting a parity error in the sequence of DQPSK symbols by comparing a combination of the first parity symbol p1 and the second parity symbol p2 against the super-parity symbol q1, wherein a parity between two DQPSK symbols describes a phase difference between the two DQPSK symbols.

A two step process for the destruction of a precursor material using a steam plasma in a three zone reactor wherein the precursor material is hydrolyzed as a first step in the high temperature zone of the reactor, followed by a second step of medium temperature oxidation of the reactant stream in the combustion zone of the reactor where combustion oxygen or air is injected and immediate quenching of the resulting gas stream to avoid the formation of unwanted by-products. A related apparatus includes a non transferred direct current steam plasma torch, an externally cooled three zone steam plasma reactor means for introducing the precursor material into the plasma plume of the plasma torch, means for introducing the combustion air or oxygen into the combustion zone, means for exiting the reactant mixture from the reactor and means for quenching the reactant mixture located at the exit end of the reactor.

Method of stabilizing radium present in radium-containing effluent, in which the effluent and a metal chloride are mixed, then the previously obtained mixture is reacted with a sulfate ion to obtain effluent containing stabilized radium. The chloride can be a barium, strontium or lead chloride. The sulfate ion can be supplied by the addition of sulfuric acid, sulfuric anhydride, soluable sulfate or soluble sulfate salt. The method applies in particular to the treatment of solid radium-containing effluents or effluents containing substances in suspension coming from chemistry or metallurgy of zirconium or treatment of uranium-containing minerals.

An independently functioning or centrally controlled wall light switch is configured to operate in normal mode and a Jewish holiday mode wherein the state of the light is fixed, regardless of the user's physical manipulation of the light switch. The control system automatically activates holiday mode by combining a geographically determined Jewish religious clock executed by software and hardware that utilizes the current time, date and geographical location of the apparatus in accordance with the Jewish definition of time and laws for calculating numerous religiously significant shifting daily points in time. The control system further incorporates several energy saving and preference modes by utilizing a particular day's calculated religious points in time in conjunction with holiday behavior patterns common to most Jewish families to provide the user with a greatly simplified means of programming an automatically adjusting on/off light timer and dimming overlay functionality during holiday mode.

In this application, a set of orthogonal functions is introduced whose power spectral densities are all rectangular shape. To find the orthogonal function set, it was considered that their spectrums (Fourier transforms of the functions) are either real-valued or imaginary-valued, which are corresponding to even and odd real-valued time domain signals, respectively. The time domain functions are all considered real-valued because they are actually physical signals. The shape of the power spectral densities of the signals are rectangular thus, the Haar orthogonal function set can be employed in the frequency domain to decompose them to several orthogonal functions. Based on the inverse Fourier transform of the Haar orthogonal functions, the time domain functions with rectangular power spectral densities can be determined. This is equivalent to finding the time-domain functions by taking the inverse Fourier transform of the frequency domain Walsh functions. The obtained functions are sampled and truncated to generate finite-length discrete signals. Truncation destroys the orthogonality of the signals. The Singular Value Decomposition method is used to restore the orthogonality of the truncated discrete signals.

Systems, devices, processors, and methods are described which may be used for the reception of a wireless broadband signal at a user terminal from a gateway via a satellite. A wireless signal may include a series of physical layer frames, each frame including a physical layer header and payload. The received signal is digitized and processed using various novel physical layer headers and related techniques to synchronize the physical layer frames and recover data from physical layer headers for purposes of demodulation and decoding.

A system (200) and a method (100) of operating a computing device to perform memoization are disclosed. The method includes determining whether a result of a function is stored in a cache and, if so, retrieving the result from the cache and, if not, calculating the result and storing it in the cache. The method (100) includes transforming (104) by the computing device at least one selected from the input parameters and the output parameters of the function, the transforming being based on an analysis of the function and its input arguments to establish whether or not there is a possible relationship reflecting redundancy among the input parameters and output parameters of the function. The transforming may include at least one of: use of symmetry, scaling, linear shift, interchanging of variables, inversion, polynomial and/or trigonometric transformations, spectral or logical transformations, fuzzy transformations, and systematic arrangement of parameters.

A method of generating a code sequence in a wireless communication system is disclosed. More specifically, the method includes recognizing a desired length of the code sequence, generating a code sequence having a length different from the desired length, and modifying the length of the generated code sequence to equal the desired length. Here, the step of modifying includes discarding at least one element of the generated code sequence or inserting at least one null element to the generated code sequence.

A method for generating multi-level (or multi-bit) pseudo-random sequences is disclosed. This embodiment relates to communication systems, and more particularly to generating multi-level pseudo random symbol sequence. Present day systems do not employ effective mechanisms for generation of multi level PRBS in order to increase the data communication rates. Further, these systems do not cover all the possible transitions for the outputs of the system. The proposed system employs mechanisms in order to generate PRBS signals for producing multi levels signals to the electronic components. The mechanism employs alternate bit tapping techniques. In the alternate bit tapping technique, bits are tapped alternatively to determine the current state and the next state of the system. In addition, the mechanism also covers all the possible states of the output vector with transitions between the output states. This ensures that high data rates are obtained for a given bandwidth of operation.

Examples disclose a computing system comprising a computing device with a display surface to detect a selection of functionality from a list of functionalities to be disabled on a calculator. Further, the computing device creates a custom configuration based on the selected functionality. Additionally, the examples also disclose a calculator with a processor to integrate the custom configuration, the custom configuration restricts the selected functionality on the calculator.

A crosslinkable curing super-branched polyester and the cured product and the preparation method thereof are disclosed. The super-branched polyester has high refractive index and comprises a compound represented by the following structural formula (I). In the formula (I), HBP is the backbone of the super-branched polyester; both a and b are positive integers; the sum of a and b is less than or equal to n; n is more than or equal to 10 and less than 80. In the super-branched polyester, A is represented by formula (II) and N is represented by formula (III), wherein R is methyl or hydrogen atom; the mole ratio of N relative to the total mole of A and N is more than 30 mol %, and the ratio of the total mole of A and N relative to the product of the total mole of HBP backbone and n is more than 0.5 and less than or equal to 1.

In embodiments of driver interface functions to interface client function drivers, a set of serial communication protocol driver interfaces are exposed by a core driver stack, and the serial communication protocol driver interfaces include driver interface functions to interface with client function drivers that correspond to client devices configured for data communication in accordance with the serial communication protocol. A client function driver can check for the availability of a driver interface function before interfacing with the core driver stack via the serial communication protocol driver interfaces. A contract version identifier can also be received from the client function driver via an extension of the driver interface functions, where the contract version identifier indicates a set of operation rules by which the client function driver interfaces with the core driver stack.

Systems, mediums, and methods are provided for scheduling input/output requests to a storage system. The input output requests may be received, categorized based on their priority, and scheduled for retrieval from the storage system. Lower priority requests may be divided into smaller sub-requests, and the sub-requests may be scheduled for retrieval only when there are no pending higher priority requests, and/or when higher priority requests are not predicted to arrive for a certain period of time. By servicing the small sub-requests rather than the entire lower priority request, the retrieval of the lower priority request may be paused in the event that a high priority request arrives while the lower priority request is being serviced.

A memory system includes a CPU that communicates commands and addresses to a main-memory module. The module includes a buffer circuit that relays commands and data between the CPU and the main memory. The memory module additionally includes an embedded processor that shares access to main memory in support of peripheral functionality, such as graphics processing, for improved overall system performance. The buffer circuit facilitates the communication of instructions and data between CPU and the peripheral processor in a manner that minimizes or eliminates the need to modify CPU, and consequently reduces practical barriers to the adoption of main-memory modules with integrated processing power.

A universal serial bus (USB) dongle device includes a USB interface that receives selection data from a host device that indicates a selection of a first video format from a plurality of available formats. The USB interface also receives an input video signal from the host device in the first video format and a power signal from the host device. An encoding module generates a processed video signal in a second video format based on the input video signal, wherein the first video format differs from the second video format. The USB interface transfers the processed video signal to the host device.

The description generally relates to a system designed to synchronize the rendering of a media file between a master device and a sister device. The system is designed so that a media file is simultaneously rendered on a master device and a sister device beginning from identical temporal starting points.

Various embodiments include apparatuses, stacked devices and methods of forming dice stacks on an interface die. In one such apparatus, a dice stack includes at least a first die and a second die, and conductive paths coupling the first die and the second die to the common control die. In some embodiments, the conductive paths may be arranged to connect with circuitry on alternating dice of the stack. In other embodiments, a plurality of dice stacks may be arranged on a single interface die, and some or all of the dice may have interleaving conductive paths.

A method for efficient dispatch/completion of a work element within a multi-node data processing system. The method comprises: selecting specific processing units from among the processing nodes to complete execution of a work element that has multiple individual work items that may be independently executed by different ones of the processing units; generating an allocated processor unit (APU) bit mask that identifies at least one of the processing units that has been selected; placing the work element in a first entry of a global command queue (GCQ); associating the APU mask with the work element in the GCQ; and responsive to receipt at the GCQ of work requests from each of the multiple processing nodes or the processing units, enabling only the selected specific ones of the processing nodes or the processing units to be able to retrieve work from the work element in the GCQ.

Methods and systems for statistically eliding fences in a work stealing algorithm are disclosed. A data structure comprising a head pointer, tail pointer, barrier pointer and an advertising flag allows for dynamic load-balancing across processing resources in computer applications.

A video player instance may be prioritized and decoding and rendering resources may be assigned to the video player instance accordingly. A video player instance may request use of a resource combination. Based on a determined priority a resource combination may be assigned to the video player instance. A resource combination may be reassigned to another video player instance upon detection that the previously assigned resource combination is no longer actively in use.

By employing a two-tier load balancing scheme, embodiments of the present invention may reduce the overhead of shared resource management, while increasing the potential aggregate throughput of a thread pool. As a result, the techniques presented herein may lead to increased performance in many computing environments, such as graphics intensive gaming.

According to an embodiment, based on task border information, and first-type dependency relationship information containing N number of nodes corresponding to data accesses to one set of data, containing edges representing dependency relationship between the nodes, and having at least one node with an access reliability flag indicating reliability/unreliability of corresponding data access; task border edges, of edges extending over task borders, are identified that have an unreliable access node linked to at least one end, and presentation information containing unreliable access nodes is generated. According to dependency existence information input corresponding to the set of data, conversion information indicating absence of data access to the unreliable access nodes is output. According to the conversion information, the first-type dependency relationship information is converted into second-type dependency relationship information containing M number of nodes (0≦M≦N) corresponding to data accesses to the set of data and containing edges representing inter-node dependency relationship.

The present invention relates to 1,4-diethynylbenzene derivatives having substituents in the 2,3-position (cf. formula I, Claims), to the use thereof for high-frequency components, to liquid-crystalline media comprising the compounds, and to high-frequency components, in particular antennae, especially for the gigahertz range, comprising these media. The liquid-crystalline media serve, for example, for the phase shifting of microwaves for tuneable ‘phased-array’ antennae.

A method for preparing 13C labeled iodotridecane represented by Formula A: The method comprises the conversion of 13C labeled propargyl alcohol to 13C labeled iodotridecane via alkylation of propargyl alcohol with iododecane.

The invention is drawn to fluid concentrate formulations of fatty acid monoethanolamides comprising (a) about 71-76% by weight of one or more C8-C22 fatty acid monoethanolamides, (b) about 15-17% by weight of water, and (c) about 10-12% by weight of one or more hydrotropes, based on the fluid formulation, wherein the fluid formulation is homogeneous, pumpable and color stable at a temperature of less than 55° C. A preferred embodiment is drawn to fluid concentrate formulations of cocamide monoethanolamide (CMEA) consisting of (a) about 71-76% by weight of CMEA, (b) about 15-17% by weight of water, and (c) about 10-12% by weight of glycerol, based on the fluid formulation. Methods of preparing the fluid concentrate formulations mulations are also disclosed. The fluid concentrate formulations of fatty acid monoethanolamides are useful in the preparation of cosmetic and pharmaceutical compositions.

A heat transfer fluid emulsion includes a heat transfer fluid, and liquid droplets dispersed within the heat transfer fluid, where the liquid droplets are substantially immiscible with respect to the heat transfer fluid and have dimensions that are no greater than about 100 nanometers. In addition, the thermal conductivity of the heat transfer fluid emulsion is greater than the thermal conductivity of the heat transfer fluid.

This invention provides a method related to the preparation of derivatives of poly(ethylene glycol), wherein the method comprises increasing the pH of an aqueous composition comprising a poly(ethylene glycol) bearing a —O—(CH2)n—CO2R3 functional group to result in an aqueous composition comprising a poly(ethylene glycol) bearing a —O—(CH2)n—CO2H functional group, wherein R3 is alkyl and (n) in each instance is 1-6.

Aqueous emulsions of epoxy- and organo-substituted, branched organopolysiloxanes are prepared by emulsifying the latter in water with the aid of a dispersing agent. The emulsions are storage stable and are useful in multi-component coating, adhesive, and binder systems.

A method and circuit arrangement utilize a low latency variable transfer network between the register files of multiple processing cores in a multi-core processor chip to support fine grained parallelism of virtual threads across multiple hardware threads. The communication of a variable over the variable transfer network may be initiated by a move from a local register in a register file of a source processing core to a variable register that is allocated to a destination hardware thread in a destination processing core, so that the destination hardware thread can then move the variable from the variable register to a local register in the destination processing core.

Embodiments provide methods, apparatus, systems, and computer readable media associated with predicting predicates and branch targets during execution of programs using combined branch target and predicate predictions. The predictions may be made using one or more prediction control flow graphs which represent predicates in instruction blocks and branches between blocks in a program. The prediction control flow graphs may be structured as trees such that each node in the graphs is associated with a predicate instruction, and each leaf associated with a branch target which jumps to another block. During execution of a block, a prediction generator may take a control point history and generate a prediction. Following the path suggested by the prediction through the tree, both predicate values and branch targets may be predicted. Other embodiments may be described and claimed.

A hypervisor and one or more guest operating systems resident in a data processing system and hosted by the hypervisor are configured to selectively enable or disable branch prediction logic through separate hypervisor-mode and guest-mode instructions. By doing so, different branch prediction strategies may be employed for different operating systems and user applications hosted thereby to provide finer grained optimization of the branch prediction logic for different operating scenarios.

A computing method includes accepting a definition of a computing task, which includes multiple Processing Elements (PEs) having execution dependencies. The computing task is compiled for concurrent execution on a multiprocessor device, by arranging the PEs in a series of two or more invocations of the multiprocessor device, including assigning the PEs to the invocations depending on the execution dependencies. The multiprocessor device is invoked to run software code that executes the series of the invocations, so as to produce a result of the computing task.

A High Performance Computing (HPC) node comprises a motherboard, a switch comprising eight or more ports integrated on the motherboard, and at least two processors operable to execute an HPC job, with each processor communicably coupled to the integrated switch and integrated on the motherboard.

An adaptable integrated circuit is disclosed having a plurality of heterogeneous computational elements coupled to an interconnection network. The interconnection network changes interconnections between the plurality of heterogeneous computational elements in response to configuration information. A first group of computational elements is allocated to form a first version of a functional unit to perform a first function by changing interconnections in the interconnection network between the first group of heterogeneous computational elements. A second group of computational elements is allocated to form a second version of a functional unit to perform the first function by changing interconnections in the interconnection network between the second group of heterogeneous computational elements. One or more of the first or second group of heterogeneous computational elements are reallocated to perform a second function by changing the interconnections between the one or more of the first or second group of heterogeneous computational elements.

Mechanisms are provided for offloading a workload from a main thread to an assist thread. The mechanisms receive, in a fetch unit of a processor of the data processing system, a branch-to-assist-thread instruction of a main thread. The branch-to-assist-thread instruction informs hardware of the processor to look for an already spawned idle thread to be used as an assist thread. Hardware implemented pervasive thread control logic determines if one or more already spawned idle threads are available for use as an assist thread. The hardware implemented pervasive thread control logic selects an idle thread from the one or more already spawned idle threads if it is determined that one or more already spawned idle threads are available for use as an assist thread, to thereby provide the assist thread. In addition, the hardware implemented pervasive thread control logic offloads a portion of a workload of the main thread to the assist thread.

In accordance with embodiments, there are provided mechanisms and methods for controlling a process using a process map. These mechanisms and methods for controlling a process using a process map can enable process operations to execute in order without necessarily having knowledge of one another. The ability to provide the process map can avoid a requirement that the operations themselves be programmed to follow a particular sequence, as can further improve the ease by which the sequence of operations may be changed.

A system and method is disclosed for communicating with sensors/loggers in integrated radio frequency identification (RFID) tags. An RFID reader uses a Communicate With Data Logger Command to communicate with a data logger in an RFID tag. The RFID reader performs data access processes using an Index Register and a Data Register of the RFID tag. The RFID reader selects one of (1) Index Read access (2) Index Write access (3) Data Write access (4) Data Read access with parity and (5) Data Read access with cyclic redundancy check (CRC). The RFID tag performs the requested data access and then performs an error detection process.