Verification of a USB4 router design is not just about USB4 but also about the inclusion of the three other major protocols namely, USB3, DisplayPort (DP), and PCI Express (PCIe). These protocols can be simultaneously tunneled through a USB4 router. Put in simple terms, such tunneling involves the conversion of the respective native USB3, DP, or PCIe protocol traffic into the USB4 transport layer packets, which are tunneled through a USB4 fabric, and converted back into the respective original native protocol traffic.

It may sound simple but is perhaps not.

There are several aspects in a router that come into picture to carry out this task of conversion of native protocol traffic, route it to the intended destination, and then convert it back to the original form. Some of those are the USB3, DP and PCIe protocol adapters, transport mechanism using routing, flow control, paths, path set-up and teardown, control and configuration, configuration spaces.

That is not all. There are core USB4 specific logical layer intricacies as well, which carry out the tasks of ensuring that all the USB4 ports and links are working as desired to provide up to 40Gbps speed and that the USB4 traffic flows through out the fabric in the intended way. These bring on the table features like High Speed link, ordered sets, lane initialization, lane adapter state machine, low power, lane bonding, RS-FEC, side band channel, sleep and wake, error checking.

All of these put together give rise to a very large verification space against which a USB4 router design should be verified. If we were to break down this space it can be broadly put in the following major dimensions,

• Protocol Adapter Layer
  • USB3 tunneling
  • DP tunneling
  • PCIe tunneling
• Host Interface Adapter Layer
• Transport Layer
  • Flow control
  • Routing
  • Paths
• Configuration layer and control packet protocol
• Configuration spaces
• Logical Layer

The independent verification of these dimensions is not all that would qualify the design as verified. They have to be verified in various combinations of each other too. Overall, all the parts of a USB4 router system need to be working together coherently.

For example, the following diagram depicts the various layers that a USB4 router may comprise of,

A USB4 router or a domain of routers does not work on its own. There is a Connection Manager per domain, which is a software-based entity managing a domain. A router provides the various capabilities for a Connection Manager to carry out its responsibilities of managing a domain.

It would not be an exaggeration to say that the spectrum of verification of a USB4 router ranges from the very minute details of logical layer to the system-level like multiple dependencies as the whole USB4 system is brought up layer by layer, step-by-step.

Cadence has a mature Verification IP solution that can help in the verification of USB4 designs. Cadence has taken an active part in the working group that defined the USB4 specification and has created a comprehensive Verification IP that is being used by multiple members in the last two years.

If you plan to have a USB4 compatible design, you can reduce the risk of adopting a new technology by using our proven and mature USB4 Verification IP. Please contact your Cadence local account team for more details and to get connected.

Once while eating dinner in Montreal, our friendly, intoxicated waitress plopped herself in my lap and proceeded to tell us about how obsessed she was with the CD that was playing - singing out the lyrics at an ungodly volume and flinging her arms about. Wow, I thought to myself, people who listen to Morcheeba sure seem to have a lot of fun, and promised to check them out.

Several CDs later, they are firmly one of my favorites. And their trip hop meditation, 2003’s Charango remains one of my most played CDs.

Morcheeba (Mor = more, Cheeba = pot) are brothers Ross and Paul Godfrey with singer Skye Edwards (who has since been replaced). Part trance, part ambience, Charango is full of smooth, snogworthy jams. And just as you surrender to its seductive groove, Slick Rick shows up with a rap called “Women Lose Weight”.

Lamenting his wife putting on weight after having kids and stalled by his mistress who wants a clean break before she shacks up with him, he decides the easiest way out of it all is to kill the spouse. Considering different ways to do the deed, he finally rams his car into her Chevy over a long lunch break one fine day. It is an unexpected, stunning, tongue-in-cheek social commentary that makes it a CD you won’t forget easily.

Rave Out © 2007 IndiaUncut.com. All rights reserved.
India Uncut * The IU Blog * Rave Out * Extrowords * Workoutable * Linkastic

I loved Nina Paley’s brilliant animated film Sita Sings the Blues. If you’re reading this, stop right now—and watch the film here.

Paley has set the story of the Ramayana to the 1920s jazz vocals of Annette Hanshaw. The epic tale is interwoven with Paley’s account of her husband’s move to India from where he dumps her by e-mail. The Ramayana is presented with the tagline: “The Greatest Break-Up Story Ever Told.”

All of this should make us curious. But there are other reasons for admiring this film:

The film returns us to the message that is made clear by every village-performance of the Ramlila: the epics are for everyone. Also, there is no authoritative narration of an epic. This film is aided by three shadow puppets who, drawing upon memory and unabashedly incomplete knowledge, boldly go where only pundits and philosophers have gone before. The result is a rendition of the epic that is gloriously a part of the everyday.

This idea is taken even further. Paley says that the work came from a shared culture, and it is to a shared culture that it must return: she has put the film on Creative Commons—viewers are invited to distribute, copy, remix the film.

Of course, such art drives the purists and fundamentalists crazy. On the Channel 13 website, “Durgadevi” and “Shridhar” rant about the evil done to Hinduism. It is as if Paley had lit her tail (tale!) and set our houses on fire!

Rave Out © 2007 IndiaUncut.com. All rights reserved.
India Uncut * The IU Blog * Rave Out * Extrowords * Workoutable * Linkastic

This is the 17th installment of The Rationalist, my column for the Times of India.

One of my favourite English words comes from chess. If it is your turn to move, but any move you make makes your position worse, you are in ‘Zugzwang’. Narendra Modi was in zugzwang after the Pulwama attacks a few days ago—as any Indian prime minister in his place would have been.

An Indian PM, after an attack for which Pakistan is held responsible, has only unsavoury choices in front of him. He is pulled in two opposite directions. One, strategy dictates that he must not escalate. Two, politics dictates that he must.

Let’s unpack that. First, consider the strategic imperatives. Ever since both India and Pakistan became nuclear powers, a conventional war has become next to impossible because of the threat of a nuclear war. If India escalates beyond a point, Pakistan might bring their nuclear weapons into play. Even a limited nuclear war could cause millions of casualties and devastate our economy. Thus, no matter what the provocation, India needs to calibrate its response so that the Pakistan doesn’t take it all the way.

It’s impossible to predict what actions Pakistan might view as sufficient provocation, so India has tended to play it safe. Don’t capture territory, don’t attack military assets, don’t kill civilians. In other words, surgical strikes on alleged terrorist camps is the most we can do.

Given that Pakistan knows that it is irrational for India to react, and our leaders tend to be rational, they can ‘bleed us with a thousand cuts’, as their doctrine states, with impunity. Both in 2001, when our parliament was attacked and the BJP’s Atal Bihari Vajpayee was PM, and in 2008, when Mumbai was attacked and the Congress’s Manmohan Singh was PM, our leaders considered all the options on the table—but were forced to do nothing.

But is doing nothing an option in an election year?

Leave strategy aside and turn to politics. India has been attacked. Forty soldiers have been killed, and the nation is traumatised and baying for blood. It is now politically impossible to not retaliate—especially for a PM who has criticized his predecessor for being weak, and portrayed himself as a 56-inch-chested man of action.

I have no doubt that Modi is a rational man, and knows the possible consequences of escalation. But he also knows the possible consequences of not escalating—he could dilute his brand and lose the elections. Thus, he is forced to act. And after he acts, his Pakistan counterpart will face the same domestic pressure to retaliate, and will have to attack back. And so on till my home in Versova is swallowed up by a nuclear crater, right?

Well, not exactly. There is a way to resolve this paradox. India and Pakistan can both escalate, not via military actions, but via optics.

Modi and Imran Khan, who you’d expect to feel like the loneliest men on earth right now, can find sweet company in each other. Their incentives are aligned. Neither man wants this to turn into a full-fledged war. Both men want to appear macho in front of their domestic constituencies. Both men are masters at building narratives, and have a pliant media that will help them.

Thus, India can carry out a surgical strike and claim it destroyed a camp, killed terrorists, and forced Pakistan to return a braveheart prisoner of war. Pakistan can say India merely destroyed two trees plus a rock, and claim the high moral ground by returning the prisoner after giving him good masala tea. A benign military equilibrium is maintained, and both men come out looking like strong leaders: a win-win game for the PMs that avoids a lose-lose game for their nations. They can give themselves a high-five in private when they meet next, and Imran can whisper to Modi, “You’re a good spinner, bro.”

There is one problem here, though: what if the optics don’t work?

If Modi feels that his public is too sceptical and he needs to do more, he might feel forced to resort to actual military escalation. The fog of politics might obscure the possible consequences. If the resultant Indian military action causes serious damage, Pakistan will have to respond in kind. In the chain of events that then begins, with body bags piling up, neither man may be able to back down. They could end up as prisoners of circumstance—and so could we.

***

Also check out:

Why Modi Must Learn to Play the Game of Chicken With Pakistan—Amit Varma
The Two Pakistans—Episode 79 of The Seen and the Unseen
India in the Nuclear Age—Episode 80 of The Seen and the Unseen

© 2007 IndiaUncut.com. All rights reserved.
India Uncut * The IU Blog * Rave Out * Extrowords * Workoutable * Linkastic

The other day, I happened to sneak out some time for myself after having sent the kids to play in the neighborhood park. I made myself a hot cup of coffee and settled on the couch hoping to enjoy the silence in the house. But was it really ...(read more)

Hello,

I have created an appForm with  the following attachmentList and size:

?attachmentList list(hicLeftPositionSet | hicRightPositionSet ; field 1
                     hicLeftPositionSet | hicRightPositionSet ; field 2
etc.

?initialSize    800:800
?minSize        800:800
?maxSize       1600:800

If I reduce the minimum y-size (?minSize        800:200), scrollbars are not inserted, unless I remove the attachmentList constraints.

Is it possible to have both scrollbars and "hicLeftPositionSet | hicRightPositionSet"? 

Thank you,

Best regards,

Aldo

Here we conclude the blog series and highlight the results of Mediatek 's use of Cadence Perspec™ System Verifier for their SoC level verification. In case you missed it, Part 1 of the blog is here , and Part 2 of the blog is here . One of their key...(read more)

What is a Power Distribution Network (PDN) after all but resistance, inductance, and capacitance in the PCB and components? And, of course, it is there to deliver the right current and voltage to each component on your PCB. But is that all? Are there oth...(read more)

Hello

The document I referenced is https://filebox.ece.vt.edu/~symort/rfworkshop/Mixer_workshop_instruction.pdf. (This is cadence workshop document)

While following the pxf simulation in the above article, the results are different and I have a question.

My result picture is shown below.

<my result error>

<document result>

<my direct plot>

<document direct plot>

The difference with the documentation is that in the direct plot screen after the pxf simulation,

1.output harmonics-> input sideband

2.Frequency axis: out-> frequency axis: absin

3.The results for port0 (RF port) are also different (see photo below).

4.The frequency values in the box are different.

My screen shows 5G, 10G, 1K ~ 10M, but the document is the same as 1K ~ 10M.

Ask for a solution. Thank you.

Other tools allow a sanity check of placement density vs available board space.  There is an older post "Skill code to evaluate all components area (Accumulative Place bound area)"  (9 years ago) that has a couple of examples that no longer work or expired.

This would be useful to provide feedback to schismatic and project managers regarding the component density on the PCB and how it will affect the routing abilities.  Thermal considerations can be evaluated as well 

Has anyone attempted this or still being done externally in spread sheets?

Hi,

I have to Take DRC report by cadence skill code I don't know the command to get Element 1 and Element 2 Report any one please help me out.

Hello All,

May I know if there is a way to breakup a selected clinesegment into a few clinesegments by just using SKILL code

Thanks All

This is the 17th installment of The Rationalist, my column for the Times of India.

One of my favourite English words comes from chess. If it is your turn to move, but any move you make makes your position worse, you are in ‘Zugzwang’. Narendra Modi was in zugzwang after the Pulwama attacks a few days ago—as any Indian prime minister in his place would have been.

An Indian PM, after an attack for which Pakistan is held responsible, has only unsavoury choices in front of him. He is pulled in two opposite directions. One, strategy dictates that he must not escalate. Two, politics dictates that he must.

Let’s unpack that. First, consider the strategic imperatives. Ever since both India and Pakistan became nuclear powers, a conventional war has become next to impossible because of the threat of a nuclear war. If India escalates beyond a point, Pakistan might bring their nuclear weapons into play. Even a limited nuclear war could cause millions of casualties and devastate our economy. Thus, no matter what the provocation, India needs to calibrate its response so that the Pakistan doesn’t take it all the way.

It’s impossible to predict what actions Pakistan might view as sufficient provocation, so India has tended to play it safe. Don’t capture territory, don’t attack military assets, don’t kill civilians. In other words, surgical strikes on alleged terrorist camps is the most we can do.

Given that Pakistan knows that it is irrational for India to react, and our leaders tend to be rational, they can ‘bleed us with a thousand cuts’, as their doctrine states, with impunity. Both in 2001, when our parliament was attacked and the BJP’s Atal Bihari Vajpayee was PM, and in 2008, when Mumbai was attacked and the Congress’s Manmohan Singh was PM, our leaders considered all the options on the table—but were forced to do nothing.

But is doing nothing an option in an election year?

Leave strategy aside and turn to politics. India has been attacked. Forty soldiers have been killed, and the nation is traumatised and baying for blood. It is now politically impossible to not retaliate—especially for a PM who has criticized his predecessor for being weak, and portrayed himself as a 56-inch-chested man of action.

I have no doubt that Modi is a rational man, and knows the possible consequences of escalation. But he also knows the possible consequences of not escalating—he could dilute his brand and lose the elections. Thus, he is forced to act. And after he acts, his Pakistan counterpart will face the same domestic pressure to retaliate, and will have to attack back. And so on till my home in Versova is swallowed up by a nuclear crater, right?

Well, not exactly. There is a way to resolve this paradox. India and Pakistan can both escalate, not via military actions, but via optics.

Modi and Imran Khan, who you’d expect to feel like the loneliest men on earth right now, can find sweet company in each other. Their incentives are aligned. Neither man wants this to turn into a full-fledged war. Both men want to appear macho in front of their domestic constituencies. Both men are masters at building narratives, and have a pliant media that will help them.

Thus, India can carry out a surgical strike and claim it destroyed a camp, killed terrorists, and forced Pakistan to return a braveheart prisoner of war. Pakistan can say India merely destroyed two trees plus a rock, and claim the high moral ground by returning the prisoner after giving him good masala tea. A benign military equilibrium is maintained, and both men come out looking like strong leaders: a win-win game for the PMs that avoids a lose-lose game for their nations. They can give themselves a high-five in private when they meet next, and Imran can whisper to Modi, “You’re a good spinner, bro.”

There is one problem here, though: what if the optics don’t work?

If Modi feels that his public is too sceptical and he needs to do more, he might feel forced to resort to actual military escalation. The fog of politics might obscure the possible consequences. If the resultant Indian military action causes serious damage, Pakistan will have to respond in kind. In the chain of events that then begins, with body bags piling up, neither man may be able to back down. They could end up as prisoners of circumstance—and so could we.

***

Also check out:

Why Modi Must Learn to Play the Game of Chicken With Pakistan—Amit Varma
The Two Pakistans—Episode 79 of The Seen and the Unseen
India in the Nuclear Age—Episode 80 of The Seen and the Unseen

The India Uncut Blog © 2010 Amit Varma. All rights reserved.
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  A few weeks ago, we talked about template text labels for design-specific information. There, we were focused on labels that are specific to the design as a whole: revision information, dates, authors, etc. Today, we’re looking at a diff...(read more)

In the Allegro back-end layout products like Allegro Package Designer Plus, it would be reasonable to assume that the most often used command is none other than “show element” (shortcut key F4). This command, runnable at nearly any t...(read more)

I am using PCB Editor v17.2-2016.

I tried to do placement by schematic page but not all pages are displayed.

Earlier, I successfully do the placement by schematic pages and it was showing all the pages. But then I decided to delete all placed components and to do placement again.

When I try to do placement by schematic page again, I noticed that only the pages that I have successfully do all the placement previously are missing.

Hi,

I am currently struggling with measuring the delay between two clocks with a sufficient accuracy. The reference one is a fixed-phase clock, and the other one is a squared clock resulting of a circuit (kind of PLL) synthesis.
As I need to run a large amount of Monte-Carlo simulations in transient noise, I need to improve the simulation speed, while keeping a satisfactory delay measurement accuracy (<0.1ps), more specifically at 0V-crossings of the differential clocks. So I cannot simply set a max timestep <0.1ps as it would be far too long to simulate.
To sum up, I would need a very relaxed timestep on clock up and down levels, and a very short timestep only at rise/fall transitions.

For this purpose, I wrote a Verilog-A script
- using a timmer function to accurately emulate the reference clock 0V-crossing times (and get the related times with $abstime)
- using @(cross to get the 0V-crossing times of the synthesized clock: but this is not accurate enough (I see simulation noise around 3ps in Conservative). Indeed, the "cross" event occures at the simulation time following the effective 0V-crossing time; this could be sometimes >3ps, far not enough accurate for my purpose.
- I have tried to replace the cross with the "above" function, but it hasn't changed anything, whatever the time_tol value I put (<0.1ps for instance), the result is the same as with the "cross" function and the points are larger than >>0.1ps, weirdly.

So I have decided to give up Verilog-A to measure the delay between my two clocks.
I am currently trying to use the "delay" function of the Cadence Calculator as I guess it will "extrapolate" the time between two simulation points and therefore give a more accurate measurement of the 0V-crossing events, but when I try to compute the delay difference between the synthesized clock and the reference clock, it returns "0".

...

Could you please give me hints to dramatically improve my 0V-crossing time measurements while relaxing the simulation time?
- either by helping me in writing a more suitable Verilog-A script
- or by helping me in using the "delay" function of the calculator
- or maybe by providing me a "magic" Skill function?
Using AMS+Multithread simulator...

Thanks a lot in advance for your help and best regards.

Hi,

This question is related to the constraint measurement criteria used by the Liberate inside view. I am trying to characterize a specific D flip-flop for low voltage operation (0.6V) using Cadence Liberate (V16). 

When the "define_arcs" are not explicitly specified in the settings for the circuit (but the input/outputs are indeed correct in define_cell), the inside view seems to probe an internal node (i.e. master latch output)  for constraint measurements instead of the Q output of the flip flop. So to force the tool to probe Q output I added following coder in constraint arcs :

# constraint arcs from CK => D
define_arc
-type hold
-vector {RRx}
-related_pin CP
-pin D
-probe Q
DFFXXX

define_arc
-type hold
-vector {RFx}
-related_pin CP
-pin D
-probe Q
DFFXXX

define_arc
-type setup
-vector {RRx}
-related_pin CP
-pin D
-probe Q
DFFXXX

define_arc
-type setup
-vector {RFx}
-related_pin CP
-pin D
-probe Q
DFFXXX

with -probe Q liberate identifies Q as the output, but uses Glitch-Peak criteria instead of delay degradation method. So what could be the exact reason for this unintended behavior ? In my external (spectre) spice simulation, the Flip-Flop works well and it does not show any issues in the output delay degradation when the input sweeps.

Thanks

Anuradha

Hi Everyone,

Many of you would have heard about the Cadence Stylus Common UI and are wondering what it is and what the advantages might be to use it versus legacy UI.

The webinar answers the following questions:

• Why did Cadence develop Stylus UI and what is Stylus Common UI?
• How does someone invoke and use the Stylus Common UI?
• What are some of the important and useful features of the Stylus Common UI?
• What are the key ways in which the Stylus Common UI is different from the default UI?​

If you want to learn more about Stylus UI in the context of implementation, view the 45-minute recorded webinar on the Cadence support site.

Related Resource

Innovus Block Implementation with Stylus Common UI

Vinita Nelson

Verification is the top challenge in mixed-signal design. Bringing analog and digital domains together into unified verification planning, simulating, and debugging is a challenging task for rapidly increasing size and complexity of mixed-signal designs. To more completely verify functionality and performance of a mixed-signal SoC and its AMS IP blocks used to build it, verification teams use simulations at transistor, analog behavioral and real-number model (RNM) and RTL levels, and combination of these.

In recent years, RNM and simulation is being adopted for functional verification by many, due to advantages it offers including simpler modeling requirements and much faster simulation speed (compared to a traditional analog behavioral models like Verilog-A or VHDL-AMS). Verilog-AMS with its wreal continue to be popular choice. Standardization of real number extensions in SystemVerilog (SV) made SV-RNM an even more attractive choice for MS SoC verification.

Verilog-AMS/wreal is scalar real type. SV-RNM offers a powerful ability to define complex data types, providing a user-defined structure (record) to describe the net value. In a typical design, most analog nodes can be modeled using a single value for passing a voltage (or current) from one module to another. The ability to pass multiple values over a net can be very powerful when, for example, the impedance load impact on an analog signal needs to be modeled. Here is an example of a user-defined net (UDN) structure that holds voltage, current, and resistance values:

When there are multiple drives on a single net, the simulator will need a resolution function to determine the final net value. When the net is just defined as a single real value, common resolution functions such as min, max, average, and sum are built into the simulator.  But definition of more complex structures for the net also requires the user to provide appropriate resolution functions for them. Here is an example of a net with three drivers modeled using the above defined structural elements (a voltage source with series resistance, a resistive load, and a current source):

To properly solve for the resulting output voltage, the resolution function for this net needs to perform Norton conversion of the elements, sum their currents and conductances, and then calculate the resolved output voltage as the sum of currents divided by sum of conductances.

With some basic understanding of circuit theory, engineers can use SV-RNM UDN capability to model electrical behavior of many different circuits. While it is primarily defined to describe source/load impedance interactions, its use can be extended to include systems including capacitors, switching circuits, RC interconnect, charge pumps, power regulators, and others. Although this approach extends the scope of functional verification, it is not a replacement for transistor-level simulation when accuracy, performance verification, or silicon correlation are required:  It simply provides an efficient solution for discretely modeling small analog networks (one to several nodes).  Mixed-signal simulation with an analog solver is still the best solution when large nonlinear networks must be evaluated.

Cadence provides a tutorial on EEnet usage as well as the package (EEnet.pkg) with UDN definitions and resolution functions and modeling examples. To learn more, please login to your Cadence account to access the tutorial.

Since the release of the Automated Device Placement and Routing solution last year, we have continued to improve and build upon it. In this blog, I’ll talk about the latest addition—the Auto Device Array form—how this is an integral piece of the new Automated Device Placement and Routing solution.(read more)

visit News18 Urdu for latest news, breaking news, news headlines and updates from Tamenglong on politics, sports, entertainment, cricket, crime and more.

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•An in silico clinical trial is underway with the 3DEXPERIENCE platform to evaluate the Living Heart simulated 3D heart for transforming how new devices can be tested •Five-year extension of their collaborative research agreement aims to spur medical device innovation by enabling innovative, new product designs •Both Dassault Systèmes and the FDA recognize the transformative impact of modeling and simulation on public health and patient safety

•Customers can seamlessly extend their design to manufacturing ecosystem to the cloud with the integrated 3DEXPERIENCE.WORKS portfolio, enabling new levels of functionality, collaboration, agility and operational efficiency •Latest release of 3D design and engineering portfolio features hundreds of enhancements, new capabilities and workflows to accelerate and improve product development •Over six million SOLIDWORKS users can innovate products faster with better performance and streamlined...