The present invention relates to a subsurface refuse collection system comprising an underground bunker (4), a refuse container (3), a deposit bin (1) and a cover (2) with automatic opening and closing which can be powered electrically using a solar system. The container (3) is collected by means of an automated crane (18) with automatic hitching to facilitate collection. The system is equipped with multiple devices to measure volume and weight of the refuse deposited in the deposit bin (1), for the purpose of system monitoring or improvements to the management of truck routes. It also includes a safety device to prevent accidental fails into the underground bunker during collection.

A process for encapsulating a radioactive object to render the object suitable for shipment and/or storage, and including the steps of preparing a plastic material, causing the plastic material to react with a foaming agent, generating a foaming plastic, encapsulating the radioactive object in the foaming plastic, and allowing the foaming plastic to solidify around the radioactive object to form an impervious coating.

Embodiments of this disclosure relate to tissue digestion and, more particularly, to methods and apparatuses for varying the number, size, and/or location of one or more tissue compartments within a digestive fluid vessel. Some examples include partitions that may be selectively positioned within a vessel (and may be selectively removable from the vessel) to create one or more tissue compartments. The partitions may be positioned, repositioned and rearranged within the vessel to form one or more tissue compartments. The partitions may be solid or include apertures, and may be oriented in horizontally and/or vertically. Alternate embodiments include one or more selectively closeable apertures that permit digestive fluid to circulate along alternate pathways, which can permit tissue digestion with reduced digestive fluid levels. Still further embodiments include baskets that are selectively positionable within the tissue digester. The baskets may also include one or more selectively positionable and/or repositionable partitions.

The invention provides a method and apparatus for creating plasma particles and applying the plasma particles to a liquid. Liquid feedstock (e.g., water and/or hydrocarbons mixed with biomass) is pumped through a pipeline; the single-phase stream is then transformed into a biphasic liquid-and-gas stream inside a chamber. The transformation is achieved by transitioning the stream from a high pressure zone to a lower-pressure zone. The pressure drop may occur when the stream further passes through a device for atomizing liquid. Inside the chamber, an electric field is generated with an intensity level that exceeds the threshold of breakdown voltage of the biphasic medium leading to a generation of a plasma state. Furthermore, the invention provides an energy-efficient highly adaptable and versatile method and apparatus for sanitizing water using plasma particles to inactivate biological agents contaminating water.

Degradation of phosphate esters, particularly neurotoxins and pesticides, is performed using high oxidative state molybdenum complexes, more particularly molybdenum(VI) complexes. A molybdenum(VI) complex is dissolved in water and then reacted with a phosphate ester. The phosphate esters can include, but are not limited to, VX, VE, VG, VM, GB, GD, GA, GF, parathion, paraoxon, triazophos, oxydemeton-methyl, chlorpyrifos, fenitrothion and pirimiphos-methyl, representing both chemical warfare agents as well as pesticides and insecticides.

A pesticidal composition comprising 4-phenoxyphenyl 2-(2-pyridyloxy)propyl ether; a hydrophobic organic solvent capable of dissolving 0.1-fold by weight of 4-phenoxyphenyl 2-(2-pyridyloxy)propyl ether at 0° C.; polyvinyl alcohol; a nonionic surfactant selected from the group consisting of alkoxylated castor oil, alkoxylated hydrogenated castor oil and alkoxylated hydrogenated castor oil fatty acid ester; and water, is excellent in storage stability.

A treatment process of persistent organic pollutants contained in particles is provided. Said process includes reacting persistent organic pollutant in particles under hydrothermal conditions in the presence of Fe2+ and Fe3+. Several beneficial effects can be achieved, including 1) no other additive is needed during the reaction process; 2) Fe2+ and Fe3+ are safe, cheap and extensive sources; 3) because Fe2+ and Fe3+ are dissolved, they can fully disperse into particles, and fully contact can be achieved, thus obtaining a decomposition rate no less than 70% of the persistent organic pollutants is under subcritical conditions.

An embodiment of the present invention relates to a method for treating spent caustic soda generated from an oil refinery process, a petrochemical process, etc. through a process in which a series of treatment steps are integrated, wherein the method can constitute a process under mild conditions excluding high temperature and/or high pressure conditions and can be advantageous to a post treatment process since the amount of by-products is small.

Method and apparatus for disposal of used home medication which comprises an outer container being sealable and disposable containing an inner water-soluble packet/bag of gelling agent and coloring agent for stabilizing the used medication wherein the outer container comprises a foil-type container having a double sealing mechanism including a first zip lock sealing portion and a second self-sticking sealing portion to insure that the contents are safely sealed prior to disposal in a conventional home solid waste disposal unit.

The cost relating to a reduction in volume and storage of a waste resin including a radioactive nuclide is reduced. In an aspect of the invention, a volume reduction processing system 1000 is provided. The volume reduction processing system 1000 includes a radioactivity meter 102 that measures the radioactivity of a processing target resin, a volume reduction processing device 110 that carries out a heating process, and an oxidation process using oxygen plasma P on the processing target resin, and a process stopping point computation unit 180 that determines a process stopping point for carrying out a volume reduction process on the processing target resin with the volume reduction processing device as far as a volume reduction target value. The volume reduction processing device 110 stops at least one process of the heating process and oxidation process on the process stopping point being reached.

A method and device for limiting the degassing of tritiated waste issued from the nuclear industry are provided. The method reduces an amount of generated tritiated hydrogen (T2 or HT) and/or tritiated water (HTO or T2O) including at least one piece of tritiated waste from the nuclear industry. The method includes placing the package in contact with a mixture including manganese dioxide (MnO2) combined with a component that includes silver; and placing the package in contact with a molecular sieve.

A method and apparatus for distributing objects. In one embodiment, the method comprises computing a modulus operand based on a number of objects to be distributed and a number of objects pertaining to a first category; computing a modulus operation based on a number of distributed objects and the modulus operand; and distributing a first object or a second object based on a result of computing the modulus operation.

Efficient computation of complex multiplication results and very efficient fast Fourier transforms (FFTs) are provided. A parallel array VLIW digital signal processor is employed along with specialized complex multiplication instructions and communication operations between the processing elements which are overlapped with computation to provide very high performance operation. Successive iterations of a loop of tightly packed VLIWs are used allowing the complex multiplication pipeline hardware to be efficiently used. In addition, efficient techniques for supporting combined multiply accumulate operations are described.

Systems and methods are provided for generating at least one high fidelity resource state. A classical code and punctured to provide a first set of generators and a second set of generators. The first set of generators is mapped to a set of stabilizer generators, and the second set of generators is mapped to a set of logical operators. A set of resource states are prepared in physical qubits. A decoding process is performed on the resource states according to a quantum code represented by the set of stabilizer generators and the set of logical operators, and qubits corresponding to the stabilizers are measured.

The present technique relates to a reception device and a reception method which can improve equalization performance. An equalization processing unit has a time domain equalization unit which equalizes a received signal in a time domain and a frequency domain equalization unit which is provided in parallel to the time domain equalization unit and which equalizes the received signal in a frequency domain, and performs control of switching between the time domain equalization unit and the frequency domain equalization unit. The present technique can be applied to, for example, equalize a signal of data transmitted by way of single carrier transmission or data transmitted by way of multicarrier transmission.

An acoustic apparatus including circuitry to correct for acoustic cross-coupling of acoustic drivers mounted in a common acoustic enclosure. A plurality of acoustic drivers are mounted in the acoustic enclosure so that motion of each of the acoustic drivers causes motion in each of the other acoustic drivers. A canceller cancels the motion of each of the acoustic drivers caused by motion of each of the other acoustic drivers. A cancellation adjuster cancels the motion of each of the acoustic drivers that may result from the operation of the canceller.

Apparatus comprising an input connected to receive an input signal, a lookup table comprising a plurality of input entries and first and second output entries for each input entry. The look up table receives the input signal and returns a lower input entry, an upper input entry, the second output entry for the lower input entry, and the first output entry for the upper input entry. A first subtractor subtracts the lower input entry from the input signal to produce a first difference. A second subtractor subtracts the input signal from the upper input entry to produce a second difference. First and second multipliers multiply the first and second differences by the first output entry for the upper input entry and the second output entry for the lower input entry, respectively, to produce first and second products. An adder adds the first and second products to produce an output signal.

A method for computer-implemented unit-conversion method, the method comprising identifying a first numerical value in a first system of units displayed on a computing device, converting the first numerical value in the first system of units into a second numerical value, and displaying the second numerical value and the second system of units on the computing device.

A barrel shifter uses a sign magnitude to 2's complement converter to generate decoder signals for its cascaded multiplexer selectors. The sign input receives the shift direction and the magnitude input receives the shift amount. The sign magnitude to 2's complement converter computes an output result as a 2's complement of the shift amount using the shift direction as a sign input, assigns a first portion (most significant bit half) of the output result to a first decoder signal, and assigns a second portion (least significant bit half) of the output result to a second decoder signal. This encoding scheme allows the decoder circuits to be relatively simple, for example, 3-to-8 decoders for an implementation adapted to shift a 64-bit operand value rather than the 4-to-9 decoder required in a conventional barrel shifter, leading to faster operation, less area, and reduced power consumption.

The generation of individual-specific information having a good reliability and uniqueness is made possible with a little circuit scale. For this purpose, in an individual-specific information generation apparatus, a plurality of digital circuits are in the same circuit configuration. Each of the digital circuits outputs a fixed or a random number output value individually without their output with respect to a certain input being determined unambiguously among the digital circuits. In each of the digital circuit, an order is defined in advance. A random number judgment unit judges whether the output value is a random value or fixed, for each of the plurality of digital circuits. An individual-specific information generation unit generates the individual-specific information based on information of the order defined in the digital circuit judged by the random number judgment unit as having a fixed output value among the plurality of digital circuits and the output value.

A sine wave generator for a Direct Digital Synthesizer (DDS) converts a digital phase input into a digital sine wave output. Sine values and slopes are stored in read-only memory (ROM) for coarse upper phase bits in a first quadrant. A quadrant folder and phase splitter reflects and inverts values from the first quadrant to generate amplitudes for all four quadrants. Each sine value and slope is stored for a range of lower phase bits. A Delta bit separates upper and lower phase bits. Delta conditionally inverts the lower phase bits, the sine value, and the final polarity. A reduced AND logic array multiplies the slope by the conditionally inverted lower phase bits. A reconstructed ADD logic array then adds the conditionally inverted sine value. The conditionally inverted polarity is added to generate the final sine value. Sine generation logic is streamlined with conditional inversion based on the Delta bit.

Disclosed is a processor that is able to efficiently execute DFT operations without having part of a basic operational circuit idle even during non-DFT-operation processing. The processor (1) has an operational means (operation unit) (2) and a control means (control unit) (3). The operation means (2) has a plurality of shift addition-and-subtraction means connected such that CORDIC (COordinate Rotation DIgital Computer) operations can be executed. The shift adding-and-subtracting means also execute shift addition-and-subtraction processing of butterfly operations that process shift addition-and-subtraction for one stage or more. The control means (3) instructs the operation means (2) to execute either CORDIC operations or butterfly operations, based on a plurality of data received from the outside.

A circuit arrangement and method couple a hardware-based pseudorandom number generator (PRNG) to an execution unit in such a manner that pseudorandom numbers generated by the PRNG may be selectively output to the execution unit for use as an operand during the execution of instructions by the execution unit. A PRNG may be coupled to an input of an operand multiplexer that outputs to an operand input of an execution unit so that operands provided by instructions supplied to the execution unit are selectively overridden with pseudorandom numbers generated by the PRNG. Furthermore, overridden operands provided by instructions supplied to the execution unit may be used as seed values for the PRNG.

A data collection unit obtains physiological data from a subject interface on a subject. The subject interface can be connected to the data collection unit. When the subject interface is connected to the data collection unit, subject interface contacts on the subject interface make contact with data collection unit contacts on the data collection unit. Some of the data collection unit contacts are for communicating physiological data from the subject interface to the data collection unit. Some of the contacts are for powering the data collection unit upon the subject interface being connected to the data collection unit and for powering down the data collection unit upon the subject interface being disconnected from the data collection unit.

An independently functioning or centrally controlled wall light switch is configured to operate in normal mode and a Jewish holiday mode wherein the state of the light is fixed, regardless of the user's physical manipulation of the light switch. The control system automatically activates holiday mode by combining a geographically determined Jewish religious clock executed by software and hardware that utilizes the current time, date and geographical location of the apparatus in accordance with the Jewish definition of time and laws for calculating numerous religiously significant shifting daily points in time. The control system further incorporates several energy saving and preference modes by utilizing a particular day's calculated religious points in time in conjunction with holiday behavior patterns common to most Jewish families to provide the user with a greatly simplified means of programming an automatically adjusting on/off light timer and dimming overlay functionality during holiday mode.

Techniques for fast filtering for a transceiver are presented. A multidimensional filter processor component (MDFPC) can perform configurations and adaptations of multiple digital filters of a transceiver. The MDFPC can treat multiple, separate filters of a transceiver as a single larger multidimensional filter, and jointly update the multiple filters in a single adaptation operation instead of performing multiple adaptation operations on multiple filters. To facilitate multidimensional filter adaptation, the MDFPC can manage respective cross-correlations associated with the inputs of the filters. The MDFPC can facilitate multidimensional filter adaptation by performing multidimensional filter adaptation in the frequency domain, wherein the adaptation can be performed in parallel for multiple frequency sub-channels. For each frequency sub-channel, the MDFPC can perform a filter adaptation, wherein respective filter adaptation matrices can be generated for respective frequency sub-channels to perform the update to facilitate managing different cross-correlations associated with different frequency sub-channels.

Memory system operations are extended for a data processor by DMA, cache, or memory controller to include a DMA descriptor, including a set of operations and parameters for the operations, which provides for data compression and decompression during or in conjunction with processes for moving data between memory elements of the memory system. The set of operations can be configured to use the parameters and perform the operations of the DMA, cache, or memory controller. The DMA, cache, or memory controller can support moves between memory having a first access latency, such as memory integrated on the same chip as a processor core, and memory having a second access latency that is longer than the first access latency, such as memory on a different integrated circuit than the processor core.

Method, apparatus, and program means for performing a conversion. In one embodiment, a disclosed apparatus includes a destination storage location corresponding to a first architectural register. A functional unit operates responsive to a control signal, to convert a first packed first format value selected from a set of packed first format values into a plurality of second format values. Each of the first format values has a plurality of sub elements having a first number of bits The second format values have a greater number of bits. The functional unit stores the plurality of second format values into an architectural register.

Method, apparatus, and program means for performing a conversion. In one embodiment, a disclosed apparatus includes a destination storage location corresponding to a first architectural register. A functional unit operates responsive to a control signal, to convert a first packed first format value selected from a set of packed first format values into a plurality of second format values. Each of the first format values has a plurality of sub elements having a first number of bits The second format values have a greater number of bits. The functional unit stores the plurality of second format values into an architectural register.

In accordance with one or more aspects, an initial output string is generated by a random number generator. The initial output string is sent to a random number service, and an indication of failure is received from the random number service if the initial output string is the same as a previous initial output string received by the random number service. Operation of the device is ceased in response to the indication of failure. Additionally, entropy estimates for hash values of an entropy source can be generated by an entropy estimation service based on hash values of various entropy source values received by the entropy estimation service. The hash values can be incorporated into an entropy pool of the device, and the entropy estimate of the pool being updated based on the estimated entropy of the entropy source.

Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes a data detector circuit. The data detector circuit includes an anti-causal noise predictive filter circuit and a data detection circuit. In some cases, the anti-causal noise predictive filter circuit is operable to apply noise predictive filtering to a detector input to yield a filtered output, and the data detection circuit is operable to apply a data detection algorithm to the filtered output derived from the anti-causal noise predictive filter circuit.

A recursive type-IV discrete cosine transform system includes a first permutation device, a recursive type-III discrete cosine/sine transform device, a cosine/sine factor generation device, a recursive type-II discrete cosine/sine transform device, a second permutation device. The first permutation device performs two-dimensional order permutation operation on N digital signals for generating N two-dimensional first temporal signals. The recursive type-III discrete cosine/sine transform device repeats a type-III discrete cosine/sine transform for generating second temporal signals. The cosine/sine factor generation device sequentially performs cosine/sine factor multiplication and corresponding addition operations for generating third temporal signals. The recursive type-II discrete cosine/sine transform device repeats a type-II discrete cosine/sine transform for generating fourth temporal signals. The second permutation device performs a one-dimensional order permutation operation for generating N one-dimensional output signals. The N one-dimensional output signals are obtained by performing a type-IV discrete cosine transform on the N digital input signals.

Solving computational problems may include generating a logic circuit representation of the computational problem, encoding the logic circuit representation as a discrete optimization problem, and solving the discrete optimization problem using a quantum processor. Output(s) of the logic circuit representation may be clamped such that the solving involves effectively executing the logic circuit representation in reverse to determine input(s) that corresponds to the clamped output(s). The representation may be of a multiplication circuit. The discrete optimization problem may be composed of a set of miniature optimization problems, where each miniature optimization problem encodes a respective logic gate from the logic circuit representation. A multiplication circuit may employ binary representations of factors, and these binary representations may be decomposed to reduce the total number of variables required to represent the multiplication circuit.

Method, apparatus, and program means for performing a conversion. In one embodiment, a disclosed apparatus includes a destination storage location corresponding to a first architectural register. A functional unit operates responsive to a control signal, to convert a first packed first format value selected from a set of packed first format values into a plurality of second format values. Each of the first format values has a plurality of sub elements having a first number of bits The second format values have a greater number of bits. The functional unit stores the plurality of second format values into an architectural register.

Method, apparatus, and program means for performing a conversion. In one embodiment, a disclosed apparatus includes a destination storage location corresponding to a first architectural register. A functional unit operates responsive to a control signal, to convert a first packed first format value selected from a set of packed first format values into a plurality of second format values. Each of the first format values has a plurality of sub elements having a first number of bits The second format values have a greater number of bits. The functional unit stores the plurality of second format values into an architectural register.

A random number generation method and apparatus using a low-power microprocessor is provided. In the random number generation method, a low-power microprocessor determines whether external power is supplied to a random number generator. The low-power microprocessor updates an internal state of the random number generator based on a first scheme if it is determined that the external power is supplied to the random number generator. The low-power microprocessor updates the internal state of the random number generator based on a second scheme different from the first scheme if it is determined that the external power is not supplied to the random number generator.

Apparatus and method for processing linear systems of equations and finding a n×1 vector x satisfying Ax=b where A is a symmetric, positive-definite n×n matrix corresponding to n×n predefined high-precision elements and b is an n1 vector corresponding to n predefined high-precision elements. A first iterative process generates n low-precision elements corresponding to an n×1 vector xl satisfying Alxl=bl where Al, bl are elements in low precision. The elements are converted to high-precision data elements to obtain a current solution vector x. A second iterative process generates n low-precision data elements corresponding to an n×1 correction vector dependent on the difference between the vector b and the vector product Ax. Then there is produced from the n low-precision data elements of the correction vector respective high-precision data elements of an n×1 update vector u. The data elements of the current solution vector x are updated such that x=x+u.

Distributed processing system and method for discrete logarithm calculation. The speed and resource efficiency of discrete logarithm calculation may be improved by allowing a plurality of operation agents to distributively process an operation of generating a modulo multiplication auxiliary table, an operation of generating a pre-calculation table, and an operation of searching for an answer by applying an iterated function for discrete logarithm calculation in a discrete logarithm calculation operation using the pre-calculation table.

A communication device includes a storage unit to store quotients and remainders associated with multiplication values obtained by multiplying a specified integer number, which is expressed in a form of (2β+α) where β is a positive integer number and α is a positive integer number other than integral multiples of 2, respectively, the quotients and the remainders being obtained by dividing the multiplication values by 2β, respectively, a first unit to divide a dividend by 2βand calculate a quotient and a remainder, a second unit to obtain a quotient, which corresponds to the remainder from the storage unit, and a third unit to determine that the data length of the packet data is normal, when a combination of the quotient and the remainder calculated by the first unit is in the storage unit.

A multiplier circuit for multiplying first and second binary values includes a first logic circuit, a priority encoder, a shifter circuit, and an accumulator. The first logic circuit receives the first binary value and a multiplier modifier, and modifies the first binary value based on the multiplier modifier. The multiplier modifier is generated by the priority encoder. The priority encoder also generates a position binary value indicating the position of a most significant set bit in the modified first binary value. The shifter circuit receives the position binary value from the priority encoder and the second binary value and generates an intermediate result. The accumulator accumulates one or more of the intermediate results and generates a final product that is a product of the first and second binary values.

A method includes receiving a dividend and a divisor for performing a division operation. Numbers p and n are found, for which the divisor equals 2n(1+2p). An interim result, which is equal to a reciprocal of 1+2p multiplied by the dividend, is calculated. The interim result is divided by 2n to produce a result of the division operation.

Techniques for medium access control. Some techniques include receiving, at a first computing device, a solicitation for at least a first medium access request that specifies at least one time period for transmitting the first medium access request to the second computing device; encoding the first medium access request at least in part by using a compressive sensing encoding technique to obtain a first encoded medium access request; and transmitting the first encoded medium access request to the second computing device during the at least one time period specified in the received solicitation.

In this application, a set of orthogonal functions is introduced whose power spectral densities are all rectangular shape. To find the orthogonal function set, it was considered that their spectrums (Fourier transforms of the functions) are either real-valued or imaginary-valued, which are corresponding to even and odd real-valued time domain signals, respectively. The time domain functions are all considered real-valued because they are actually physical signals. The shape of the power spectral densities of the signals are rectangular thus, the Haar orthogonal function set can be employed in the frequency domain to decompose them to several orthogonal functions. Based on the inverse Fourier transform of the Haar orthogonal functions, the time domain functions with rectangular power spectral densities can be determined. This is equivalent to finding the time-domain functions by taking the inverse Fourier transform of the frequency domain Walsh functions. The obtained functions are sampled and truncated to generate finite-length discrete signals. Truncation destroys the orthogonality of the signals. The Singular Value Decomposition method is used to restore the orthogonality of the truncated discrete signals.

Systems, devices, processors, and methods are described which may be used for the reception of a wireless broadband signal at a user terminal from a gateway via a satellite. A wireless signal may include a series of physical layer frames, each frame including a physical layer header and payload. The received signal is digitized and processed using various novel physical layer headers and related techniques to synchronize the physical layer frames and recover data from physical layer headers for purposes of demodulation and decoding.

A method of frequency-domain filtering is provided that includes a plurality of filters, the plurality of filters including at least one constrained filter(s) W=I, I and at least one unconstrained filter(s) W=1,K− The method includes cascading the W k=i,K unconstrained filter(s). A single constraint window C is applied to the cascaded W=i,K unconstrained filter(s). The W=1,I constrained filter(s) are cascaded with the constrained cascaded Wk=1,K unconstrained filter(s) to form a resulting filter Wll=C(W 1{circle around (x)} . . . {circle around (x)} W){circle around (x)} W . . . W. The frequency domain representation of the single constraint window C may be based, at least in part, on a time domain representation of a single constraint window C that has been circularly shifted such that the frequency domain representation of the constraint window matches a property of the frequency domain representation of the cascaded W=1,K unconstrained filters.

A function f(x) is calculated with a calculating apparatus that makes a correct calculation with a low probability. Provided that G and H are cyclic groups, f is a function that maps an element x of the group H into the group G, X1 and X2 are random variables whose values are elements of the group G, x1 is a realized value of the random variable X1, and x2 is a realized value of the random variable X2, an integer calculation part calculates integers a' and b' that satisfy a relation a'a+b'b=1 using two natural numbers a and b that are relatively prime. A first randomizable sampler is capable of calculating f(x)bx1 and designates the calculation result as u. A first exponentiation part calculates u'=ua. A second randomizable sampler is capable of calculating f(x)ax2 and designates the calculation result as v. A second exponentiation part calculates v'=vb. A determining part determines whether u'=v' or not. A final calculation part calculates ub'va' in a case where it is determined that u'=v'.

The disclosure is related systems and methods for using operation durations of a data storage medium to generate random numbers. In one embodiment, a device may comprise a random number generator circuit configured to store a value representing a duration of an operation on the data storage medium, and generate a random number based on the value. Another embodiment may be a method comprising recording durations of access operations to a data storage medium, and generating a random number based on the durations.

A method is provided for decimating a digital signal by a factor of M and matching it to a desired channel bandwidth. The method applies the digital signal input samples to a (M−1) stage tapped delay line, downsamples the input samples and the output samples of each tapped delay line stage by a factor of M, and applies each of the M downsampled sample value streams to M allpass IIR filters, respectively. The M allpass IIR filtered sample streams are then summed and scaled by a factor of 1/M. The result can then be filtered by a digital channel filter.

A method and apparatus for including in a processor instructions for performing logical-comparison and branch support operations on packed or unpacked data. In one embodiment, instruction decode logic decodes instructions for an execution unit to operate on packed data elements including logical comparisons. A register file including 128-bit packed data registers stores packed single-precision floating point (SPFP) and packed integer data elements. The logical comparisons may include comparison of SPFP data elements and comparison of integer data elements and setting at least one bit to indicate the results. Based on these comparisons, branch support actions are taken. Such branch support actions may include setting the at least one bit, which in turn may be utilized by a branching unit in response to a branch instruction. Alternatively, the branch support actions may include branching to an indicated target code location.

A method and apparatus for including in a processor instructions for performing logical-comparison and branch support operations on packed or unpacked data. In one embodiment, instruction decode logic decodes instructions for an execution unit to operate on packed data elements including logical comparisons. A register file including 128-bit packed data registers stores packed single-precision floating point (SPFP) and packed integer data elements. The logical comparisons may include comparison of SPFP data elements and comparison of integer data elements and setting at least one bit to indicate the results. Based on these comparisons, branch support actions are taken. Such branch support actions may include setting the at least one bit, which in turn may be utilized by a branching unit in response to a branch instruction. Alternatively, the branch support actions may include branching to an indicated target code location.