A semiconductor device has a semiconductor wafer with a plurality of contact pads. A first insulating layer is formed over the semiconductor wafer and contact pads. A portion of the first insulating layer is removed, exposing a first portion of the contact pads, while leaving a second portion of the contact pads covered. An under bump metallization layer and a plurality of bumps is formed over the contact pads and the first insulating layer. A second insulating layer is formed over the first insulating layer, a sidewall of the under bump metallization layer, sidewall of the bumps, and upper surface of the bumps. A portion of the second insulating layer covering the upper surface of the bumps is removed, but the second insulating layer is maintained over the sidewall of the bumps and the sidewall of the under bump metallization layer.

Embodiments of a method for fabricating stacked microelectronic packages are provided, as are embodiments of a stacked microelectronic package. In one embodiment, the method includes arranging microelectronic device panels in a panel stack. Each microelectronic device panel includes a plurality of microelectronic devices and a plurality of package edge conductors extending therefrom. Trenches are formed in the panel stack exposing the plurality of package edge conductors. An electrically-conductive material is deposited into the trenches and contacts the plurality of package edge conductors exposed therethrough. The panel stack is then separated into partially-completed stacked microelectronic packages. For at least one of the partially-completed stacked microelectronic packages, selected portions of the electrically-conductive material are removed to define a plurality of patterned sidewall conductors interconnecting the microelectronic devices included within the stacked microelectronic package.

It is an object to provide a semiconductor device including a thin film transistor with favorable electric properties and high reliability, and a method for manufacturing the semiconductor device with high productivity. In an inverted staggered (bottom gate) thin film transistor, an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer, and a buffer layer formed using a metal oxide layer is provided between the semiconductor layer and a source and drain electrode layers. The metal oxide layer is intentionally provided as the buffer layer between the semiconductor layer and the source and drain electrode layers, whereby ohmic contact is obtained.

A process for preparing a semiconductor structure for mounting to a carrier is disclosed. The process involves causing a support material to substantially fill a void defined by surfaces formed in the semiconductor structure and causing the support material to solidify sufficiently to support the semiconductor structure when mounted to the carrier.

A III-N device is described with a III-N material layer, an insulator layer on a surface of the III-N material layer, an etch stop layer on an opposite side of the insulator layer from the III-N material layer, and an electrode defining layer on an opposite side of the etch stop layer from the insulator layer. A recess is formed in the electrode defining layer. An electrode is formed in the recess. The insulator can have a precisely controlled thickness, particularly between the electrode and III-N material layer.

The object of the invention is to provide a method for fabricating a semiconductor device having a peeled layer bonded to a base material with curvature. Particularly, the object is to provide a method for fabricating a display with curvature, more specifically, a light emitting device having an OLED bonded to a base material with curvature. An external force is applied to a support originally having curvature and elasticity, and the support is bonded to a peeled layer formed over a substrate. Then, when the substrate is peeled, the support returns into the original shape by the restoring force, and the peeled layer as well is curved along the shape of the support. Finally, a transfer object originally having curvature is bonded to the peeled layer, and then a device with a desired curvature is completed.

Disclosed is a semiconductor device including an oxide semiconductor film. A first oxide semiconductor film with a thickness of greater than or equal to 2 nm and less than or equal to 15 nm is formed over a gate insulating layer. First heat treatment is performed so that crystal growth from a surface of the first oxide semiconductor film to the inside thereof is caused, whereby a first crystal layer is formed. A second oxide semiconductor film with a thickness greater than that of the first oxide semiconductor film is formed over the first crystal layer. Second heat treatment is performed so that crystal growth from the first crystal layer to a surface of the second oxide semiconductor film is caused, whereby a second crystal layer is formed. Further, oxygen doping treatment is performed on the second crystal layer.

To provide a method by which a semiconductor device including a thin film transistor with excellent electric characteristics and high reliability is manufactured with a small number of steps. After a channel protective layer is formed over an oxide semiconductor film containing In, Ga, and Zn, a film having n-type conductivity and a conductive film are formed, and a resist mask is formed over the conductive film. The conductive film, the film having n-type conductivity, and the oxide semiconductor film containing In, Ga, and Zn are etched using the channel protective layer and gate insulating films as etching stoppers with the resist mask, so that source and drain electrode layers, a buffer layer, and a semiconductor layer are formed.

An object is to provide a thin film transistor and a method for manufacturing the thin film transistor including an oxide semiconductor with a controlled threshold voltage, high operation speed, a relatively easy manufacturing process, and sufficient reliability. An impurity having influence on carrier concentration in the oxide semiconductor layer, such as a hydrogen atom or a compound containing a hydrogen atom such as H2O, may be eliminated. An oxide insulating layer containing a large number of defects such as dangling bonds may be formed in contact with the oxide semiconductor layer, such that the impurity diffuses into the oxide insulating layer and the impurity concentration in the oxide semiconductor layer is reduced. The oxide semiconductor layer or the oxide insulating layer in contact with the oxide semiconductor layer may be formed in a deposition chamber which is evacuated with use of a cryopump whereby the impurity concentration is reduced.

A method for producing a Ga-containing group III nitride semiconductor having reduced threading dislocation is disclosed. A buffer layer in a polycrystal, amorphous or polycrystal/amorphous mixed state, comprising AlGaN is formed on a substrate. The substrate having the buffer layer formed thereon is heat-treated at a temperature higher than a temperature at which a single crystal of a Ga-containing group III nitride semiconductor grows on the buffer layer and at a temperature that the Ga-containing group III nitride semiconductor does not grow, to reduce crystal nucleus density of the buffer layer as compared with the density before the heat treatment. After the heat treatment, the temperature of the substrate is decreased to a temperature that the Ga-containing group III nitride semiconductor grows, the temperature is maintained, and the Ga-containing group III nitride semiconductor is grown on the buffer layer.

A microelectronic assembly and method of making, which includes a first microelectronic element (including a substrate with first and second opposing surfaces, a semiconductor device, and conductive pads at the first surface which are electrically coupled to the semiconductor device) and a second microelectronic element (including a handler with first and second opposing surfaces, a second semiconductor device, and conductive pads at the handler first surface which are electrically coupled to the second semiconductor device). The first and second microelectronic elements are integrated such that the second surfaces face each other. The first microelectronic element includes conductive elements each extending from one of its conductive pads, through the substrate to the second surface. The second microelectronic element includes conductive elements each extending between the handler first and second surfaces. The conductive elements of the first microelectronics element are electrically coupled to the conductive elements of the second microelectronics element.

A semiconductor device has a protective layer formed over an active surface of a semiconductor wafer. The semiconductor die with pre-applied protective layer are moved from the semiconductor wafer and mounted on a carrier. The semiconductor die and contact pads on the carrier are encapsulated. The carrier is removed. A first insulating layer is formed over the pre-applied protective layer and contact pads. Vias are formed in the first insulating layer and pre-applied protective layer to expose interconnect sites on the semiconductor die. An interconnect structure is formed over the first insulating layer in electrical contact with the interconnect sites on the semiconductor die and contact pads. The interconnect structure has a redistribution layer formed on the first insulating layer, a second insulating layer formed on the redistribution layer, and an under bump metallization layer formed over the second dielectric in electrical contact with the redistribution layer.

A semiconductor device having favorable electric characteristics and a manufacturing method thereof are provided. A transistor includes an oxide semiconductor layer formed over an insulating layer, a source electrode layer and a drain electrode layer which overlap with part of the oxide semiconductor layer, a gate insulating layer in contact with part of the oxide semiconductor layer, and a gate electrode layer over the gate insulating layer. In the transistor, a buffer layer having n-type conductivity is formed between the source electrode layer and the oxide semiconductor layer and between the drain electrode layer and the oxide semiconductor layer. Thus, parasitic resistance is reduced, resulting in improvement of on-state characteristics of the transistor.

When forming sophisticated semiconductor-based gate electrode structures of transistors, the pre-doping of one type of gate electrode structure may be accomplished after the actual patterning of the electrode material by using an appropriate mask or fill material for covering the active regions and using a lithography mask. In this manner, a high degree of flexibility is provided with respect to selecting an appropriate patterning regime, while at the same time a uniform and superior cross-sectional shape for any type of gate electrode structure is obtained.

A highly reliable semiconductor device is manufactured by giving stable electric characteristics to a transistor in which an oxide semiconductor film is used for a channel. An oxide semiconductor film which can have a first crystal structure by heat treatment and an oxide semiconductor film which can have a second crystal structure by heat treatment are formed so as to be stacked, and then heat treatment is performed; accordingly, crystal growth occurs with the use of an oxide semiconductor film having the second crystal structure as a seed, so that an oxide semiconductor film having the first crystal structure is formed. An oxide semiconductor film formed in this manner is used for an active layer of the transistor.

A method for forming an amorphous semiconductor which contains an impurity element and has low resistivity and a method for manufacturing a semiconductor device with excellent electrical characteristics with high yield are provided. In the method for forming an amorphous semiconductor containing an impurity element, which utilizes a plasma CVD method, pulse-modulated discharge inception voltage is applied to electrodes under the pressure and electrode distance with which the minimum discharge inception voltage according to Paschen's Law can be obtained, whereby the amorphous semiconductor which contains an impurity element and has low resistivity is formed.

The present invention provides an electroconductive sheet and a touch panel which do not impair visibility in a vicinity of an electrode terminal in a sensing region. In an electroconductive sheet which has an electrode pattern constructed of a metal thin wire and an electrode terminal that is electrically connected to an end of the electrode pattern, a transmittance of the electrode pattern is 83% or more, and when the transmittance of the electrode pattern is represented by a %, a transmittance of the electrode terminal is controlled to be (a-20)% or more and (a-3)% or less.

In a semiconductor device, where, with respect to a parasitic resistor in a current mirror circuit, a compensation resistor for compensating the parasitic resistor is provided in the current mirror circuit, the current mirror circuit includes at least two thin film transistors. The thin film transistors each have an island-shaped semiconductor film having a channel formation region and source or drain regions, a gate insulating film, a gate electrode, and source or drain electrodes, and the compensation resistor compensates the parasitic resistor of any one of the gate electrode, the source electrode, and the drain electrode. In addition, each compensation resistor has a conductive layer containing the same material as the gate electrode, the source or drain electrodes, or the source or drain regions.

Provided is a liquid crystal display including, on an insulation substrate having a polygonal display area and a peripheral area surrounding the display area a first signal line, a second signal line crossing the first signal line, a plurality of switching elements connected to the first signal line and the second signal line and disposed in the display area, a plurality of pixel electrodes each connected to the switching element and disposed in the display area, and a shielding conductor disposed in the peripheral area and extending along at least one side of the polygonal display area.

In a semiconductor device, a first interlayer insulating layer made of an inorganic material and formed on inverse stagger type TFTs, a second interlayer insulating layer made of an organic material and formed on the first interlayer insulating layer, and a pixel electrode formed in contact with the second interlayer insulating layer are disposed on a substrate, and an input terminal portion that is electrically connected to a wiring of another substrate is provided on an end portion of the substrate. The input terminal portion includes a first layer made of the same material as that of the gate electrode and a second layer made of the same material as that of the pixel electrode. With this structure, the number of photomasks used in the photolithography method can be reduced to 5.

The liquid crystal display device includes an island-shaped first semiconductor film 102 which is formed over a base insulating film 101 and in which a source 102d, a channel forming region 102a, and a drain 102b are formed; a first electrode 102c which is formed of a material same as the first semiconductor film 102 to be the source 102d or the drain 102b and formed over the base insulating film 101; a second electrode 108 which is formed over the first electrode 102c and includes a first opening pattern 112; and a liquid crystal 110 which is provided over the second electrode 108.

The liquid crystal display device includes an island-shaped first semiconductor film 102 which is formed over a base insulating film 101 and in which a source 102d, a channel forming region 102a, and a drain 102b are formed; a first electrode 102c which is formed of a material same as the first semiconductor film 102 to be the source 102d or the drain 102b and formed over the base insulating film 101; a second electrode 108 which is formed over the first electrode 102c and includes a first opening pattern 112; and a liquid crystal 110 which is provided over the second electrode 108.

Constant-temperature equipment wherein mechanical and electrical structures are eliminated from the inside of a temperature-controlled chamber (15) by using a non-contact magnetic arrangement as a drive transmission for a sample table (5) and a sample table drive mechanism (6), thus reducing failure and enhancing maintainability. In addition, a conveyance mechanism (11) is provided with a pass box adjacent which sliding shielding plates (9) are stacked vertically, and the shielding plates (9) are linked with the conveyance mechanism (11) by an engaging mechanism provided in the conveyance mechanism (11) to allow the plates to be opened and closed by a travel mechanism (12), thus simplifying the structure and minimizing change in atmosphere during conveying. The sample table drive mechanism (6) and the conveyance mechanism (11) can be attached removably to the temperature-controlled chamber (15) to permit sterilization at high temperature.

Provided is constant-temperature equipment wherein maintenance is facilitated with the least failure, and highly reliable culturing and testing can be carried out. Mechanical and electrical structures are eliminated from the inside of a temperature-controlled chamber (15) by using a non-contact magnetic arrangement as a drive transmission for a sample table (5) and a sample table drive (6), thus reducing failure and enhancing maintainability. In addition, a conveyor (11) is provided with a pass box to minimize change in atmosphere during conveying. The sample table drive (6) and the conveyor (11) can be attached removably to the temperature-controlled chamber (15) to permit sterilization at high temperature.

Methods of washing adherent cells, capable of effectively suppressing cell death due to proteolytic enzyme treatment for detaching the adherent cell from a culture vessel and subsequent cell treatment; cell-washing solutions used for the washing method; methods of producing cell suspensions for transplantation using the cell-washing solution; and kits comprising the cell-washing solution. Trehalose or its derivative or a salt thereof is added to physiological aqueous solutions to prepare cell-washing solutions containing trehalose or its derivative or a salt thereof as an active ingredient. The cell-washing solutions can be used to wash adherent cells before detaching the adherent cells from a culture vessel by proteolytic enzyme treatment to suppress cell death due to the proteolytic enzyme treatment. The concentration of trehalose applied to the cell-washing solution may be a concentration capable of suppressing the cell death due to the proteolytic enzyme treatment, such as 0.1 to 20 (w/v) %.

The invention provides an improved design for the construction of extensible nucleic acid-based, ligand-controlled regulatory systems, and the nucleic acid regulatory systems resulting therefrom. The invention contemplates improving the design of the switches (ligand-controlled regulatory systems) through the design of an information transmission domain (ITD). The improved ITD eliminates free-floating ends of the switching and the competing strands, and localizes competitive hybridization events to a contiguous strand of competing and switching strands in a strand-displacement mechanism-based switch, thereby improving the kinetics of strand-displacement. The improved regulatory systems have many uses in various biological systems, including gene expression control or ligand-concentration sensing.

The invention is directed to a single-step method for rapidly and efficiently preparing protein-polymer conjugates, including an insulin-polymer conjugate. According to the method of the present invention, a protein and hydrophilic polymer are contacted in the presence of at least one organic solvent and at least one metal chelator, under conditions that promote the formation of a conjugate of the protein and polymer. Thus, the invention is directed to the site-specific modification of selected proteins, such as insulin, with poly(ethylene glycol) at residue PheB1. The invention also provides a pharmaceutical formulation for encapsulating the conjugate in a biodegradable polymer.

Isolated polynucleotides and polypeptides and recombinant DNA constructs particularly useful for altering agronomic characteristics of plants under nitrogen limiting conditions, compositions (such as plants or seeds) comprising these recombinant DNA constructs, and methods utilizing these recombinant DNA constructs. The recombinant DNA construct comprises a polynucleotide operably linked to a promoter functional in a plant, wherein said polynucleotide encodes an LNT1 polypeptide.

This invention provides recombinant DNA constructs and methods for manipulating expression of a target gene that is regulated by a small RNA, by interfering with the binding of the small RNA to its target gene. More specifically, this invention discloses recombinant DNA constructs encoding cleavage blockers, 5-modified cleavage blockers, and translational inhibitors useful for modulating expression of a target gene and methods for their use. Further disclosed are miRNA targets useful for designing recombinant DNA constructs including miRNA-unresponsive transgenes, miRNA decoys, cleavage blockers, 5-modified cleavage blockers, and translational inhibitors, as well as methods for their use, and transgenic eukaryotic cells and organisms containing such constructs.

The invention relates to genes coding for TCP family transcription factors and having a biological role in the development of axillary buds and branch growth. Furthermore, the invention relates to the promoters of the transcription of said genes, to the genetic constructs containing same and to the uses thereof, including the use of agents that modulate the expression of these genes in order to modify plant architecture.

Disclosed are process for contacting a protein containing material with one or more wet-mill streams. The protein content of the protein containing material is increased.

[Problem to be Solved] The importance of sugar chains having α2,3- or α2,6-linked sialic acid at their non-reducing ends is known. Industrial production has been demanded for these sugar chain compounds. Particularly, the production of glycoprotein drugs or the like inevitably requires producing in quantity sugar chains having homogeneous structures by controlling the linking pattern (α2,6-linkage or α2,3-linkage) of sialic acid. Particularly, a triantennary or tetraantennary N-type complex sugar chain having sialic acid at each of all non-reducing ends is generally considered difficult to chemically synthesize. There has been no report disclosing that such a sugar chain was chemically synthesized. Furthermore, these sugar chains are also difficult to efficiently prepare enzymatically.[Solution]The present inventors have newly found the activity of sialyltransferase of degrading sialic acid on a reaction product in the presence of CMP and also found that formed CMP can be degraded enzymatically to thereby efficiently produce a sialic acid-containing sugar chain. The present inventors have further found that even a tetraantennary N-type sugar chain having four α2,6-linked sialic acid molecules, which has previously been difficult to synthesize, can be prepared at high yields by one-pot synthesis comprising the elongation reaction of a biantennary sugar chain used as a starting material without performing purification after each enzymatic reaction.

An embodiment of the present invention provides an apparatus, comprising at least one anti-parallel pair VVC network comprised of two parallel VVCs with one biased in the opposite polarity of the other and at least one anti-series VVC network comprised of two VVCs configured in series, one biased in the opposite polarity of the other such that the resulting AC capacitive variations produce a desired capacitance variation.

In an oscillating apparatus, a detection unit detects a frequency offset between an input signal and a reference signal. A code generation unit specifies a relationship among a code having a predetermined number of bits, the frequency offset, and a voltage to be applied to a voltage-controlled oscillator by a DAC, in accordance with a frequency offset detection state of the detection unit. The code generation unit also generates a frequency offset correction code having a predetermined number of bits in accordance with the specified relationship. The DAC applies the voltage to the voltage-controlled oscillator, in accordance with the relationship described above and the code generated by the code generation unit. The voltage controlled oscillator outputs an oscillator signal having an oscillation frequency corresponding to the voltage applied by the DAC.

Control method and apparatus for a manual spray gun may include a second manually actuated trigger disposed on the spray gun handle, with the second trigger being operational to select or change one or more coating operation parameters.

An improved grounding technique for mechanically adjustable rotary capacitors uses a directly grounded bronze sliding contact to effectively and continuously ground the rotating comb-like blades of the capacitor. RF measurements of the continuity and repeatability of the capacitance settings prove the suitability of the modified capacitors for using in pre-calibrated multi-capacitor MHz range impedance tuners.

One of mark sensors is automatically selected in accordance with specifications of a thermal sheet. A cutting position on the thermal sheet is decided on the basis of an output of the selected one mark sensor.

A print shop consolidation system including a print shop consolidation management system with an application is provided. The application is used to (1) evaluate, with a set of information, an operational capacity of a first print shop to process both a first group of print jobs and a second group of print jobs, (2) evaluate, with the set of information, an operational capacity of the second print shop to process both the first and second groups of print jobs, and (3) use the evaluations of (1) and (2) to consolidate processing of the first and second groups of print jobs at one of first and second print shops.

A data processing apparatus is monitoring the first port of itself and the second port of itself. If the data processing apparatus receives data via the second port, it conducts a specific process to the data regardless of a data format of the data so as to convert the data into the data format that can be processed regardless of a data format of the data and sends converted data to the first port.

An exemplary system for managing the deployment of a seismic data acquisition system uses a module configured to execute a plurality of task in the field by receiving one or more seismic devices. The module may include a power source that provides electrical power to the seismic devices. The module may also include a processor programmed to retrieve data stored in the seismic devices, perform diagnostics, facilitate inventory and logistics control, configure seismic devices and update data or pre-programmed instructions in the seismic device.

Provided are a backlight unit and a display device having the same. The backlight unit includes a case having an opening, at least one lamp assembly disposed on a side surface of the case and including a light source, an optical transreflective unit on the case, the optical transreflective unit transmitting a portion of first light passing through the opening and reflecting a portion of second light generated from the light source, and an optical sheet including a first diffusion unit on the optical transreflective unit.

An apparatus includes a head transducer configured to interact with a magnetic recording medium and a heater configured to thermally actuate the head transducer. A thermal sensor at or near the head transducer is configured to produce a sensor signal. Circuitry is coupled to the heater and configured to cause an oscillation in heater power. The heater power oscillation causes an oscillation in the sensor signal. A detector is coupled to the thermal sensor and configured to detect head-medium contact using the oscillating sensor signal and heater power.

A container data center includes a container, a plurality of power supplies, an electric switch system, a plurality of normally closed switches, an alarm device, and a controller. The electric switch system is received in the container. The plurality of normally closed switches are connected between the power supplies and the electric switch system. Each normally closed switch is connected with a corresponding one of the power supplies in series. The controller is connected to the normally closed switches and the alarm device, configured for receiving earthquake information containing an earthquake intensity, and configured for controlling the alarm device to activate alarms and controlling some of the normally closed switches or all the normally closed switches to open when the earthquake intensity is equal to or greater than a predetermined earthquake intensity.

A printing device includes at least one printing engine that has actuators and sensors. At least one engine controller is operatively connected to the printing engine, the engine controller uses software to control operations of the printing engine. At least one non-volatile memory is operatively connected to the engine controller. The non-volatile memory stores values used by the engine controller to control operations of the printing engine. Further, at least one adapter card is operatively connected to the non-volatile memory and to the actuators and sensors. The adapter card stores data and receives sensor feedback from the sensors. The adapter card uses the data and the sensor feedback to control the actuators by bypassing the engine controller when communicating with the actuators. The adapter card provides adapter card feedback to the non-volatile memory.

This invention concerns a method and apparatus for dispensing minute quantities of highly viscous material from a jetting needle when an expelling mechanism is activated using a nozzle plate with a jetting chamber having a top formed by a diaphragm and a bottom in fluid communication with a jetting needle. Fluid enters the chamber from an inlet channel and is jetted from the chamber by deforming the diaphragm to block the channel and expel a drop of fluid from the needle. A diaphragm driven metering chamber and/or reservoir chamber can optionally be used provide fluid to the jetting chamber.

Disclosed are methods of lithography using a tip array having a plurality of pens attached to a backing layer, where the tips can comprise a metal, metalloid, and/or semi-conducting material, and the backing layer can comprise an elastomeric polymer. The tip array can be used to perform a lithography process in which the tips are coated with an ink (e.g., a patterning composition) that is deposited onto a substrate upon contact of the tip with the substrate surface. The tips can be easily leveled onto a substrate and the leveling can be monitored optically by a change in light reflection of the backing layer and/or near the vicinity of the tips upon contact of the tip to the substrate surface.

An object is to prevent an operation defect and to reduce an influence of fluctuation in threshold voltage of a field-effect transistor. A field-effect transistor, a switch, and a capacitor are provided. The field-effect transistor includes a first gate and a second gate which overlap with each other with a channel formation region therebetween, and the threshold voltage of the field-effect transistor varies depending on the potential of the second gate. The switch has a function of determining whether electrical connection between one of a source and a drain of the field-effect transistor and the second gate of the field-effect transistor is established. The capacitor has a function of holding a voltage between the second gate of the field-effect transistor and the other of the source and the drain of the field-effect transistor.

Alloys and methods for preparing the same are provided. The alloys are represented by the general formula of (ZraAlbCucNid)100-e-fYeMf, wherein a, b, c, and d are atomic fractions, in which: 0.472≦a≦0.568; 0.09≦b≦0.11; 0.27≦c≦0.33; 0.072≦d≦0.088; the sum of a, b, c, and d equals 1; e and f are atomic numbers of elements Y and M respectively, in which 0≦e≦5 and 0.01≦f≦5; and M is selected from the group consisting of Nb, Ta, Sc, and combinations thereof.

Provided are a bake hardening steel having a crystalline grain size of ASTM No. 9 or more and a method for preparing the bake hardening steel by controlling the winding, rolling and cooling conditions. The bake hardening steel includes: C:0.0016˜0.0025%, Si:0.02% or less, P:0.01˜0.05%, S:0.01% or less, sol.Al:0.08˜0.12%, N:0.0025% or less, Ti:0.003% or less, Nb:0.003˜0.011%, Mo:0.01˜0.1%, B:0.0005˜0.0015% or less, balance Fe and other inevitable impurities, wherein % is weight %, and Mn and P satisfy the relation of −30(° C.)≧803P−24.4Mn−58.

Magnesium alloys containing: Y: 2.0-6.0% by weight Nd: 0-4.0% by weight Gd: 0-5.5% by weight Dy: 0-5.5% by weight Er: 0-5.5% by weight Zr: 0.05-1.0% by weight Zn+Mn: