Disclosed is a process for producing 2-chloro-1,3,3,3-tetrafluoropropene (1224), including a first step of separating 2,3-dichloro-1,1,1,3-tetrafluoropropane (234da) into erythro form and threo form, and a second step of bringing the separated erythro form or threo form in contact with a base to obtain 2-chloro-1,3,3,3-tetrafluoropropene (1224). The first step is a step of separating 234da by distillation to achieve a separation into a fraction containing mainly erythro form and a fraction containing mainly threo form. In the second step, 1224 cis form is obtained from the erythro form, and 1224 trans form is obtained from the threo form. By this process, it is possible to selectively and efficiently produce cis form or trans form of 2-chloro-1,3,3,3-tetrafluoropropene (1224).

This invention provides a process for producing 2,3,3,3-tetrafluoropropene, the process comprising: (1) a first reaction step of reacting hydrogen fluoride with at least one chlorine-containing compound selected from the group consisting of a chloropropane represented by Formula (1): CClX2CHClCH2Cl, wherein each X is the same or different and is CI or F, a chloropropene represented by Formula (2): CClY2CCl═CH2, wherein each Y is the same or different and is CI or F, and a chloropropene represented by Formula (3): CZ2═CClCH2Cl, wherein each Z is the same or different and is CI or F in a gas phase in the absence of a catalyst while heating; and (2) a second reaction step of reacting hydrogen fluoride with a reaction product obtained in the first reaction step in a gas phase in the presence of a fluorination catalyst while heating. According to the process of this invention, 2,3,3,3-tetrafluoropropene (HFO-1234yf) can be obtained with high selectivity, and catalyst deterioration can be suppressed.

Process for producing silica-comprising dispersions comprising a polyetherol or a polyether amine, which comprises the steps of (i) admixing an aqueous silica sol (K) having an average particle diameter of from 1 to 150 nm and a silica content, calculated as SiO2, of from 1 to 60% by weight and a pH of from 1 to 6 with at least one polyetherol (b1) and/or polyether amine (b2) based on ethylene oxide and/or propylene oxide and having an average OH or amine functionality of from 2 to 6 and a number average molecular weight of from 62 to 6000 g/mol,(ii) distilling off at least part of the water,(iii) admixing the dispersion with at least one compound (S) having at least one at least monoalkoxylated silyl group and at least one alkyl, cycloalkyl or aryl substituent, where this substituent may have groups which are reactive toward an alcohol, an amine or an isocyanate in an amount of from 0.1 to 20 μmol of (S) per m2 of surface area of (K), where steps (i) and (iii) can be carried out simultaneously or in succession in any order, (iv) optionally adjusting the pH of the silica-comprising dispersions obtained to a value of from 7 to 12 by adding a basic compound, where step (iv) can also be carried out between steps (ii) and (iii).

Emulsions, and processes for making the emulsions, useful for imparting water resistance to gypsum products are disclosed. Process for making the emulsion and gypsum products made from the emulsion are also disclosed. The emulsions of the invention include at least one paraffin wax and a hydrophilic metallic salt. The emulsions of the invention may further include a saponifiable wax substitute for montan wax. The emulsions of the invention may further include a biocide.

The invention relates to process for the treatment of a hydrophobic surface by a liquid film comprising an aqueous phase comprising the coating of said surface by the liquid whose aqueous phase comprises an effective amount of an agent of modification of the properties of surface and an active agent.

A method for producing polymer particles includes a preparation step for preparing a first oily liquid containing an oily olefin monomer, a radical polymerization initiator, and an iodine molecule, a synthesis step for obtaining a second oily liquid containing at least an iodine compound produced by a reaction between a radical generated by cleavage of the radical polymerization initiator and the iodine molecule in the first oily liquid, a suspension step for obtaining an oil droplet of the second oily liquid by suspending the second oily liquid in water, and a polymerization step for polymerizing the oily olefin monomer in the oil droplet.

The present invention relates to a method for producing particles of a compound of interest. In a method according to the invention a solution is provided of the compound of interest in a solvent. This solution is thickened or gelled and particles are formed. The invention further relates to a particle that is obtainable by the invention.

Emulsions, and processes for making the emulsions, useful for imparting water resistance to gypsum products are disclosed. Process for making the emulsion and gypsum products made from the emulsion are also disclosed. The emulsions of the invention include at least one paraffin wax and a hydrophilic metallic salt. The emulsions of the invention may further include a saponifiable wax substitute for montan wax. The emulsions of the invention may further include a biocide.

An object of the present invention is to provide a method for producing a conductive material that allows a low electric resistance to be generated, and that is obtained by using an inexpensive and stable conductive material composition containing no adhesive. The conductive material can be provided by a producing method that includes the step of sintering a first conductive material composition that contains silver particles having an average particle diameter (median diameter) of 0.1 μm to 15 μm, and a metal oxide, so as to obtain a conductive material. The conductive material can be provided also by a method that includes the step of sintering a second conductive material composition that contains silver particles having an average particle diameter (median diameter) of 0.1 μm to 15 μm in an atmosphere of oxygen or ozone, or ambient atmosphere, at a temperature in a range of 150° C. to 320° C., so as to obtain a conductive material.

A manufacturing method of a glass substrate for a magnetic disk is provided whereby nano pits and/or nano scratches cannot be easily produced in polishing a principal face of a glass substrate using a slurry containing zirconium oxide as an abrasive. The manufacturing method of a glass substrate for a magnetic disk includes, for instance, a polishing step of polishing a principal face of a glass substrate using a slurry containing, as an abrasive, zirconium oxide abrasive grains having monoclinic crystalline structures (M) and tetragonal crystalline structures (T).

A method for producing an emulsion is provided. At least a fluid to be processed that forms continuous phase and a fluid to be processed that forms dispersed phase are mixed in a thin film fluid formed between processing surfaces arranged to be opposite to each other so as to be able to approach to and separate from each other, at least one of which rotates relative to the other, whereby the emulsion having variation coefficient of 0.3 to 30% in a particle size distribution is obtained.

Process for preparing a dispersion comprising silicon dioxide particles and cationizing agents, by dispersing 50 to 75 parts by weight of water, 25 to 50 parts by weight of silicon dioxide particles having a BET surface area of 30 to 500 m2/g and 100 to 300 μg of cationizing agent per square meter of the BET surface area of the silicon dioxide particles, wherein the cationizing agent is obtainable by reacting at least one haloalkyl-functional alkoxysilane, hydrolysis products, condensation products and/or mixtures thereof with at least one aminoalcohol and water; and optionally removing the resulting hydrolysis alcohol from the reaction mixture. Also the process for preparing the dispersion, wherein the cationizing agent comprises one or more quaternary, aminoalcohol-functional, organosilicon compounds of formula III and/or condensation products thereof, wherein Ru and Rv are independently C2-4 alkyl group, m is 2-5 and n is 2-5.

A data processing apparatus includes multiple processing means that are connected in a ring shape via corresponding communication means respectively. Each communication means includes a reception means for receiving data from a previous communication means, and a transmission means for transmitting data to a next communication means. Connection information is assigned to each of the reception means and the transmission means. The communication means, when receiving a packet that has same connection information as one assigned to its reception means, causes the corresponding processing means to perform data processing on the packet, sets the connection information assigned to its transmission means to the packet, and transmits the packet to the next communication means, and when receiving a packet that has connection information that is not same as one assigned to its reception means, transmits the packet to the next communication means without changing the connection information of the packet.

A statue management section of a control section is provided with a corresponding real number storage section that stores a real number converted from a logical number by a configuration number converting section. When the corresponding real number storage section has stored configuration information with a real number of the next transition state, the state management section directly supplies the real number to the configuration information storage section in the next or later processing cycle.

A method and circuit arrangement utilize a low latency variable transfer network between the register files of multiple processing cores in a multi-core processor chip to support fine grained parallelism of virtual threads across multiple hardware threads. The communication of a variable over the variable transfer network may be initiated by a move from a local register in a register file of a source processing core to a variable register that is allocated to a destination hardware thread in a destination processing core, so that the destination hardware thread can then move the variable from the variable register to a local register in the destination processing core.

The disclosure relates to the implementation of multi-tasking on a digital signal processor. Blocking functions are arranged such that they do not make use of a processor's hardware stack. Respective function calls are replaced with a piece of inline assembly code, which instead performs a branch to the correct routine for carrying out said function. If a blocking condition of the blocking function is encountered, a task switch can be done to resume another task. Whilst the hardware stack is not used when a task switch might have to occur, mixed-up contents of the hardware stack among function calls performed by different tasks are avoided.

A technique for activating processor cores within a computer system is disclosed. Initially, a value representing a number of processor cores to be enabled within the computer system is received. The computer system includes multiple processors, and each of the processors includes multiple processor cores. Next, a scale variable value representing a specific type of tasks to be optimized during an execution of the tasks within the computer system is received. From a pool of available processor cores within the computer system, a subset of processor cores can be selected for activation. The subset of processor cores is activated in order to achieve system optimization during an execution of the tasks.

The disclosure provides a method for passing a parameter between processors. The method comprises the following steps: in a source program of a slave processor, directly introducing a static configuration parameter to be passed; obtaining a relative address of the static configuration parameter when converting the source program of the slave processor into a target program of the slave processor; and configuring directly, by a master processor, a parameter value of the static configuration parameter in the target program of the slave processor according to the obtained relative address of the static configuration parameter. The disclosure also provides a system for passing a parameter between processors. The system has no need to use external hardware such as a dual-port Random Access Memory (RAM) and a register, thus, the requirement of parameter transmission on the external hardware is reduced, and further the area and static power consumption of a chip are reduced. The disclosure reduces the cycle delay of the slave processor in accessing the dual-port RAM and the register, thereby effectively reducing the dynamic power consumption of the chip, improving the processing capability of the slave processor and enhancing the effective performance of the slave processor.

A processor determines whether a first program is under execution when a second program is executed, and changes a setting of a memory management unit based on access prohibition information so that a fault occurs when the second program makes an access to a memory when the first program is under execution. Then, the processor determines whether an access from the second program to a memory area used by the first program is permitted based on memory restriction information when the fault occurs while the first program and the second program are under execution, and changes the setting of the memory management unit so that the fault does not occur when the access to the memory area is permitted.

Augmented processor hardware contains a microcode interpreter. When encrypted microcode is included in a message from a service, the microcode may be passed to the microcode interpreter. Based on decryption and execution of the microcode taking place at the processor hardware, extended functionality may be realized.

A multi-threaded in-order superscalar processor 2 includes an issue stage 12 including issue circuitry 22, 24 for selecting instructions to be issued to execution units 14, 16 in dependence upon a currently selected issue policy. A plurality of different issue policies are provided by associated different policy circuitry 28, 30, 32 and a selection between which of these instances of the policy circuitry 28, 30, 32 is active is made by policy selecting circuitry 34 in dependence upon detected dynamic behavior of the processor 2.

A microprocessor having performs an architectural instruction that instructs it to perform an operation on first and second source operands to generate a result and to write the result to a destination register only if its architectural condition flags satisfy a condition specified in the architectural instruction. A hardware instruction translator translates the instruction into first and second microinstructions. To execute the first microinstruction, an execution pipeline performs the operation on the source operands to generate the result. To execute the second microinstruction, it writes the destination register with the result generated by the first microinstruction if the architectural condition flags satisfy the condition, and writes the destination register with the current value of the destination register if the architectural condition flags do not satisfy the condition.

A computing method includes accepting a definition of a computing task, which includes multiple Processing Elements (PEs) having execution dependencies. The computing task is compiled for concurrent execution on a multiprocessor device, by arranging the PEs in a series of two or more invocations of the multiprocessor device, including assigning the PEs to the invocations depending on the execution dependencies. The multiprocessor device is invoked to run software code that executes the series of the invocations, so as to produce a result of the computing task.

In a multiprocessor system, in general, a processor assigned with a larger amount of tasks is apt to perform a larger amount of communication with other processors assigned with tasks, than a processor assigned with a smaller amount of tasks. Thus in order for each processor to be able to perform the routing process efficiently, tasks are assigned such that, when there are a first processor and a second processor, the number of processors each assigned with one or more tasks and directly connected with the second processor being smaller than the number of processors each assigned with one or more tasks and directly connected with the first processor, the amount of tasks assigned to the first processor is equal to or larger than the amount of tasks assigned to the second processor.

A method for activating processor cores within a computer system is disclosed. Initially, a value representing a number of processor cores to be enabled within the computer system is received. The computer system includes multiple processors, and each of the processors includes multiple processor cores. Next, a scale variable value representing a specific type of tasks to be optimized during an execution of the tasks within the computer system is received. From a pool of available processor cores within the computer system, a subset of processor cores can be selected for activation. The subset of processor cores is activated in order to achieve system optimization during an execution of the tasks.

A High Performance Computing (HPC) node comprises a motherboard, a switch comprising eight or more ports integrated on the motherboard, and at least two processors operable to execute an HPC job, with each processor communicably coupled to the integrated switch and integrated on the motherboard.

A data processing device includes processing circuitry 20 for executing a first memory access instruction to a first address of a memory device 40 and a second memory access instruction to a second address of the memory device 40, the first address being different from the second address. The data processing device also includes prefetching circuitry 30 for prefetching data from the memory device 40 based on a stride length 70 and instruction analysis circuitry 50 for determining a difference between the first address and the second address. Stride refining circuitry 60 is also provided to refine the stride length based on factors of the stride length and factors of the difference calculated by the instruction analysis circuitry 50.

A multiprocessor system includes a first microprocessor and a second microprocessor. A first signaling pathway is configured to send message transmission coordination signals from the first microprocessor to the second microprocessor. The first signaling pathway may be coupled to at least two flag registers associated with the second microprocessor. A second signaling pathway is configured to send message transmission coordination signals from the second microprocessor to the first microprocessor. The second signaling pathway may be coupled to at least two flag registers associated with the first microprocessor. The first signaling pathway is independent of the second signaling pathway.

Efficient data processing apparatus and methods include hardware components which are pre-programmed by software. Each hardware component triggers the other to complete its tasks. After the final pre-programmed hardware task is complete, the hardware component issues a software interrupt.

In accordance with embodiments, there are provided mechanisms and methods for controlling a process using a process map. These mechanisms and methods for controlling a process using a process map can enable process operations to execute in order without necessarily having knowledge of one another. The ability to provide the process map can avoid a requirement that the operations themselves be programmed to follow a particular sequence, as can further improve the ease by which the sequence of operations may be changed.

A data processing system arranged for receiving over a network, according to a data transfer protocol, data directed to any of a plurality of destination identities, the data processing system comprising: data storage for storing data received over the network; and a first processing arrangement for performing processing in accordance with the data transfer protocol on received data in the data storage, for making the received data available to respective destination identities; and a response former arranged for: receiving a message requesting a response indicating the availability of received data to each of a group of destination identities; and forming such a response; wherein the system is arranged to, in dependence on receiving the said message.

A method includes, in a processor, loading/moving a first portion of bits of a source into a first portion of a destination register and duplicate that first portion of bits in a subsequent portion of the destination register.

A processor receives an instruction operation (OP) code from a verification system. The instruction OP code includes instruction bits and forced event bits. The processor identifies a forced event based upon the forced event bits, which is unrelated to an instruction that corresponds to the instruction bits. In turn, the processor executes the forced event.

In an example embodiment, there is described herein an apparatus comprising an interface for communicating with a plurality of digital signal processors and logic operable to send and receive data via the interface. The logic is configured to determine a first set of digital signal processors to be maintained in a ready state, a second set of digital signal processors to be maintained in a first energy saving state, and a third set of digital signal processors to be maintained in a second energy saving state.

Systems and methods for static code scheduling are disclosed. A method can include receiving an intermediate representation of source code, building a directed acyclic graph (DAG) for the intermediate representation, and creating chains of dependent instructions from the DAG for cluster formation. The chains are merged into clusters and each node in the DAG is marked with an identifier of a cluster it is part of to generate a marked instruction DAG. Instruction DAG scheduling is then performed using information about the clusters to generate an ordered intermediate representation of the source code.

A computer-implemented method is provided for evaluating team performance in a product development environment. The method includes receiving a plurality of points of effort made by a team over a plurality of days in a time period, computing a slope associated with a line of best fit through the plurality of points of effort over the plurality of days, computing a deviation of the slope from an ideal slope corresponding to a desired performance rate for the team, and generating a display illustrating at least one of the slope, the ideal slope or the deviation.

A method of applying formal verification methodologies to event processing applications is provided herein. The method includes the following stages: representing an event processing application as an event processing network, being a graph with event processing agents as nodes; generating a finite state machine based on the event processing network, wherein the finite state machine is an over-approximation of the event processing application; expressing stateful rules and policies that are associated with the event processing application using temporal logic, to yield a temporal representation of the event processing application; combining the temporal representation and the finite state machine into a model; generating a statement associated with a user-selected verification-related property of the event processing application, wherein the statement is generated using the temporal representation; and applying the statement to the model, to yield an indication for: (i) a correctness of the statement or (ii) a counter example, respectively.

Graphical programming or modeling environments in which a coding standard can be applied to graphical programs or models are disclosed. The present invention provides mechanisms for applying the coding standard to graphical programs/models in the graphical programming/modeling environments. The mechanisms may detect violations of the coding standard in the graphical model and report such violations to the users. The mechanisms may automatically correct the graphical model to remove the violations from the graphical model. The mechanisms may also automatically avoid the violations in the simulation and/or code generation of the graphical model.

An information processing system, computer readable storage medium, and method for automatically generating human readable and meaningful documentation for one or more source code files. A processor of the information processing system receives one or more source code files containing source code artifacts (SCA) and infers semantics therefrom based on predefined rules. The processor, based on the inferred semantics, extracts documentation from another source code file. The extracted documentation and the inferred semantics are used to generate new human readable and meaningful documentation for the SCA, such new documentation being previously missing from the SCA. The generated new documentation is included with the SCA in one or more source code files.

A method is provided for providing consistent logical code across specific programming languages. The method incorporates preprocessor macros in a source computer program code to generate a program control flow. The preprocessor macros can be used to describe program control flow in the source programming language for execution in the source computer program code. The preprocessor macros can also be used to generate control flow objects representing the control flow, which converts the source computer program code into a general language representation. The general language representation when executed is used to output computer programming code in specific programming languages representing the same logical code as that of the source computer program code.

The present invention relates to a method for compiling code for a multi-core processor, comprising: detecting and optimizing a loop, partitioning the loop into partitions executable and mappable on physical hardware with optimal instruction level parallelism, optimizing the loop iterations and/or loop counter for ideal mapping on hardware, chaining the loop partitions generating a list representing the execution sequence of the partitions.

In one embodiment, a machine-implemented method programs a heterogeneous multi-processor computer system to run a plurality of program modules, wherein each program module is to be run on one of the processors The system includes a plurality of processors of two or more different processor types. According to the recited method, machine-implemented offline processing is performed using a plurality of SIET tools of a scheduling information extracting toolkit (SIET) and a plurality of SBT tools of a schedule building toolkit (SBT). A program module applicability analyzer (PMAA) determines whether a first processor of a first processor type is capable of running a first program module without compiling the first program module. Machine-implemented online processing is performed using realtime data to test the scheduling software and the selected schedule solution.

In one embodiment of the invention, a method is disclosed for modifying a pre-existing application program for multi-processing and/or distributed parallel processing. The method includes searching an application program for a computational loop; analyzing the computational loop to determine independence of the computational transactions of the computational loop; and replacing the computational loop with master code and slave code to provide master-slave execution of the computational loop in response to analyzing the computational loop to determine independence of the computational transactions of the computational loop. Multiple instances of the modified application program are executed to provide multi-processing and/or distributed parallel processing.

In one embodiment, an optimization hint may be included in a business process flow. An executable process may be generated from the business process flow where the optimization hint is included in the executable process. While executing the executable process, the runtime engine encounters an optimization hint and determines an optimization to perform. The optimization hint may be related to an aspect of a business process being orchestrated by the business process flow. The optimization is then performed while executing the executable process. For example, the runtime engine may start pre-processing the branch while the condition is being evaluated. If the condition evaluates such that the pre-processed branch should be executed, then the runtime engine has already started processing of that branch. The processing is thus optimized in that the runtime engine is not sitting idle while waiting for the condition to be evaluated.

This invention relates to a method, computer readable medium, and apparatus for identifying one or more problematic loops in an application. This invention provides a Directed Acyclic Graph or DAG representation of structure of one or more loops in the application by performing a static and a dynamic analysis of the application source code and depicts the loop information as LoopID, loop weight, total loop iteration, average loop iteration, total loop iteration time, average loop iteration time and embedded vector size. This aids a programmer to concentrate on problematic loops in the application and analyze them further for potential parallelism.

A binary library overload instruction is received at an embedded computing device that executes a write-protected firmware build. The binary library overload instruction specifies a write-protected binary library of the write-protected firmware build to be overloaded by execution of an alternative binary library instead of the write-protected binary library of the write-protected firmware build. The alternative binary library is configured within a random access memory (RAM) storage area to execute instead of the write-protected binary library as specified in the received binary library overload instruction. The write-protected firmware build is executed using the alternative binary library instead of the write-protected binary library specified in the binary library overload instruction.

Embodiments provide various techniques for dynamic adjustment of a number of threads for execution in any domain based on domain utilizations. In a multiprocessor system, the utilization for each domain is monitored. If a utilization of any of these domains changes, then the number of threads for each of the domains determined for execution may also be adjusted to adapt to the change.

Methods and systems to identify and reproduce concurrency bugs in multi-threaded programs are disclosed. An example method disclosed herein includes defining a data type. The data type includes a first predicate associated with a first thread of a multi-threaded program that is associated with a first condition, a second predicate that is associated with a second thread of the multi-threaded program, the second predicate being associated with a second condition, and an expression that defines a relationship between the first predicate and the second predicate. The relationship, when satisfied, causes the concurrency bug to be detected. A concurrency bug detector conforming to the data type is used to detect the concurrency bug in the multi-threaded program.

An improved method for program building uses predefined source files and predefined build scripts comprising a sequence of build commands; wherein each build command comprises an origin command line interpretable by an operating system and addressed to at least one compiling tool.

A microcapsule comprising A) a core containing a hydrophobic liquid or wax, B) a polymeric shell comprising a) a polymer formed from a monomer mixture containing: i) 1 to 95% by weight of a hydrophobic mono functional ethylenically unsaturated monomer, ii) 5 to 99% by weight of a polyfunctional ethylenically unsaturated monomer, and iii) 0 to 60% by weight of other mono functional monomer, and b) a further hydrophobic polymer which is insoluble in the hydrophobic liquid or wax. The invention includes a process for the manufacture of particles and the use of particles in articles, such as fabrics, and coating compositions, especially for textiles.