Systems, methods and computer program products may provide managing utilization of one or more physical processors in a shared processor pool. A method of managing utilization of one or more physical processors in a shared processor pool may include determining a current amount of utilization of the one or more physical processors and generating an instruction message. The instruction message may be at least partially determined by the current amount of utilization. The method may further include sending the instruction message to a guest operating system, the guest operating system having a number of enabled virtual processors.

Techniques for adaptive thread scheduling on a plurality of cores for reducing system energy are described. In one embodiment, a thread scheduler receives leakage current information associated with the plurality of cores. The leakage current information is employed to schedule a thread on one of the plurality of cores to reduce system energy usage. On chip calibration of the sensors is also described.

Disclosed are a reconfigurable processor and processing method, a reconfiguration control apparatus and method, and a thread modeler and modeling method. A memory area of a reconfigurable processor may be divided into a plurality of areas, and a context enabling a thread process may be stored in respective divided areas, in advance. Accordingly, when a context switching is performed from one thread to another thread, the other thread may be executed by using information stored in an area corresponding to the other thread.

The disclosure relates to the implementation of multi-tasking on a digital signal processor. Blocking functions are arranged such that they do not make use of a processor's hardware stack. Respective function calls are replaced with a piece of inline assembly code, which instead performs a branch to the correct routine for carrying out said function. If a blocking condition of the blocking function is encountered, a task switch can be done to resume another task. Whilst the hardware stack is not used when a task switch might have to occur, mixed-up contents of the hardware stack among function calls performed by different tasks are avoided.

A technique for activating processor cores within a computer system is disclosed. Initially, a value representing a number of processor cores to be enabled within the computer system is received. The computer system includes multiple processors, and each of the processors includes multiple processor cores. Next, a scale variable value representing a specific type of tasks to be optimized during an execution of the tasks within the computer system is received. From a pool of available processor cores within the computer system, a subset of processor cores can be selected for activation. The subset of processor cores is activated in order to achieve system optimization during an execution of the tasks.

The disclosure provides a method for passing a parameter between processors. The method comprises the following steps: in a source program of a slave processor, directly introducing a static configuration parameter to be passed; obtaining a relative address of the static configuration parameter when converting the source program of the slave processor into a target program of the slave processor; and configuring directly, by a master processor, a parameter value of the static configuration parameter in the target program of the slave processor according to the obtained relative address of the static configuration parameter. The disclosure also provides a system for passing a parameter between processors. The system has no need to use external hardware such as a dual-port Random Access Memory (RAM) and a register, thus, the requirement of parameter transmission on the external hardware is reduced, and further the area and static power consumption of a chip are reduced. The disclosure reduces the cycle delay of the slave processor in accessing the dual-port RAM and the register, thereby effectively reducing the dynamic power consumption of the chip, improving the processing capability of the slave processor and enhancing the effective performance of the slave processor.

Augmented processor hardware contains a microcode interpreter. When encrypted microcode is included in a message from a service, the microcode may be passed to the microcode interpreter. Based on decryption and execution of the microcode taking place at the processor hardware, extended functionality may be realized.

A multi-threaded in-order superscalar processor 2 includes an issue stage 12 including issue circuitry 22, 24 for selecting instructions to be issued to execution units 14, 16 in dependence upon a currently selected issue policy. A plurality of different issue policies are provided by associated different policy circuitry 28, 30, 32 and a selection between which of these instances of the policy circuitry 28, 30, 32 is active is made by policy selecting circuitry 34 in dependence upon detected dynamic behavior of the processor 2.

A microprocessor having performs an architectural instruction that instructs it to perform an operation on first and second source operands to generate a result and to write the result to a destination register only if its architectural condition flags satisfy a condition specified in the architectural instruction. A hardware instruction translator translates the instruction into first and second microinstructions. To execute the first microinstruction, an execution pipeline performs the operation on the source operands to generate the result. To execute the second microinstruction, it writes the destination register with the result generated by the first microinstruction if the architectural condition flags satisfy the condition, and writes the destination register with the current value of the destination register if the architectural condition flags do not satisfy the condition.

In a multiprocessor system, in general, a processor assigned with a larger amount of tasks is apt to perform a larger amount of communication with other processors assigned with tasks, than a processor assigned with a smaller amount of tasks. Thus in order for each processor to be able to perform the routing process efficiently, tasks are assigned such that, when there are a first processor and a second processor, the number of processors each assigned with one or more tasks and directly connected with the second processor being smaller than the number of processors each assigned with one or more tasks and directly connected with the first processor, the amount of tasks assigned to the first processor is equal to or larger than the amount of tasks assigned to the second processor.

A method for activating processor cores within a computer system is disclosed. Initially, a value representing a number of processor cores to be enabled within the computer system is received. The computer system includes multiple processors, and each of the processors includes multiple processor cores. Next, a scale variable value representing a specific type of tasks to be optimized during an execution of the tasks within the computer system is received. From a pool of available processor cores within the computer system, a subset of processor cores can be selected for activation. The subset of processor cores is activated in order to achieve system optimization during an execution of the tasks.

A High Performance Computing (HPC) node comprises a motherboard, a switch comprising eight or more ports integrated on the motherboard, and at least two processors operable to execute an HPC job, with each processor communicably coupled to the integrated switch and integrated on the motherboard.

A multiprocessor system includes a first microprocessor and a second microprocessor. A first signaling pathway is configured to send message transmission coordination signals from the first microprocessor to the second microprocessor. The first signaling pathway may be coupled to at least two flag registers associated with the second microprocessor. A second signaling pathway is configured to send message transmission coordination signals from the second microprocessor to the first microprocessor. The second signaling pathway may be coupled to at least two flag registers associated with the first microprocessor. The first signaling pathway is independent of the second signaling pathway.

Efficient data processing apparatus and methods include hardware components which are pre-programmed by software. Each hardware component triggers the other to complete its tasks. After the final pre-programmed hardware task is complete, the hardware component issues a software interrupt.

A method includes, in a processor, loading/moving a first portion of bits of a source into a first portion of a destination register and duplicate that first portion of bits in a subsequent portion of the destination register.

A processor receives an instruction operation (OP) code from a verification system. The instruction OP code includes instruction bits and forced event bits. The processor identifies a forced event based upon the forced event bits, which is unrelated to an instruction that corresponds to the instruction bits. In turn, the processor executes the forced event.

In an example embodiment, there is described herein an apparatus comprising an interface for communicating with a plurality of digital signal processors and logic operable to send and receive data via the interface. The logic is configured to determine a first set of digital signal processors to be maintained in a ready state, a second set of digital signal processors to be maintained in a first energy saving state, and a third set of digital signal processors to be maintained in a second energy saving state.

A method is provided for providing consistent logical code across specific programming languages. The method incorporates preprocessor macros in a source computer program code to generate a program control flow. The preprocessor macros can be used to describe program control flow in the source programming language for execution in the source computer program code. The preprocessor macros can also be used to generate control flow objects representing the control flow, which converts the source computer program code into a general language representation. The general language representation when executed is used to output computer programming code in specific programming languages representing the same logical code as that of the source computer program code.

The present invention relates to a method for compiling code for a multi-core processor, comprising: detecting and optimizing a loop, partitioning the loop into partitions executable and mappable on physical hardware with optimal instruction level parallelism, optimizing the loop iterations and/or loop counter for ideal mapping on hardware, chaining the loop partitions generating a list representing the execution sequence of the partitions.

In one embodiment, a machine-implemented method programs a heterogeneous multi-processor computer system to run a plurality of program modules, wherein each program module is to be run on one of the processors The system includes a plurality of processors of two or more different processor types. According to the recited method, machine-implemented offline processing is performed using a plurality of SIET tools of a scheduling information extracting toolkit (SIET) and a plurality of SBT tools of a schedule building toolkit (SBT). A program module applicability analyzer (PMAA) determines whether a first processor of a first processor type is capable of running a first program module without compiling the first program module. Machine-implemented online processing is performed using realtime data to test the scheduling software and the selected schedule solution.

Embodiments provide various techniques for dynamic adjustment of a number of threads for execution in any domain based on domain utilizations. In a multiprocessor system, the utilization for each domain is monitored. If a utilization of any of these domains changes, then the number of threads for each of the domains determined for execution may also be adjusted to adapt to the change.

Navigation systems and associated methods for providing navigation services are provided. Information associated with a desired route for a vehicle, such as a route between a current location and a desired destination, may be determined. Additionally, contextual information associated with the vehicle may be identified. Based upon the desired route and the contextual information, a direction may be generated for presentation to one or more users, and the generated direction may be output for presentation.

A plurality of Field Programmable Gate Arrays (FPGA), high performance transceivers, and memory devices provide a verification module for timing and state debugging of electronic circuit designs. Signal value compression circuits and gigabit transceivers embedded in each FPGA increase the fanout of each FPGA. Ethernet communication ports enable remote software debugging of processor instructions.

The present invention is a solid rinse aid composition and methods of making and using the same. Applicants have surprisingly found that the crystal modifier sodium xylene sulfonate (short chain alkyl benzene or alkyl naphthalene sulfonates) at higher percentage can act as a solidification agent. The solid rinse aid composition generally includes an short chain alkyl benzene or alkyl naphthalene sulfonates solidification agent and an effective amount of a surfactant which can include a sheeting agent component, defoamer component and/or association disruption agent. The solid rinse aid composition may be phosphate-free, aminocarboxylate-free, and GRAS if desired.

Quantum annealing may include applying and gradually removing disorder terms to qubits of a quantum processor, for example superconducting flux qubits of a superconducting quantum processor. A problem Hamiltonian may be established by applying control signals to the qubits, an evolution Hamiltonian established by applying disorder terms, and annealing by gradually removing the disorder terms. Change in persistent current in the qubits may be compensated. Multipliers may mediate coupling between various qubits and a global signal line, for example by applying respective scaling factors. Two global signal lines may be arranged in an interdigitated pattern to couple to respective qubits of a communicatively coupled pair of qubits. Pairs of qubits may be communicatively isolated and used to measure a response of one another to defined signals.

The invention pertains to a memory management unit for a microprocessor system, the memory management unit being connected or connectable to at least one processor core of the microprocessor system and being connected or connectable to a physical memory of the microprocessor system. The memory management unit is adapted to selectively operate in a hypervisor mode or in a supervisor mode, the hypervisor mode and the supervisor mode having different privilege levels of access to hardware The memory management unit comprises a first register table indicating physical address information for mapping at least one logical physical address and at least one actual physical address onto each other; a second register table indicating an allowed address range of physical addresses accessible to a process running in or under supervisor mode; wherein the memory management unit is adapted to prevent write access to the second register table by a process not in hypervisor mode. The memory management unit is further adapted to allow write access to the first register table of a process running in or under supervisor mode to reconfigure the physical address information indicated in the first register table with memory mapping information relating to at least one physical address, if the at least one physical address is in the allowed address range, and to prevent write access to the first register table of the process running in or under supervisor mode if the at least one physical address is not in the allowed address range. The invention also pertains to a microprocessor system and a method for managing memory.

A cytosine analog, a method of preparation of a cytosine analog, a DNA methyltransferase 1 inhibitor, and a method for DNA methylation inhibition, is provided for the treatment of diseases associated with deviations from normal DNA methylation. The analog of cytosine may be comprised of 1, N4, 5 and 6-substituted derivatives of cytosine or 5,6-dihydrocytosine, wherein the analog can be described by the chemical formula where R1 is H, R3, R4, 2'-deoxyribosyl, R4 is alkyl or aryl, X is N or C, wherein if X in the analog of formula I is N, then R5 is no substituent and if X in the analog of formula I and/or II is C or if X in the analog of formula II is N, then R5 and R6 are independently alkyl, aryl, hydroxyalkyl, aminoalkyl, hydroxyl, carboxyl, amino group, alkoxyl, aryloxyl, aminoalkyl, aminoaryl, thio group, sulfonyl, sulfinyl or halogen.

In an embodiment, an apparatus includes a cryptographic processor within a wireless device. The cryptographic processor includes at least one cryptographic unit. The cryptographic processor also includes a nonvolatile memory to store one or more microcode instructions, wherein at least one of the one or more microcode instructions is related to a sensitive operation. The cryptographic processor also includes a controller to control execution of the one or more microcode instructions by the at least one cryptographic unit, wherein the controller is to preclude execution of the sensitive operation if the apparatus is within an untrusted state.

A power controller can set the power state of a processor bridge based on which processor modules are in a communicative state. In addition, for a power state where selected processor modules are expected to be non-communicative, the power controller can set the supplied voltage to have a reduced voltage guard band as compared to other power states. These power management techniques can reduce the power consumed by the processor.

An SOC implements a security enclave processor (SEP). The SEP may include a processor and one or more security peripherals. The SEP may be isolated from the rest of the SOC (e.g. one or more central processing units (CPUs) in the SOC, or application processors (APs) in the SOC). Access to the SEP may be strictly controlled by hardware. For example, a mechanism in which the CPUs/APs can only access a mailbox location in the SEP is described. The CPU/AP may write a message to the mailbox, which the SEP may read and respond to. The SEP may include one or more of the following in some embodiments: secure key management using wrapping keys, SEP control of boot and/or power management, and separate trust zones in memory.

Various embodiments described herein relate to apparatus for executing software in a secure computing environment. A secure processor can be used and configured to request a context swap from a first context to a second context when switching execution from a first portion of software to a second portion of software. A context manager, which can be in communication with the secure processor, can be configured to receive and initiate a requested context swap. A trust vector verifier, which can be in communication with the secure processor and the context manager, can be configured to load a trust vector descriptor upon command from a context manager.

The present invention provides an acrylic resin composition containing a polycrystal of colloidal particles of silicon oxide in an acrylic resin that is formed by curing an acrylic monomer liquid at room temperature and/or an acrylic oligomer liquid at room temperature, wherein a mean distance between the colloidal particles in the polycrystal is 140 to 330 nm. The size of the single crystal that constitutes the polycrystal can be controlled by adjusting the content of silicon oxide and/or the additive amount of impurities. An architectural material, a fashion accessory, and an optical material are provided that are formed by using the acrylic resin composition.

Method and apparatus for centrifugal blood component separation including temperature sensing in each of a plurality of separation cells. The temperature of unit of bloods over time is recorded. If the temperature of any of the units exceeds a pre-determined maximum, portions of the blood separation device may be cooled. A controller may determine which of the units to process first, generally proceeding from the warmest unit to the coolest. The order of unit processing may be changed during processing. The detected temperature may be used to calibrate a pressure sensor used to predict the volume of a component separated from a composite fluid by predicting the volume of the composite fluid from sensed pressure and predicting the volume of other separated components from sensed movement of the other components to collection bags.

An apparatus for separating at least two discrete volumes of a composite liquid into components, comprising a valve design that facilitates loading and unloading of sets of blood bags. The valves comprise a jaw mounted on a shaft, the jaw being adapted to apply radio frequency energy to seal a tube, a stepper motor section, and at least two position sensors. The valve sections are mounted on an upper plate, and the stepper motor sections are mounted on a lower plate. A main radio frequency coil is selectively electrically coupled to each of the valves through a multiplexing switch.

The present invention relates to a centrifuge and a method for cooling a centrifuge. The centrifuge according to the invention includes a cooling device which is improved in that its required installation space is reduced such that the centrifuge can be of a more compact design with the centrifugation capacity remaining unchanged, or the centrifugation capacity can be increased with the installation space remaining unchanged. Further, the number of components can be reduced and thus cost and assembly time can be saved.

Method and Apparatus for predicting the volume of a component separated from a composite fluid by predicting the volume of the composite fluid from sensed pressure and predicting the volume of other separated components from sensed movement of the other components to collection bags.

A label has a water dissolvable or water dispersible paper with a coating of a type which can be printed with direct thermal printing. The label is produced by passing a length of such paper with a freshly applied coating of the above type through an oven for drying before the coating has an opportunity to deteriorate the surface of the paper.

Methods and apparatuses for activating colorant in selected regions of an article in which the colorant is incorporated are described. The colorant activation can create various desired visual aspects.

A method (and system) of emulation in a multiprocessor system, includes performing an emulation in which a host multiprocessing system of the multiprocessor system supports a weak consistency model, and the target multiprocessing system of the multiprocessor system supports a strong consistency model.

A combustor apparatus is provided, comprising a mixing arrangement for mixing a carbonaceous fuel with enriched oxygen and a working fluid to form a fuel mixture. A combustion chamber is at least partially defined by a porous perimetric transpiration member, at least partially surrounded by a pressure containment member. The combustion chamber has longitudinally spaced apart inlet and outlet portions. The fuel mixture is received by the inlet portion for combustion within the combustion chamber at a combustion temperature to form a combustion product. The combustion chamber directs the combustion product longitudinally toward the outlet portion. The transpiration member is configured to substantially uniformly direct a transpiration substance therethrough toward the combustion chamber, such that the transpiration substance is directed to flow helically about the perimeter and longitudinally between the inlet and outlet portions, for buffering interaction between the combustion product and the transpiration member. Associated systems are also provided.

A dissolution generator includes: an upright housing; a screen assembly extending across an interior of the housing, and configured to support a column of powder thereabove; a spray nozzle disposed below the screen assembly and directed towards the screen assembly; and a pressure mechanism disposed above the screen assembly, and configured to apply a substantially constant downward pressure.

A magnetized nut for fastening a compressor wheel of an exhaust turbocharger to a turbo shaft. The nut has a base body made of a non-magnetic material forming a hollow space for accommodating a magnetic material, and a method for the production of the magnetized nut. In order to provide a magnetized nut that is produced in a simple and cost-effective manner and ensures as equal a distribution of mass as possible with regard to the rotational axis of the nut, the magnetic material is introduced into the hollow space using injection molding.

A servo processor for an optical disk drive is provided that includes: an analog-to-digital converter for converting versions of photodetector output signals into digital signals; and a digital signal processor configured to receive the digital signals, the digital signal processor being further configured to determine a focus error signal (FES) and a tracking error signal (TES) from the digital signals, the digital signal processor being further configured to process TES and FES through servo algorithms to produce tracking and focus control signals.

Devices and methods for implantation at a native mitral valve. One embodiment of the device includes a valve support having a first region and a second region, and anchoring member having a longitudinal dimension with a first portion configured to contact tissue at the non-circular annulus, a second portion configured to be attached to the valve support, and a lateral portion transverse to the longitudinal dimension between the first portion and the second portion. The anchoring member and the valve support are configured to move from a low-profile configuration to an expanded configuration in which the first portion of the anchoring member at least partially adapts to the non-circular annulus of the native mitral valve and a shape of the first region of the valve support is at least partially independent of a shape of the first portion of the anchoring member.

In a scroll compressor of the present invention, a fixed scroll 11 and an orbiting scroll 12 are meshed with each other such that spiral laps of the fixed scroll 11 and the orbiting scroll 12 inwardly face each other, an Oldham ring 26 is provided between the main bearing member 19 and the orbiting scroll 12, and a key portion of the Oldham ring 26 is inserted into a key groove 19a of the main bearing member 19. Grooves 19b are formed in Oldham ring 26 sliding surfaces on both sides of the key groove 19a. According to this configuration, the Oldham ring 26 and the main bearing member 19 can be restrained from coming into contact with each other in the vicinity of the bearing key groove 19a, and restrained from vibrating, and it is possible to provide an inexpensive scroll compressor of low noise.

Apparatus, and an associated method, for generating a trouble ticket related to an IT incident. When an IT incident occurs, a worklog is formed by a reporter that enters information associated with the incident. Successive inputs, made by appropriate personnel, are made to update the status of the incident. A table-of-contents is formed, associated with the collection of entries of information. And, each entry of information is categorized, to identify the entry by an associated category.

The present invention relates to a process to dissolve plutonium or a plutonium alloy, by placing it in contact with an aqueous dissolution mixture, wherein said dissolution mixture comprises nitric acid, a carboxylic acid with complexing properties with respect to plutonium, and a compound comprising at least one —NH2 radical such as urea. The invention also relates to a process to convert plutonium or a plutonium alloy into plutonium oxide and to manufacture nuclear fuel from said oxide.The invention particularly applies to the dismantling of plutonium contained in nuclear weapons with a view to its use in civilian nuclear reactors, particularly in the form of MOX fuel.

The present invention concerns a process for dissolving ruthenium deposits that are present on a surface and a process for decontaminating the internal circuits of nuclear fuel reprocessing plants using the said dissolution process. The process according to the invention comprises bringing the said surface into contact with an aqueous solution of perruthenate, with the said aqueous solution having a pH equal to or greater than 12, so that the ruthenium is oxidised.

A method for measuring the neutron flux in the core of a nuclear reactor, the method including several steps recurrently performed at instants separated by a period, the method comprising at each given instant the following steps: acquiring a total signal by a cobalt neutron detector placed inside the core of the reactor; assessing a calibration factor representative of the delayed component of the total signal due to the presence of cobalt 60 in the neutron detector; assessing a corrected signal representative of the neutron flux at the detector from the total signal and from the calibration factor; assessing a slope representative of the time-dependent change of the calibration factor between the preceding instant and the given instant; the calibration factor at the given instant being assessed as a function of the calibration factor assessed at the preceding instant, of the slope, and of the time period separating the given instant from the preceding instant.

A location aware user interface on a wireless handset is described. The location aware user interface comprises a location module configured to transmit a location message to a remote server via a network. The remote server is configured to determine whether the wireless handset is within a geofence. The user interface further comprises a display module configured to display at least one content item associated with the geofence. The user interface also comprises an input module configured to receive a user-created content item and transmit the received user-created content item to the remote server. The remote server is configured to associate the content item with the geofence in which the wireless handset is located.