1 Iraqi Dinar = 0.0424 Philippine Peso

1 Cayman Islands Dollar = 60.5778 Philippine Peso

1 Swiss Franc = 52.0041 Philippine Peso

1 CFA Franc BCEAO = 0.0835 Philippine Peso

1 Vietnamese Dong = 0.0022 Philippine Peso

1 Macedonian Denar = 0.8886 Philippine Peso

1 Zambian Kwacha = 0.0097 Philippine Peso

1 South Korean Won = 0.0414 Philippine Peso

1 Jordanian Dinar = 71.1694 Philippine Peso

1 Lebanese Pound = 0.0334 Philippine Peso

1 Bahraini Dinar = 133.5214 Philippine Peso

1 Chilean Peso = 0.0611 Philippine Peso

1 Maldivian Rufiyaa = 3.257 Philippine Peso

1 Malaysian Ringgit = 11.6508 Philippine Peso

1 Nicaraguan Cordoba Oro = 1.4677 Philippine Peso

1 Netherlands Antillean Guilder = 28.1278 Philippine Peso

1 Estonian Kroon = 3.5404 Philippine Peso

1 Danish Krone = 7.3384 Philippine Peso

1 Fiji Dollar = 22.4119 Philippine Peso

1 New Zealand Dollar = 30.9937 Philippine Peso

1 Croatian Kuna = 7.2774 Philippine Peso

1 Peruvian Nuevo Sol = 14.8557 Philippine Peso

1 Dominican Peso = 0.9174 Philippine Peso

1 Papua New Guinean Kina = 14.7199 Philippine Peso

1 Brunei Dollar = 35.7294 Philippine Peso

Last year, I wrote a blog post entitled Modeling Oscillators with Arbitrary Phase Noise Profiles . We now have an easier way to do this. Starting in MMSIM 13.1 , you can specify the phase noise as an instance parameter in Spectre sources, including...(read more)

The other day, I happened to sneak out some time for myself after having sent the kids to play in the neighborhood park. I made myself a hot cup of coffee and settled on the couch hoping to enjoy the silence in the house. But was it really ...(read more)

Curious about what’s going on behind the scenes with verification? Bernard Murphy, Jim Hogan, and our own Paul Cunningham are on the case with the “Innovation in Verification” blog stream over at semiwiki.com. Every month, this trio reviews a newly-published paper in academia that pertains to verification and discusses its implications. Be sure to stop by—it’s a great place to see what might be coming down the pipeline someday.

This month, they discuss the implications of metamorphic testing. The purpose of metamorphic testing is to define a verification approach where is there is no “golden reference.” This situation comes up a lot now as designs grow in complexity, and it begs the question: “how does one know the design is verified if there is no standard to compare to?”. Metamorphic testing addresses the problem of not having a “gold standard” to compare to by comparing the results of related tests instead. The paper reviewed by this team used metamorphic testing to study methods of managing JavaScript tags.

Paul saw this as a valuable new class of coverage. Metamorphic testing represents a way to create better distribution analyses through understanding the relationships among tests. This can reveal critical-but-complex issues that traditional verification methods may overlook. He saw this as an emerging class of coverage that new verification tools could be built around. Paul asserted that a future metamorphic-testing-based tool’s main contribution to the field of verification would be to better analyze noisy performance results where the noise is multi-modal. It could be useful in detecting race conditions and similar hard-to-debug anomalies. Paul also sees metamorphic testing as ripe for ML techniques. Overall—Paul sees a bright future for metamorphic testing in verification.

Jim is reminded of Solido and Spice—these metamorphic testing capabilities are “more than just a feature”—they might be a product. Maybe even a whole new class of verification tools, as Paul said.

Bernard says that this topic is “too rich to address in one blog”, so be sure to head over to the post to see more of what the future has in store for verification.

Key Findings:  Nearly 100% of SoCs are mixed-signal to some extent.  Every one of these could benefit from the use of a metrics-driven unified verification methodology for mixed-signal (MD-UVM-MS), but the modeling step is the biggest hurdle to overcome.  Without the magical models, the process breaks down for lack of performance, or holes in the chip verification.

In the last installment of The Low Road, we were at the mixed-signal verification party. While no one talked about it, we all saw it: The party was raging and everyone was having a great time, but they were all dancing around that big elephant right in the middle of the room. For mixed-signal verification, that elephant is named Modeling.

To get to a fully verified SoC, the analog portions of the design have to run orders of magnitude faster than the speediest SPICE engine available. That means an abstraction of the behavior must be created. It puts a lot of people off when you tell them they have to do something extra to get done with something sooner. Guess what, it couldn’t be more true. If you want to keep dancing around like the elephant isn’t there, then enjoy your day. If you want to see about clearing the pachyderm from the dance floor, you’ll want to read on a little more….

Figure 1: The elephant in the room: who’s going to create the model?

 Whose job is it?

Modeling analog/mixed-signal behavior for use in SoC verification seems like the ultimate hot potato.  The analog team that creates the IP blocks says it doesn't have the expertise in digital verification to create a high-performance model. The digital designers say they don’t understand anything but ones and zeroes. The verification team, usually digitally-centric by background, are stuck in the middle (and have historically said “I just use the collateral from the design teams to do my job; I don’t create it”).

If there is an SoC verification team, then ensuring that the entire chip is verified ultimately rests upon their shoulders, whether or not they get all of the models they need from the various design teams for the project. That means that if a chip does not work because of a modeling error, it ought to point back to the verification team. If not, is it just a “systemic error” not accounted for in the methodology? That seems like a bad answer.

That all makes the most valuable guy in the room the engineer, whose knowledge spans the three worlds of analog, digital, and verification. There are a growing number of “mixed-signal verification engineers” found on SoC verification teams. Having a specialist appears to be the best approach to getting the job done, and done right.

So, my vote is for the verification team to step up and incorporate the expertise required to do a complete job of SoC verification, analog included. (I know my popularity probably did not soar with the attendees of DVCON with that statement, but the job has to get done).

It’s a game of trade-offs

The difference in computations required for continuous time versus discrete time behavior is orders of magnitude (as seen in Figure 2 below). The essential detail versus runtime tradeoff is a key enabler of verification techniques like software-driven testbenches. Abstraction is a lossy process, so care must be taken to fully understand the loss and test those elements in the appropriate domain (continuous time, frequency, etc.).

Figure 2: Modeling is required for performance

AFE for instance

The traditional separation of baseband and analog front-end (AFE) chips has shifted for the past several years. Advances in process technology, analog-to-digital converters, and the desire for cost reduction have driven both a re-architecting and re-partitioning of the long-standing baseband/AFE solution. By moving more digital processing to the AFE, lower cost architectures can be created, as well as reducing those 130 or so PCB traces between the chips.

There is lots of good scholarly work from a few years back on this subject, such as Digital Compensation of Dynamic Acquisition Errors at the Front-End of ADCS and Digital Compensation for Analog Front-Ends: A New Approach to Wireless Transceiver Design.

Figure 3: AFE evolution from first reference (Parastoo)

The digital calibration and compensation can be achieved by the introduction of a programmable solution. This is in fact the most popular approach amongst the mobile crowd today. By using a microcontroller, the software algorithms become adaptable to process-related issues and modifications to protocol standards.

However, for the SoC verification team, their job just got a whole lot harder. To determine if the interplay of the digital control and the analog function is working correctly, the software algorithms must be simulated on the combination of the two. That is, here is a classic case of inseparable mixed-signal verification.

So, what needs to be in the model is the big question. And the answer is, a lot. For this example, the main sources of dynamic error at the front-end of ADCs are critical for the non-linear digital filtering that is highly frequency dependent. The correction scheme must be verified to show that the nonlinearities are cancelled across the entire bandwidth of the ADC. 

This all means lots of simulation. It means that the right level of detail must be retained to ensure the integrity of the verification process. This means that domain experience must be added to the list of expertise of that mixed-signal verification engineer.

Back to the pachyderm

There is a lot more to say on this subject, and lots will be said in future posts. The important starting point is the recognition that the potential flaw in the system needs to be examined. It needs to be examined by a specialist.  Maybe a second opinion from the application domain is needed too.

So, put that cute little elephant on your desk as a reminder that the beast can be tamed.

Steve Carlson

Related stories

- It’s Late, But the Party is Just Getting Started

visit News18 Urdu for latest news, breaking news, news headlines and updates from Jyotiba Phoole Nagar on politics, sports, entertainment, cricket, crime and more.

કિમ જોંગ અને તેમના બે બોડી ડબલ એક મિસાઇલ લોન્ચ દરમિયાન નજરે પડ્યા હતા.

આ ઠંડીના વાતાવરણ વચ્ચે એક શ્વાનની તસવીર સોશિયલ મીડિયા પર વાયરલ થઈ રહી છે, જે લોકોનું હૃદય ઓગાળવા માટે પૂરતી છે.

આ વખતની રમત પ્રતિયોગિતામાં અમેરિકન યુવતીઓની રમત આકર્ષનું કેન્દ્ર રહી હતી

મહિલા બાથરૂમ ગઇ તો સિંક પર હતો 8 ફૂટનો અજગર

કોટાના નિતિન શાકાહારી જૈન પરિવારના છે એટલે લગ્નની દાવતમાં કંઈ જ માંસાહારી કે નોન વેજિટેરિયન બની શકે નહીં. એટલે મોટો પ્રશ્ન એ હતો કે તાઈવાનથી આવેલા મહેમાનોને એવું શું પિરસવામાં આવે કે દાવતની લીજ્જત માણી શકે અને માંસાહારની ઉણપ પણ ન લાગે.

આ મગર ઈન્ડોનેશિયાના સુલાવેસી પ્રાંતના પાલૂ શહેરમાં છે. તેના ગળામાં આ બાઈકનું ટાયર છેલ્લા ચાર વર્ષ એટલે કે 2016થી ફસાયું છે. પરંતુ હજી સુધી કોઈએ તેને કાઢવાની હિંમત નથી કરી.

આ યુવકો લૂણકરણસર વિસ્તારના લોકોને પરેશાન કરવા, યુવતીઓ અને મહિલાઓ સાથે અભદ્ર વર્તન કરવાનો આરોપ છે. કિન્નર બનીને બંને યુવકો લોકોને પરેશાન કરીને રુપિયા પડાવી રહ્યા હતા.

ઘડિયાળની આ તસવીર કેમ વાયરલ થઈ તેનું કારણ જાણશો તો તમે પણ વખાણ કર્યા વગર નહીં રહી શકો

આ 6 વર્ષની બિલાડી ઇન્સ્ટાગ્રામ પર ખૂબ જ પોપ્યુલર છે.

આ ઘટના વાંચી તમને પણ થશે કે શું પ્રાણીઓને પણ આટલી સમજ પડતી હશે?

એક સંગ્રહાલયમાં સીરિયલ કિલર Peter Kurtenનું કાપેલું માથું રાખવામાં આવ્યું છે.

PhonePeના 20 કરોડ યૂઝર્સનો મળી શકશે રોકાણની તક, આવી રીતે કરો શુભારંભ

visit News18 Urdu for latest news, breaking news, news headlines and updates from Imphal West on politics, sports, entertainment, cricket, crime and more.

visit News18 Urdu for latest news, breaking news, news headlines and updates from Imphal East on politics, sports, entertainment, cricket, crime and more.

visit News18 Urdu for latest news, breaking news, news headlines and updates from Champhai on politics, sports, entertainment, cricket, crime and more.

visit News18 Urdu for latest news, breaking news, news headlines and updates from Phek on politics, sports, entertainment, cricket, crime and more.

visit News18 Urdu for latest news, breaking news, news headlines and updates from Phulbani on politics, sports, entertainment, cricket, crime and more.